ARM Corstone SSE-300 User manual

Arm® Corstone™ SSE-300 with Cortex®-M55
and Ethos™-U55 : Example Subsystem for MPS3
Revision: C
Application Note AN547
Non-Confidential
Issue C
Copyright © 2020, 2021 Arm Limited (or its affiliates).
All rights reserved.
DAI 0547C

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
Example Subsystem for MPS3 - Application Note AN547
DAI 0547C
Issue C
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Non-Confidential
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Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : Example
Subsystem for MPS3
Application Note AN547
Copyright ©2020, 2021 Arm Limited (or its affiliates). All rights reserved.
Release information
Document history
Issue
Date
Confidentiality
Change
A
30 November 2020
Confidential
First Issue
B
29 January 2021
Non-Confidential
Confidentiality status changed to Non-Confidential
C
30 June 2021
Non-Confidential
Document title change,
Added selftest support for DS 2020.1
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Example Subsystem for MPS3 - Application Note AN547
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LICENCE GRANTS
THE END USER LICENCE AGREEMENT FOR THE ARM SYSTEM OR SUBSYSTEM FOR AN ARM FPGA
PROTOTYPING BOARD (“THE LICENCE”), LES-PRE-21902, DEFINES THE LICENCE GRANTS.
DELIVERABLES
Part A
Hardware Binaries:
Encrypted FPGA bitstream file containing various the Arm technology including:
SSE-300 Subsystem
Cortex-M55 Processor
Ethos-U55 Embedded ML Inference processor.
Software Binaries:
Motherboard Configuration Controller binary (mbb_vxxx.ebf), including Keil®USB and SD card drivers, and
Analog Devices FMC EEPROM reader.
selftest binary (an547_st.axf) for Cortex-M55 in Corstone™ SSE-300.
Documentation:
Documentation, provided as PDF
Part B
Text configuration files (.txt) in the <install_dir>/Boardfiles/MB/HBI0309x/ directory:
/board.txt
/AN547/an547_vx.txt
/AN547/images.txt
Part C
None
Part D
None

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
Example Subsystem for MPS3 - Application Note AN547
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Contents
1 Introduction........................................................................................................................................................... 8
1.1 Intended audience.................................................................................................................................................... 8
1.2 Conventions ............................................................................................................................................................... 8
1.2.1 Glossary.................................................................................................................................................................... 8
1.2.2 Typographical conventions ............................................................................................................................... 9
1.3 Additional reading.................................................................................................................................................... 9
1.4 Feedback....................................................................................................................................................................10
1.4.1 Feedback on this product.................................................................................................................................10
1.4.2 Feedback on content .........................................................................................................................................10
1.4.3 Other information ..............................................................................................................................................11
2 Preface ..................................................................................................................................................................12
2.1 Purpose of this application note........................................................................................................................12
2.2 Terms and abbreviations .....................................................................................................................................12
2.3 Arm IP version details ...........................................................................................................................................13
2.4 Encryption key.........................................................................................................................................................13
3 Overview ..............................................................................................................................................................14
3.1 System block diagram ...........................................................................................................................................14
3.2 SSE-300 Configuration.........................................................................................................................................15
3.2.1 Render Settings ...................................................................................................................................................15
3.2.2 Subsystem static input values.........................................................................................................................17
3.3 SIE-300 Components............................................................................................................................................18
3.4 SIE-200 Components............................................................................................................................................18
3.5 CoreLink XHB-500.................................................................................................................................................18
3.6 Memory Protection ...............................................................................................................................................18
3.7 Memory Map Overview .......................................................................................................................................19
3.8 Expansion System peripherals...........................................................................................................................22
3.8.1 Manager Peripheral Expansion Low Latency Interface Memory Map (HMSTEXPPILL)...........22
3.8.2 MSTEXPPIHL Peripheral Map........................................................................................................................25
3.9 FPGA Utilization.....................................................................................................................................................27
3.9.1 Total design utilization......................................................................................................................................27
4 Programmers Model .........................................................................................................................................28

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4.1 ITCM ...........................................................................................................................................................................28
4.2 FPGA SRAM .............................................................................................................................................................28
4.3 DTCM .........................................................................................................................................................................28
4.4 QSPI.............................................................................................................................................................................28
4.5 DDR4 ..........................................................................................................................................................................28
4.6 AHB GPIO .................................................................................................................................................................29
4.7 SPI ................................................................................................................................................................................29
4.8 SBCon (I2C) ...............................................................................................................................................................29
4.9 UART...........................................................................................................................................................................30
4.10 Color LCD parallel interface ............................................................................................................................30
4.11 Ethernet ..................................................................................................................................................................31
4.12 USB............................................................................................................................................................................31
4.13 RTC ...........................................................................................................................................................................31
4.14 Audio I2S..................................................................................................................................................................32
4.15 Audio Configuration ...........................................................................................................................................33
4.16 FPGA system control and I/O..........................................................................................................................34
4.17 Serial Configuration Controller (SCC)..........................................................................................................35
5 Clock architecture .............................................................................................................................................37
5.1 Clocks..........................................................................................................................................................................37
5.1.1 Source clocks........................................................................................................................................................37
5.1.2 Generated clocks ................................................................................................................................................37
5.1.3 SSE-300 clocks.....................................................................................................................................................38
6 FPGA Secure Privilege Control......................................................................................................................39
7 Interrupt Map......................................................................................................................................................43
7.1 UART Interrupts .....................................................................................................................................................45
8 Shield Support.....................................................................................................................................................46
9 ZIP Bundle Description ....................................................................................................................................48
9.1 Overall Structure....................................................................................................................................................48
9.2 Bundle Directory Tree/Structure .....................................................................................................................48
10 Board Revision And Support........................................................................................................................50
10.1 Identifying the MPS3 board revision ............................................................................................................50
10.2 Bundle support for specific MPS3 board revisions..................................................................................50

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11 Using AN547 on the MPS3 Board...............................................................................................................51
11.1 Pre-Requisites.......................................................................................................................................................51
11.2 Loading a prebuilt image onto the MPS3 Board........................................................................................51
11.3 UART Serial Ports ................................................................................................................................................52
11.4 UART Serial Port Terminal Emulator Settings...........................................................................................52
11.5 MPS3 USB Serial port drivers for Windows...............................................................................................52
11.6 MCC Memory mapping......................................................................................................................................53
12 Software.............................................................................................................................................................54
12.1 Rebuilding software............................................................................................................................................54
12.2 Loading software on the MPS3 board ..........................................................................................................54
13 Debug..................................................................................................................................................................55
13.1 Debug Connectivity ............................................................................................................................................55
13.2 Debug support for Keil MDK...........................................................................................................................55
13.3 Trace support for Keil MDK.............................................................................................................................57
13.4 Debug and Trace support for Arm Development Studio .......................................................................58
13.4.1 Establishing a Debug Session.......................................................................................................................58
13.4.2 Trace in Debug session...................................................................................................................................62

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1Introduction
1.1 Intended audience
This application note document is written for experienced hardware, System-on-Chip (SoC) and
software engineers who might or might not have experience with Arm products. Such engineers
typically have experience in writing Verilog and of performing synthesis but might have limited
experience of integrating and implementing Arm products.
1.2 Conventions
The following subsections describe conventions used in Arm documents.
1.2.1 Glossary
The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those
terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning
differs from the generally accepted meaning.
See the Arm Glossary for more information: https://developer.arm.com/glossary.

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1.2.2 Typographical conventions
Convention
Use
italic
Introduces citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for
terms in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program
names, and source code.
monospace bold
Denotes language keywords when used outside example code.
monospace
underline
Denotes a permitted abbreviation for a command or option. You can enter the underlined
text instead of the full command or option name.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code
fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in
the Arm®Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC,
UNKNOWN, and UNPREDICTABLE.
This represents a recommendation which, if not followed, might lead to system failure or
damage.
This represents a requirement for the system that, if not followed, might result in system
failure or damage.
This represents a requirement for the system that, if not followed, will result in system
failure or damage.
This represents an important piece of information that needs your attention.
This represents a useful tip that might make it easier, better or faster to perform a task.
This is a reminder of something important that relates to the information you are reading.
1.3 Additional reading
This document contains information that is specific to this product. See the following documents for
other relevant information:

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
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Document name
Document ID
Licensee only
Arm® MPS3 FPGA Prototyping Board Technical
Reference Manual
100765
No
Arm® Corstone™ SSE-300 Example Subsystem
Technical Reference Manual
101773
No
Arm® Corstone™ SSE-300 Example Subsystem
Configuration and Integration Manual
101774
Yes
Arm® Ethos™-U55 NPU Technical reference manual
101885
No
Arm® CoreLink™ SIE-200 System IP for Embedded
Technical Reference Manual
DDI 0571
No
Arm® CoreLink™ SIE-300 AXI5 System IP for
Embedded Technical Reference Manual
101526
No
Arm® Cortex®-M System Design Kit Technical
Reference Manual
DDI 0479
No
Arm® CoreLink™ XHB-500 Bridge Technical
Reference Manual
101375
No
MCBQVGA-TS-Display-v12 –Keil MCBSTM32F200
display board schematic
-
No
Arm® MPS3 FPGA Prototyping Board Getting
Started Guide
-
No
Table 1-1 : Arm Publications
1.4 Feedback
Arm welcomes feedback on this product and its documentation.
1.4.1 Feedback on this product
If you have any comments or suggestions about this product, contact your supplier and give:
•The product name.
•The product revision or version.
•An explanation with as much information as you can provide. Include symptoms and diagnostic
procedures if appropriate.
1.4.2 Feedback on content
If you have comments on content, send an email to [email protected]om and give:

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
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•The title Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : Example Subsystem
for MPS3 Application Note AN547.
•The number DAI 0547C.
•If applicable, the page number(s) to which your comments refer.
•A concise explanation of your comments.
Arm also welcomes general suggestions for additions and improvements.
1.4.3 Other information
•Arm Documentation, https://developer.arm.com/documentation/
•Arm Technical Support Knowledge Articles, https://www.arm.com/support/technical-support
•Arm Support, https://www.arm.com/support
•Arm Glossary, https://developer.arm.com/documentation/aeg0014/g
The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary
does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.
Arm tests the PDF only in Adobe Acrobat and Acrobat Reader and cannot guarantee the quality of
the represented document when used with any other PDF reader.

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2Preface
2.1 Purpose of this application note
This application note describes the features and functionality of the AN547 Soft Macrocell Model (SMM), or
AN547 subsystem. The AN547 SMM is an FPGA image that is a Single Cortex-M55 FPGA implementation of
the Corstone SSE-300 with Cortex-M55 and Ethos™-U55 Example Subsystem. The example subsystem uses
SIE-300 and SIE-200 components with CMSDK peripherals to provide a reference design.
2.2 Terms and abbreviations
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
BRAM
Block Random Access Memory
CMSDK
Cortex-M System Design Kit
DMA
Direct Memory Access
DTCM
Data Tightly Coupled Memory
EAM
Exclusive Access Controller
FPGA
Field Programmable Gate Array
IDAU
Implementation Defined Attribution Unit
ITCM
Instruction Tightly Coupled Memory
KB
Kilobyte
MB
Megabyte
MCC
Motherboard Configuration Controller
MPC
Memory Protection Controller
MSC
Manager Security Controller
PPC
Peripheral Protection Controller
RAM
Random Access Memory
RAZ/WI
Read As Zero/Write Ignored
RTC
Real Time Clock
RTL
Register Transfer Level
SCC
Serial Configuration Controller
SMM
Soft Macrocell Model system implemented as an
FPGA image and described in this AN
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
TPIU
Trace Port Interface Unit
TRM
Technical Reference Manual

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2.3 Arm IP version details
The following IP packages have been used in this Product.
Version
Description
r0p0
Arm® Corstone™ SSE-300
The Arm® Corstone™ SSE-300 Example Subsystem is a collection of pre-assembled
elements to use as the basis of an Internet of Things (IoT) System on Chip (SoC).
r1p0
Arm® Ethos™-U55 NPU
The Arm® Ethos™-U55 is a Neural Processing Unit (NPU) which improves the inference
performance of neural networks.
r1p0
Arm® CoreLink™ SIE-300
The SIE-300 AXI5 System IP for Embedded provides a set of configurable AXI5 security-
aware components.
r3p1
Arm® CoreLink™ SIE-200
The CoreLink SIE-200 System IP for Embedded product is a collection of interconnect,
peripheral, and TrustZone® controller components for use with a processor that complies
with the ARMv8-M processor architecture.
BP210
Cortex-M System Design Kit
Full version of the design kit supporting Cortex-M0, Cortex-M0 DesignStart®, Cortex-
M0+, Cortex-M3 and Cortex-M4. Also contains the AHB Bus Matrix and advanced AHB
components.
r1p3-00rel1
Arm® PrimeCell Synchronous Serial Port (PL022)
Arm PrimeCell Synchronous Serial Port
Figure 2-1 : Arm IP versions
2.4 Encryption key
Arm supplies the MPS3 prototyping board with a decryption key programmed into the FPGA. This key is
needed to enable loading of prebuilt encrypted images.
Note
The FPGA programming file that is supplied as part of the bundle is encrypted.
Caution
A battery supplies power to the key storage area of the FPGA. Any keys stored in the FPGA might be lost when
battery power is lost. If this happens you must return the board to Arm for reprogramming of the key.

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3Overview
The AN547 SMM is a Single Cortex-M55 FPGA implementation of the Corstone SSE-300 with Cortex-M55 and
Ethos-U55 Example Subsystem. The example subsystem uses SIE-300 and SIE-200 components with CMSDK
peripherals to provide a reference design.
3.1 System block diagram
The following high-level block diagram shows the full MPS3 FPGA System :
mps3_fpga_top
fpga_specific
mps3_fpga_system
mps3_fpga_user mps3_user_periph_wrapper mps3_user_ahb_subsystemmps3_user_apb_subsystem_1mps3_user_apb_subsystem_0
mps3_peripheral_mem_wrapper
mps3_ddr_peripheral_subsys
mps3_system_core mps3_core_periph_wrapper
fpga_iot_wrapper
mps3_mem_preload
mps3_core_periph_wrapper
mps3_core_ahb_subsystemmps3_core_apb_subsystem_1mps3_core_apb_subsystem_0
mps3_core_mem_wrapper
mps3_core_mem_mpc_ppc
Trace
Port JTAG Port
Ethernet
LCD
Shield/
PMOD 0
& 1
TSC Audio Switches
Buttons
LEDs
ADC
QSPI flash
MCC
DDR4
AXI5
MPC AHB to
APB
APB PPC APB PPC
AHB to APB AHB PPC
AXI5
MPC
APBAPB AHB5 to
AHB-lite
NIC400
AXI5
MPC
APB
APB
SMB TO
AHB
clocks resets
mps3_bram_qspi_memsubsys
Default
Slave
AHB
GPIO x4
UART
x6
SPI x3
(master)
Audio
I2Sx2 FPGA
IO regs
CharLCD
SCC
I2C x5
x2
Shield
NIC400
Xilinx
QSPI
XIP
x2
Shield
x2
Shield
Uart x2
SPI x2
I2C x2
Xilinx
QSPI
Write
AXI 4AXI 4 AXI 4
AXI4
AHB5 to
extmem
Address
Decode
Address
Decode
Address
Decode
Address
Decode
AXI 4
NIC400
AHB PPC
FPGA
SRAM Xilinx
MIG
CorstoneSSE-300
DMA
Pl081
AHB PPC
SIE-300 Component
SIE-200 Component
XHB-500 Component
NIC-400 Component
Xilinx IP
XHB AHB to AXI
NIC400
DMA
Pl081
DMA
Pl081
Address
Decode
External_masters
MSC
Ethos
- U55
IDAU MSCMSC IDAUIDAU
AHB5 Fabric
APB
AHB5 Fabric
XSLVEXPMI0 HSLVEXPMI1 HSLVEXPPILL HSLVEXPPIHL
XMSTEXPCODE XMSTEXPSRAM XMSTEXPDEV HMSTEXPPILL HMSTEXPPIHL
Debug
XSLVTCM
UART
UART
UART
UART x4
APB PPC
AHB5 Fabric
AHB to APB
Figure 3-1 : MPS3 System Overview

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3.2 SSE-300 Configuration
The following tables show the configuration settings of the SSE-300 subsystem in the AN547 SMM. See the Arm®
Corstone™ SSE-300 Example Subsystem Configuration and Integration Manual for full details of each configuration
option.
3.2.1 Render Settings
Configuration Define
SSE-300
Default Value
AN547 Value
NUMCPU
0
0
PILEVEL
1
1
CPU0TYPE
3
3
CPU1TYPE
0
0
CPU2TYPE
0
0
CPU3TYPE
0
0
NUMNPU
1
1
NPU0TYPE
1
1
NPU1TYPE
0
0
NPU2TYPE
0
0
NPU3TYPE
0
0
NPU0_NUM_MACS
128
128
NPU1_NUM_MACS
256
256
NPU2_NUM_MACS
32
32
NPU3_NUM_MACS
64
64
NUM_AXI_SLAVES_EXP_MI
2
2
NUM_AHB_SLAVES_EXP_PIHL
1
1
NUM_AHB_SLAVES_EXP_PILL
1
1
EXPLOGIC_PRESENT
1
1
VMMPCBLKSIZE
7
11
CPU0_INITNSVTOR_ADDR_INIT
0x00000000
0x00000000
CPU0EXPNUMIRQ
64
100
CPU0EXPIRQDIS
64b0
100b0
CPU0_EXP_IRQTIER
65b1
100b1
CPU0_INT_IRQTIER
32b1
32b1
CPU0_EXP_IRQ_PULSE_SPT_PRESENT
64b0
100b0
CPU0_EXP_IRQ_SYNC_TO_CPU_PRESENT
65b1
100b1
CPU0_EXP_IRQ_SYNC_TO_EWIC_PRESENT
65b1
100b1
CPU0_EXP_NMI_PULSE_SPT_PRESENT
0
0
CPU0_EXP_NMI_SYNC_TO_CPU_PRESENT
1
1
CPU0_EXP_NMI_SYNC_TO_EWIC_PRESENT
1
1
DEBUGLEVEL
0
2
CPU0_ITM_PRESENT
1
1
CPU0_ETM_PRESENT
2
1
CPU0_FPU_PRESENT
1
1
CPU0_MVE_CONFIG
2
2
SECEXT
1
1
CPU0_MPU_S
8
16
CPU0_MPU_NS
8
16

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CPU0_SAUDISABLE
0
0
CPU0_NUM_SAU_CONFIG
8
8
CPU0_DBGLVL
2
2
HASCPU0CPIF
1
0
CPU0_INSTR_CACHE_SIZE
0b01111
0b01111
CPU0_DATA_CACHE_SIZE
0b01111
0b01111
CPU0_IRQLVL
3
3
CPU0_ITGUBLKSZ
7
8
CPU0_DTGUBLKSZ
7
8
CPU0_RAR
1
1
CPU0_LOCKSTEP
0
0
CPU0_CFGITCMSZ
0b1001
0b1010
CPU0_CFGDTCMSZ
0b1001
0b1010
CPU0MCUROMADDR
0xE00FE
0xE00FE
CPU0MCUROMVALID
1
1
SOCVAR
0x0
0x0
SOCREV
0x0
0x0
SOCPRTID
0x7E0
0x7E0
SOCIMPLID
0x43B
0x43B
IMPLVAR
0x0
0x0
IMPLREV
0x0
0x0
IMPLPRTID
0x74A
0x74A
IMPLID
0x43B
0x43B
INITTCMEN
0b11
0b11
INITPAHBEN
1
1
LOCKDCAIC
0
0
TCM_MID_WIDTH
5
5
S_MID_WIDTH
5
6
TCM_ID_WIDTH
5
5
XS_ID_WIDTH
6
6
S_HMASTER_WIDTH
5
4
XOM_USER_SIGNAL_PRESENT
0
0
CPU0_PMC_PRESENT
0
0
NUMVMBANK
2
2
VMADDRWIDTH
18
21
HASCRYTO
0
0
HASCSS
0
0
LOGIC_RETENTION_PRESENT
0
0
NSMSCEXPRST
0xA5A5
0xA5A5
MPCEXPDIS
0x5A5A
0x5A5A
MSCEXPDIS
0x5A5A
0x5A5A
BRGEXPDIS
0x5A5A
0x5A5A
PERIPHPPCEXP3DIS
0x5A5A
0xFFFE
PERIPHPPCEXP2DIS
0x5A5A
0xF000
PERIPHPPCEXP1DIS
0x5A5A
0xFE00
PERIPHPPCEXP0DIS
0x5A5A
0x1FCC
MAINPPCEXP3DIS
0x5A5A
0x5A5A
MAINPPCEXP2DIS
0x5A5A
0x5A5A
MAINPPCEXP1DIS
0x5A5A
0xFFF1
MAINPPCEXP0DIS
0x5A5A
0xBE00

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
Example Subsystem for MPS3 - Application Note AN547
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PDCMQCHWIDTH
4
4
HASCPU0IWIC
0
0
CPU0CPUIDRST
0
0
COLDRESET_MODE
0
0
BUSPROT_PRESENT
0
0
ECC_PRESENT
0
0
CPU0_CTI_PRESENT
1
1
CFGBIGEND
0
0
CFGMEMALIAS
0b10000
0b10000
CPU0_INITECCEN
0
0
PERIPHERAL_INTERCONNECT_ARBITRATION_SCHEME
“round”
“round”
CPU0_CFGPAHBZE
0b010
0b010
CPU0_LOCKPAHB
1
1
PERFORM_CONFIGCHECK
1
1
Table 3-1 : SSE-300 Render Configuration Settings
3.2.2 Subsystem static input values
The SSE-300 subsystem in AN547 has several inputs which are tied off and therefore static, at the subsystem top
level. These are detailed in the below table.
Input
Tie Off Value
CPU0_INITSVTOR 1
25'h0200000
CPU0CFGFPU
1'b1
CPU0CFGMVE
2'b10
CPU0MPUNSDISABLE
1'b0
CPU0MPUSDISABLE
1'b0
CPU0CFGSSTCALIB
25'h0270FF
CPU0CFGNSSTCALIB
25'h0270FF
CPU0INITL1RSTDIS
1'b0
Table 3-2 : Subsystem static input values
CPU0_INITSVTOR is the value for INITSVTOR0RST specified in the SSE-300 TRM.

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
Example Subsystem for MPS3 - Application Note AN547
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3.3 SIE-300 Components
This system uses the following SIE-300 components:
•AXI5 Memory Protection Controller.
There are 3 MPCs implemented in the FPGA and these are configured with the following block sizes:
MPC
Block size
SRAM MPC
16KB
QSPI MPC
64KB
DDR4 MPC
1MB
3.4 SIE-200 Components
This system uses the following SIE-200 components:
•TrustZone AHB5 peripheral protection controller
•TrustZone AHB5 Manager security controller
•AHB5 bus matrix
•AHB5 to AHB5 synchronous bridge
•AHB5 to APB synchronous bridge
•TrustZone APB4 peripheral protection controller
•AHB5 default subordinate
3.5 CoreLink XHB-500
This system implements one CoreLink XHB-500, configured for AHB to AXI mode.
3.6 Memory Protection
The SIE-300 MPC, and SIE-200 PPC components can affect memory and I/O security management and must be
configured as required for your application. See Arm®SIE-200 System IP Technical Reference Manual and Arm®
CoreLink™ SIE-300 AXI5 System IP for Embedded Technical Reference Manual.

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
Example Subsystem for MPS3 - Application Note AN547
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3.7 Memory Map Overview
The following figure shows the AN547 memory map and how it relates to the Armv8-M reference memory map.
The figure includes IDAU security information for memory regions.
See the Arm® CoreLink™ SIE-200 System IP for Embedded Technical Reference Manual for more information.
SRAM
All accesses performed on
DTCM or M-AXI
CODE
All accesses performed on
ITCM or M-AXI
Peripheral
Instruction and data accesses
performed on P-AHB or M-AXI
External RAM
Instruction and data accesses
performed on M-AXI
External Device
Instruction and data accesses
performed on M-AXI
Private Peripheral Bus.
Local to Each CPU.
Vendor_SYS
0x0000_0000
0x2000_0000
0x4000_0000
0xE000_0000
0xE010_0000
0xFFFF_FFFF
0x6000_0000
0x8000_0000
0x5000_0000
QSPI (8MB)
0x2000_0000
0x2200_0000
Reserved
0x2800_0000
DTCM (4 x 128KB)
Reserved
FPGA SRAM (2MB)
0x3000_0000
Non-Secure Low Latency
Peripheral Region
Non-Secure High Latency
Peripheral Region
0x4800_0000
Secure High Latency
Peripheral Region
0x5800_0000
Private Peripheral Bus
Vendor_SYS
0xFFFF_FFFF
0xE010_0000
GPIO 0 0x4110_1000
GPIO 1 0x4110_2000
GPIO 2 0x4110_3000
GPIO 3 0x4110_4000
Reserved
I2C (Touch)
I2C (Audio Conf)
SPI ADC
SPI Shield0
SPI Shield1
I2C Shield0
I2C Shield1
Reserved
SCC
I2S Audio
FPGAIO
UART 0
UART 1
UART 2
UART Shield0
UART Shield1
UART 3
CLCD
Reserved
ETHERNET
QSPI XIP CONFIG
QSPI WRITE CONFIG
Reserved
RTC
0x4110_0000
0x4800_0000
0x4810_0000
0x4920_0000
0x4140_0000
0x4160_0000
0x4150_0000
USB
0x9000_0000
0xA000_0000
0xB000_0000
0xC000_0000
0xD000_0000
0x6000_0000 DDR 4
DDR 4
0x7000_0000
0x8000_0000
0xE000_0000
DDR 4
DDR 4
DDR 4
DDR 4
DDR 4
DDR 4
0x1E00_0000
0x0000_0000
Reserved
FPGA SRAM (2MB)
ITCM (512KB)
I2C DDR4 EEPROM
Reserved
Reserved
Arm®v8-M
Ref Memory map AN547 Memory map
0x0100_0000
QSPI (8MB)
Reserved
ITCM (512KB)
0x2100_0000
0x2880_0000
DTCM (4 x 128KB)
Reserved
Reserved
Secure Low Latency
Peripheral Region
Reserved
Subsystem Peripherals 0x4010_0000
0x4000_0000
USER AHB 0 0x4110_5000
USER AHB 1 0x4110_6000
USER AHB 2 0x4110_7000
USER AHB 3 0x4110_8000
0x4120_0000
DMA 0 0x4120_1000
DMA 1 0x4120_2000
DMA 2 0x4120_3000
DMA 3 0x4120_4000
Reserved
USER APB 0
USER APB 1
USER APB 2
USER APB 3
0x4170_1000
0x4170_2000
0x4170_3000
0x4170_4000
0x4170_0000
Reserved 0x4180_0000
0x4180_2000
0x4180_1000
0x4800_0000
0x5110_1000
0x5110_2000
0x5110_3000
0x5110_4000
0x5110_0000
0x5140_0000
0x5160_0000
0x5150_0000
0x5010_0000
0x5000_0000
0x5110_5000
0x5110_6000
0x5110_7000
0x5110_8000
0x5120_0000
0x5120_1000
0x5120_2000
0x5120_3000
0x5120_4000
0x5170_1000
0x5170_2000
0x5170_3000
0x5170_4000
0x5170_0000
0x5180_0000
0x5180_2000
0x5180_1000
0x5800_0000
Reserved
Non-Secure Low Latency Peripheral Region
Secure Low Latency Peripheral Region
Secure High Latency Peripheral Region
Non-Secure High Latency Peripheral Region
Subsystem Peripherals
USER APB
0x4920_1000
0x4920_2000
0x4920_3000
0x4920_4000
0x4920_5000
0x4920_6000
0x4920_7000
0x4920_8000
0x4920_9000
0x4930_0000
0x4930_1000
0x4930_2000
0x4930_3000
0x4930_4000
0x4930_5000
0x4930_6000
0x4930_7000
0x4930_8000
0x4930_9000
0x4930_A000
0x4930_B000
0x4930_C000
0x5000_0000
0x5800_0000
0x5810_0000
0x5920_0000
0x5920_1000
0x5920_2000
0x5920_3000
0x5920_4000
0x5920_5000
0x5920_6000
0x5920_7000
0x5920_8000
0x5920_9000
0x5930_0000
0x5930_1000
0x5930_2000
0x5930_3000
0x5930_4000
0x5930_5000
0x5930_6000
0x5930_7000
0x5930_8000
0x5930_9000
0x5930_A000
0x5930_B000
0x5930_C000
0x6000_0000
Internal SRAM (2 x 2MB)
Internal SRAM (2 x 2MB)
0x0E00_0000
0x1000_0000
0x1100_0000
0x3200_0000
0x3800_0000
0x4000_0000
0x3100_0000
0x3880_0000
Non-Secure Secure
Non-Secure Secure
PDM 0x4930_D000 0x5930_D000
0x4810_2000
U55 TIMING ADAPTER 0
U55 TIMING ADAPTER 1
Reserved
0x4810_3000
0x4810_4000
0x5810_2000
0x5810_3000
0x5810_4000
Figure 3-2 : Memory Map

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :
Example Subsystem for MPS3 - Application Note AN547
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The following table shows the memory map.
RO
W
ID
Address
Size
Region
Name
Description
Alias
with
Row ID
IDAU Region Values
From
To
Security
IDAU
ID
NSC
1
0x0000_0000
0x0007_FFFF
512KB
Code
ITCM3
5
NS
0
0
2
0x0008_0000
0x00FF_FFFF
15.5MB
Reserved
Reserved
3
0x0100_0000
0x011F_FFFF
2MB
Code
FPGA SRAM (2MB)1
7
4
0x0120_0000
0x0FFF_FFFF
238MB
Reserved
Reserved
5
0x1000_0000
0x100F_FFFF
512KB
Code
ITCM3
1
S
1
CODE
NSC
6
0x1010_0000
0x10FF_FFFF
15.5MB
Reserved
Reserved
7
0x1100_0000
0x111F_FFFF
2MB
Code
FPGA SRAM (2MB)1
3
8
0x1120_0000
0x1FFF_FFFF
238MB
Reserved
Reserved
9
0x2000_0000
0x2007_FFFF
512KB
SRAM
DTCM (4 x banks of 128KB)3
15
NS
2
0
10
0x2008_0000
0x20FF_FFFF
15.5MB
Reserved
Reserved
11
0x2100_0000
0x213F_FFFF
4MB
SRAM
Internal SRAM Area (SSE-
300 implements 2x2MB)3
17
12
0x2140_0000
0x27FF_FFFF
108MB
Reserved
Reserved
13
0x2800_0000
0x287F_FFFF
8MB
SRAM
QSPI (8MB)1
19
14
0x2880_0000
0x2FFF_FFFF
120MB
Reserved
Reserved
15
0x3000_0000
0x303F_FFFF
512KB
SRAM
DTCM (4 x banks of 128KB)3
9
S
3
RAM
NSC
16
0x3040_0000
0x30FF_FFFF
15.5MB
Reserved
Reserved
17
0x3100_0000
0x313F_FFFF
4MB
SRAM
Internal SRAM Area (SSE-
300 implements 2x2MB)3
11
18
0x3140_0000
0x37FF_FFFF
108MB
Reserved
Reserved
19
0x3800_0000
0x387F_FFFF
8MB
SRAM
QSPI (8MB)1
13
20
0x3880_0000
0x3FFF_FFFF
120MB
Reserved
Reserved
21
0x4000_0000
0x47FF_FFFF
128MB
Peripheral
Non-Secure Low Latency
Peripheral Region
23
NS
4
0
22
0x4800_0000
0x4FFF_FFFF
128MB
Peripheral
Non-Secure High Latency
Peripheral Region
24
NS
4
0
23
0x5000_0000
0x57FF_FFFF
128MB
Peripheral
Secure Low Latency
Peripheral Region
21
S
5
0
24
0x5800_0000
0x5FFF_FFFF
128MB
Peripheral
Secure High Latency
Peripheral Region
22
S
5
0
25
0x6000_0000
0x6FFF_FFFF
256MB
External RAM
DDR41
NS
6
0
26
0x7000_0000
0x7FFF_FFFF
256MB
External RAM
DDR41
S
7
0
27
0x8000_0000
0x8FFF_FFFF
256MB
External
device
DDR41
NS
8
0