Chrontel CH7515A Guide

AN-B021
Application Notes
206-1000-021 Rev 1.0 2020-07-15 1
Chrontel
PCB Layout and Design Guide for CH7515A
1.0 INTRODUCTION
Chrontel’s CH7515A is a low-cost, low-power semiconductor device that translates the eDP/DP signal to the LVDS
in form of RGB. This innovative eDP/DP receiver with integrated 4 channel LVDS transmitters is specially designed
to target the All-In-One and the notebook market segment.
This application note focuses only on the basic PCB layout and design guidelines for CH7515A Embedded Display
Port/ Display Port Receiver with LVDS Transmitter. Guidelines in component placement, power supply decoupling,
grounding, input /output signal interface are discussed in this document.
The discussion and figures that follow reflect and describe connections based on the 128-pin TQFP (14x14mm)
package of the CH7515A. Please refer to the CH7515A datasheet for the details of the pin assignments.
2.0 COMPONENT PLACEMENT AND DESIGN CONSIDERATIONS
Components associated with the CH7515A should be placed as close as possible to the respective pins. The following
discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the
placement and layout of components associated with these pins.
2.1 Power Supply Decoupling
The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power
supply pins as shown in Figure 1. These capacitors (C2, C3, C4, C5, C8, C9, C10, C11, C14, C15, C16, C17, C19)
should be connected as close as possible to their respective power and ground pins using short and wide traces to
minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the
decoupling capacitors to the CH7515A and CH716A ground pins, in addition to ground vias.
2.1.1 Ground Pins
The CH7515A should be connected to a common ground plane to provide a low impedance return path for the supply
currents. Whenever possible, each of the CH7515A ground pins should be connected to its respective decoupling
capacitor ground lead directly, and then connected to the ground plane through a ground via. Short and wide traces
should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins assignment.
2.1.2 Power Supply Pins
The power supplies include VDDPLL, DVDD, AVDD, AVCC, VDDRX, and VDDBG. Refer to Table 1 for the
Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.

CHRONTEL AN-B021
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Table 1: Power Supply Pins Assignment of the CH7515A (128TQFP)
Pin Assignment
# Of Pins
Type
Symbol
Description
3, 5, 112
3
Power
VDDPLL
PLL Power Supply (1.8V)
4, 111
2
Ground
GNDPLL
PLL Ground
8, 85
2
Power
DVDD
Digital Power Supply (1.8V)
9, 86
2
Ground
DGND
Digital Power Ground
21, 47, 74
3
Power
AVDD
LVDS Power Supply (3.3V)
22, 48, 73
3
Ground
AGND
LVDS Ground
101
1
Power
AVCC
Analog Power Supply (3.3V)
97
1
Ground
AVSS
Analog Ground
113, 119, 125
3
Power
VDDRX
DP Rx Power Supply (1.8V)
116, 122
2
Ground
GNDRX
DP Rx Ground
126
1
Power
VDDBG
Band-gap Power Supply (1.8V)
128
1
Ground
GNDBG
Band-gap Ground
RB
VCC18
VCC33 T1
Figure 1: Power Supply Decoupling and Distribution
Note:
1. Pease make sure the Voltage of AVCC and AVDD (VCC33) should be given earlier than the DVDD
and VDDPLL (VCC18).
2. The RB signal should be given to CH7515A after the powers are stable.
CH7515A
L1
47R 100MHz
1
2
C10
0.1uF
VDDRX
C11
0.1uF
C12
10uF
L2
47R 100MHz
1
2
L3
47R 100MHz
1
2
C16
0.1uF
C6
10uF
C18
10uF
VDDBG
C9
0.1uF
VCC3_3
C8
0.1uF
C7
10uF
C15
0.1uF
C13
10uF
AVCC
C17
0.1uF
TQFP
U1
CH7515A
AVCC
101
DVDD
8, 85
VDDRX
113, 119, 125
VDDBG
126
VDDPLL
3, 5, 112
DGND
9, 86
GNDRX
116, 122
GNDBG
128
GNDPLL
4, 111
AVSS
97
AVDD
21, 47, 74
AGND
22, 48, 73
C5
0.1uF
C3
0.1uF
C2
0.1uF
C1
10uF
VCC1_8
AVDD
C4
0.1uF
DVDD
VDDPLL
C14
0.1uF
L4
47R 100MHz
1
2
C19
0.1uF
VCC3_3
L5
47R 100MHz
1
2
L6
47R 100MHz
1
2
VCC1_8

CHRONTEL AN-B021
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3. T1 (the VCC18 rise slope time) should not be larger than 2ms
4. The exposed pad, which is the Thermal pad, must be linked to GND.
5. All the Ferrite Beads described in this document are recommended to have an impedance of less than
0.05 Ohm at DC; 23 Ohm at 25MHz & 47 Ohm at 100MHz. Please refer to Fair Rite part
#2743019447 for details or an equivalent part can be used for the diagram.
2.2 Internal Reference Pins
• RBIAS pin
This pin sets the Band-gap Bias Voltage. A 10 K-Ohm, 1% tolerance resistor should be connected between RBIAS
and GND as shown in Figure 2. A smaller resistance will create less Band-gap Bias voltage. This resistor should be
placed with short and wide traces as near as possible to CH7515A. For optimum performance, this signal should not
overlay the analog power or analog output signals.
Figure 2: RBIAS Pin Connection
2.3 General Control Pins
• RB
This pin is the chip reset pin for CH7515A. RB pin, which is internally pulled-up, places the device in the power on
reset condition when this pin is low. As shown in Figure 3, one 10Kohm resistor is necessary to be pulled high to
DVDD (1.8V). One 0.1uf capacitor is recommend to be pulled low to GND. After the powers are stable, please give
the chip the RB signal (low to high) As shown in Figure 1.
Option1: link RB signal to external GPIO_PCH signal (1.8V).
Option2: add the level shifter circuits to link RB signal to GPIO_PCH signal (3.3V).
• XI, XO
27MHz crystal (30ppm) can be connected to these pins of XI, XO as the CH7515A optional reference clock input.
In PCB design, 27MHz crystal must be placed as close as possible to the XI and XO pins, with traces connected from
point to point, overlaying the ground plane. Since the crystal generates timing reference for the CH7515A, it is very
important that noise should not couple into these input pins.
The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. As an example to show the
load capacitors, Figure 3 shows a reference design for crystal circuit design.
• REFCK
The REFCK is also the optional pin as reference input clock of the CH7515A. The choice is injecting clock 27MHz
(3.3V) at this pin as shown in Figure 3. For PCB design, the capacitor must be placed as close as possible to the
REFCK pin, with traces connected from point to point, overlaying the ground plane.
CH7515A
U1
RBIAS
127
R1
10k 1%
TQFP

CHRONTEL AN-B021
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Figure 3: General Control Pins
2.4 Serial Port Control Pins
• SPC0 and SPD0
SPD0 and SPC0 function as a serial interface where SPD0 is bi-directional data and SPC0 is an input only serial clock.
In the reference design, SPD0 and SPC0 pins are pulled up to VCC3_3 with 6.8kohm resistors. Through these two
pins, the internal register values of the chip can be read and can update the external Boot ROM. These pins should be
connecting to SPC1 and SPD1 with Jumpers as shown in Figure 4.
• SPC1 and SPD1
SPD1 and SPC1 function as a serial interface where SPD1 is bi-directional data and SPC1 is an input only serial clock.
In the reference design, SPD1 and SPC1 pins are pulled up to VCC3_3 with 6.8kohm resistors as shown in Figure 4.
SPD1 and SPC1 are used to interface with CH9904 (the serial BOOT ROM). From the BOOT ROM, the EDID and
Programmable Registers can be setting in BOOT ROM. When powering up, CH7515A will auto-load the values from
the BOOT ROM.
R1
10K
VCC18
C1
0.1uF
Q1
PMBS3904
1
2
3
R3
1k
R2
10K
VCC33
Q2
PMBS3904
1
2
3
RB_PCH
Note:
The resetb is 1.8V level. It need 10Kohm
resister to 1.8V and 0.1uf capacitor to
GND. So if the system reset signal is
3.3V,the level shift circuit is necessary.
REFCK
CH7515A
NOTE: CH7515/CH7516 supports three
kinds of clock input ways
Option1: use 27MHz crystal with 22pf
capacitors
Option 2: inject clock 14.318MHz(3.3V) in
REFCK pin(Pin 10)
Option 3: inject clock 27MHz (3.3V) in
REFCK pin(Pin 10)
U1
RB
1
XO
6
XI
7
REFCK
10
X1
644-1232-2-ND (27 MHz)
GND
4
P1
1
GND
2
P2
3
C3
18pF
1
2
C2
18pF
1
2

CHRONTEL AN-B021
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Figure 4: Serial Port Control
Note:
1. Pease make sure the Voltage (3.3V) should be given earlier than the DVDD and VDDPLL.
2. If the SPC0/SPD0 or AUX channel is used to update the CH9904, the precondition is that MCU firmware
must work well. We advise that the customers use IIC/SMBUS to update CH9904 by linking IIC/SMBUS to
SPC0 and SPD0
2.5 Display Port Signal Pins
• RXP/N0, RXP/N1, RXP/N2, RXP/N3
These pins accept four AC-coupled differential pair signals from the Display Port transmitter.
Since the digital serial data of the CH7515A may be toggled at speeds up to 2.7 GHz, it is strongly recommended that
the connection of these video signals between the graphics controller and the CH7515A should be kept as short as
possible and be isolated as much as possible from the analog outputs and analog circuitry. For optimum performance,
these signals should not overlay the analog power or analog output signals. It is recommended that 5 mils traces
should be used in routing these signals. There should be 7 mils spacing between each intra pair. The length for a pair
of intra differential signals should be matched within 5 mils. The length for inter pairs should be matched within
10mils. Bend, which is smaller than 45 degrees should be avoided. The AC coupling capacitors for the serial video
inputs must be placed close to the GMCH, as shown in Figure 5
.
Figure 5: CH7515A DispalyPort Main Link Lane Inputs
R3
6.8K
R5
6.8K
R4
6.8K
R8
10K
SPC1
R6
6.8K
1
2
U2
CH9904
GP1
1
GP2
2
GP3
3
GND
4
SPD
5
SPC
6
WE
7
VCC
8
VCC3_3
R7
6.8K
1
2
VCC3_3
VCC3_3
C1
0.1uF
1
2
SPC0
SPD0
R1
6.8K
1
2
R2
6.8K
1
2
VCC3_3
SPD1
JP1
HEADER 1x2
1
2
JP2
HEADER 1x2
1
2
SPC1
SPC0
SPD1
SPD0
U1
CH7515A
SPD1
104
SPC1
105
SPD0
106
SPC0
107
Boot Rom
U1
CH7515A
RXN3
124
RXN0
115
RXP0
114
RXP3
123
RXN2
121
RXP2
120
RXN1
118
RXP1
117
U2
GMCH
RXN3
RXN0
RXP0
RXP3
RXN2
RXP2
RXN1
RXP1
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
Soure

CHRONTEL AN-B021
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• AUXP and AUXN
These two pins are Display Port AUX channel control that accepts a half-duplex, bi-directional AC-coupled
differential signal.
They must have the AC-coupling capacitors, and 100nF capacitors are recommended in this document, as shown in
Figure 6.
• HPDET
This output pin indicates whether this device is active or not. It also generates interrupt pulse as defined by Display
Port standard. Output voltage is 3.3V. A resistor more than 100K-Ohm should be connected between this pin and
GND, as shown in Figure 6.
U1
CH 7515A and CH7516A
AUXN 95
HPDET 110
AUXP 96
U2
GMCH
AUXN
HPDET
AUXP
C1 0.1uF
C2 0.1uF
R1
100K R2
100K
Sink Source eDP
U9
CH 7515A and CH7516A
AUXN 95
HPDET 110
AUXP 96
C4 0.1uF
U11
GMCH
AUXN
HPDET
AUXP
R7
100K
C6 0.1uF
R8
100K
C3 0.1uF
Source DP
Sink
C5 0.1uF
R3
1M R5
100K
R4
1M R6
100K
+3.3V +3.3V
Figure 6: CH7515A AUX channel and HPDET
2.6 LVDS Signal Pins
• LVDS Outputs (LDxP and LDxN, LCxP and LCxN?)
The LVDS output signals are LDxP and LDxN. The LVDS is a differential interface with a nominal swing 200mV.
The following rules should be applied to the signals:
1. Keep traces as short as possible.
2. Make these traces have 100-ohm differential impedance.
3. Trace widths should be 5 mils.
4. Intra Pair spacing (spacing between the “+” and “-” pairs) should be 7mils.
5. Inter Pair spacing (spacing between one differential pair and another) should be a minimum of 20 mils exclude pin
pitch around.
6. Difference in trace lengths between “+” and “-” pairs should be within 5mils.
7. Difference in trace lengths among Inter pairs should be within 10mils.
8. “+” And “-” pairs should be routed in parallel.
2.7 Audio Output
•IIS
IIS audio output can be configured through programming CH7515A registers. (Refer to Figure 7)
• SPDIF
For SPDIF output, CH7515A support audio sample frequencies from 32Khz to 192kHz. (Refer to Figure 7)

CHRONTEL AN-B021
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Figure 7: CH7515A IIS or SPDIF Output Pins
2.8 Other function pins
• GPIO [0:3]
These pins are general-purpose input/output. GPIO [0] should be connecting to VDDEN pin with jumper as shown in
Figure 8.
• BLUP, BLDN
BLUP is the increase backlight brightness input pin.
BLDN is the decrease backlight brightness input pin.
Buttons can be placed at these pins to adjust the backlight brightness. Design is shown in Figure 8.
• PWRDN
CH7515A enter into or exits power down state when receiving active low pulse from this pin. The connection is
shown in Figure 8.
U1
CH7515A
SCLK
90
SDATA/SPDIF
88
WS
89
MCLK
87
SPDIF
J1
HEADER 3
1
2
3
I2S DAC
U1
CH7515A
BLUP
109
BLDN
108
PWRDN
91
GPIO[0]
11
VDDEN
98
R1
10K
+3.3V
SW1
BLUP
C1
0.1uF
R2
10K
R3
10K
SW2
BLDN
+3.3V
R4
10K
C2
0.1uF
R5
10K
SW3
PWRDN
+3.3V
R6
10K
C3
0.1uF
JP1
HEADER 1x2
1
2

CHRONTEL AN-B021
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Figure 8: BLDN, BLUP, PWRDN and GPIO [0] Connections
• PSEL [0:2]
These pins can be used as panel select signals. They can be pulled high or low forming into 8 different combinations.
Every combination can match with one panel type. The connection is shown Figure 9.
Figure 9: PSEL [0:2] connections
Method 1 (default)
PSEL [2:0] can be connected to high/low level by pull-up/pull-down resistors in CH7515A PCB board; CH7515A can
get correct LVDS Panel selection value upon power ON.
Method 2
PSEL [2:0] can be controlled by other chip’s GPIO pins in CH7515A application system.
If the chip controlling CH7515A PSEL [2:0] cannot set expected value before CH7515A finishes loading. Its
firmware (typically 150ms after CH7515A power ON), then the controlling chip must reset CH7515A to restart
CH7515A Loading BOOT ROM file. It is recommended to reset CH7515A by the controlling chip each time LVDS
Panel selection value is changed.
The following figure shows the typical cases to control CH7515A PSEL [2:0] by other chip.
Case1 is the right loading case. The PSEL pins can keep stable values in 150ms after the reset signal is given to
CH7515A RB pin
Case2 is the wrong loading case. The PSEL pins cannot keep stable values in 150ms after the reset signal is given to
CH7515A RB pin. So the RB signal must be given again. The RB pulse width is recommended be larger than 10ms.
R1
10k
+3.3V
R3
10k
R2
10k
R4
10k
R6
10k
R5
10k
U1
CH7515A
PSEL[2]
94
PSEL[1]
93
PSEL[0]
92
PSEL[2]
PSEL[0]
PSEL[1]

CHRONTEL AN-B021
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RB
Loading FirmwareIDLE Loading LVDS
Configurations
CH7515A I2C
Master Activity
Random Values Correct LVDS Panel Selection Value
IDLE
CH7515A
PSEL [2:0]
Case 1: CH7515A PSEL [2:0] settles before it starts loading LVDS configurations
RB
Loading Firmware
IDLE Loading LVDS
Configurations
CH7515A I2C
Master Activity
Random Values Correct LVDS Panel Selection Value
IDLE
CH7515A
PSEL [2:0]
Case 2: CH7515A PSEL [2:0] cannot settle before it starts loading LVDS configurations
Loading Firmware Loading LVDS
Configurations
Wrong LVDS
configurations! Correct LVDS configurations!
RB pulse generated by
Customers host chip
Figure 10: Typical cases to control CH7515A PSEL [2:0] by host chip
Note:
1. The PSEL pins must keep stable values in 150ms after the RB signal is given to CH7515A RB pin. Otherwise,
a reset signal must be given again.
2. All the case2 must be finished before VBIOS works. Otherwise, some BIOS pictures will be lost.
• PWM_OUT
The output Frequency from PWM_OUT can be up to 400 KHz. Its duty cycle rang is from 0% to 100%. Or this signal
can use PWM bypass mode way to output PWM signal. The voltage level is 3.3V. The detail information can be
reference to datasheet.
• PWM_IN
PWM_IN has two work modes: Bypass mode and Duty Cycle Multiplication with AUX CH mode.
In bypass mode, the input frequency to PWM_IN can be up to 1MHz.In Duty Cycle Multiplication with AUX CH
mode, the input frequency to PWM_IN can be up to 50 KHz. Despite in which mode, the voltage level is 3.3V.
Figure 11: PWM Control connections
• Reserved
Reserved pin (pin 2) should be left open in the application.
2.9 Important Design Considerations
U1
CH7515A
PWM_IN
103
PWM_OUT
102
PWM_IN
PWM_OUT

CHRONTEL AN-B021
10 206-1000-021 Rev 1.0 2020-07-15
(Panel power, backlight power, pull-up voltage)
• LVDS Power
Close attention must be paid to the power supplied to the LVDS backlight and the LVDS panel. Power requirements
may differ from panel to panel. Please check the panels’ power and backlight voltage specifications. BLL_EN,
BLR_EN and VDDEN of the CH7515A can be used as control signal to turn on the power to the LVDS backlight and
the LVDS logic circuitry.
2.10 Thermal Exposed Pad Package
The CH7515A are available in 128-pin TQFP package with thermal exposed pad package. The advantage of the
thermal exposed pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently.
When properly implemented, the exposed pad package provides a means of reducing the thermal resistance of the
CH7515A.
Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat
dissipation, the exposed pad of the package should be soldered to the PCB as shown in Figure 12.
Die
Exposed Pad
Solder
PCB
Pin
Figure 12: Cross-section ofexposed pad package

CHRONTEL AN-B021
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11
3.0 REFERENCE DESIGN EXAMPLE
The following schematics are to be used as a CH7515A PCB design example only. It is not a complete design. Those
who are seriously doing an application design with the CH7515A and would like to have a complete reference design
schematic, which should contact Applications within Chrontel, Inc.
3.1 Schematics of Reference Design Example

CHRONTEL AN-B021
12 206-1000-021 Rev 1.0 2020-07-15
Figure 13:CH7515A Reference schematic
Spdif_out
HPDET
GPIO[0]
SPD0
GPIO[1]
GPIO[0]
SPD0
HPDET
GPIO[3]
GPIO[2]
GPIO[1]
GPIO[3]
GPIO[2]
SPC0
SPC0
NOTE:
1. The dotted line parts are option funtion circuits.
2. The voltage circuit can only support CH7515/CH7516 chip to work.If supporting
the panel voltage, please add the other circuit.
3. Whether to use PWM_IN(3.3V), PWM_OUT(3.3V)
is determined by customers.Which is used for Panel luminance adjustment.
4. DP and LVDS diffential pairs should be as short as possible. Please see
appliciton note for detial layout guide
PSEL[0]
PSEL[1]
PSEL[2]
R5
6.8k
R6
6.8k
+3.3V
R4
1.8k
+3.3V
SPC1
R1
6.8k
SPD1
Boot Room
R3
6.8k
+3.3V
R2
6.8k
NOTE: PSEL[2:0]
are for
selecting panel
VCC18
R20
10k
R21
10k
R22
10k
+3.3V
DP3P
DP1N
DP1P
DP0N
DP2N
DP2
DP3N
DP0P
GND
DP0N
DP0P
GND
DP2N
DP2P
C3
0.1uF
C5
0.1uF
C1
0.1uF
C2
0.1uF
GND
DP3N
DP3P
GPIO[2]
GPIO[3]
AUXP
AUXN
GND
VCC18
GND
GND
VCC18
GND
U2
DP_sink
ML_Lane3n
1
GND
2
ML_Lane3p
3
ML_Lane2n
4
GND
5
ML_Lane2p
6
ML_Lane1n
7
GND
8
ML_Lane1p
9
ML_Lane0n
10
GND
11
ML_Lane0p
12
GND
13
GND
14
AUX_CHp
15
GND
16
AUX_CHn
17
HPDET
18
RTN_DPPWR
19
DPPWR
20
GND
22
GND
23
GND
24
GND
25
DP0P_MLDP0P_ML
DPPWR
GND
GND
DP0N_MLDP0N_ML
GND
GND
HPDETHPDET
R12
10K(1%)
1
2
+3.3V
R8
10K
R7
49.9
C4
0.1uF
C7
0.1uF
C6
0.1uF
DP1N
DP1P
C8
0.1uF
DP Interface
R23
10k
R24
10k
R25
10k
Backlight_L
Backlight_R
VCC18
VCC18
GND
+12V
+3.3V
Y1
27MHz
C31
22pF
C33
22pF
Q4
MMBT3904
1
2
3
U5
AMP4953
S1
1
G1
2
S2
3
G2
4
D2
5
D2
6
D1
7
D1
8
R27
50k
BLR_EN
R29
10k
Q3
H2N7002
1
3
2
VCC33
C24
0.1uF
R26
470
+3.3V
L1
Bead
C9
0.1uF
+3.3V
+12V
JP1
HEADER 3
1
2
3
C11
10uF
U1
IRU1206-18
Vout
3
Gnd
2
Vin
1
pin
4
+1.8V
VCC_PanelDriver
Q7
MMBT3904
1
2
3
C12
0.1uF
R32
50k
L2
Bead
C10
10uF
U6
AMP4953
S1
1
G1
2
S2
3
G2
4
D2
5
D2
6
D1
7
D1
8
VCC18
GND
VCC18
VDDEN
R37
10k
C22
0.1uF
C17
0.1uF
Q6
H2N7002
1
3
2
C23
0.1uF
C14
0.1uF
R31
470
C13
0.1uF
VCC33
VCC18
C16
0.1uF
+5V
Panel Voltage and backlight control circuit
REFCK
C15
0.1uF
C19
0.1uF
C18
0.1uF
C20
0.1uF
Power
Supply
TXE3P
GND
C25
0.1uF
TXC3P
TXC3N
VCC33
TXE3N
TXD3P
TXD3N
TXCK3P
TXCK3N
C21
0.1uF
VCC33
GND
TXA0N
TXB3N
TXB3P
TXB0P
TXCK0P
TXCK0N
TXC0P
TXA0P
TXB0N
TXC0N
VCC18
TXCK2
TXA3N
TXE2P
TXE2N
TXA3P
TXB2P
TXB2N
TXD2P
TXD2N
TXCK2P
TXA2N
VCC33
GND
TXC2P
TXC2N
TXD1N
TXCK1P
TXCK1N
TXC1P
TXC1N
TXA2P
TXA1P
TXA1N
TXE1P
TXE1N
TXD1P
TXE0N
TXD0P
TXD0N
TXB1P
TXB1N
PWM_OUT
VCC18
VCC18
GND
HPDET
TXE0P
SPD0
SPC1
SPD1
PWM_IN
BLR_EN
VDDEN
GND
BLUP
BLDN
SPC0
VCC33
BLL_EN
R30
10k
Q5
MMBT3904
1
2
3
R28
50k
BLL_EN
R13
100K
1
2
AUXP
AUXN
C30
0.1uF
C32
0.1uF
MCLK
SDATA
SPDIF
GND
PSEL[2]
WS
PSEL[1]
PSEL[0]
SCLK
PWRDN
+3.3V
J1
2
4
6
1
3
5
R33
10K
R34
10K
R35
10K
C29
0.1uF
R19
1k
R15
10K
VCC33
RESETB_PCH
R11
10K
Q2
PMBS3904
1
2
3
Q1
PMBS3904
1
2
3
VCC18
U4
CH7515A
RB
1
Reserved
2
VDDPLL
3
GNDPLL
4
VDDPLL
5
XO
6
XI
7
DVDD
8
DGND
9
REFCK
10
GPIO[0]
11
GPIO[1]
12
NC
13
NC
14
15
NC
NC
16
LD16N
32
NC
17
NC
18
NC
19
NC
20
AVDD
21
AGND
22
LC3P
23
LC3N
24
LD19P
25
LD19N
26
LD18P
27
LD18N
28
LD17P
29
LD17N
30
LD16P
31
PSEL[2]
94
PSEL[1]
93
PSEL[0]
92
PWRDN
91
SCLK
90
WS
89
SDATA/SPDIF
88
MCLK
87
DGND
86
AUXP
96
AUXN
95
DVDD
85
GPIO[3]
84
GPIO[2]
83
NC
82
NC
81
NC
80
NC
79
NC
78
NC
77
NC
76
NC
75
AVDD
74
AGND
73
LD0N
72
LD0P
71
LD1N
70
LD1P
69
LD2N
68
LD2P
67
LD3N
66
LD3P
65
RXN
121
RXP2
120
VDDRX
119
RXN1
118
RXP1
117
GNDRX
116
RXN0
115
RXP0
114
VDDRX
113
VDDPLL
112
GND_PLL
111
HPDET
110
BLUP
109
BLDN
108
SPC0
107
SPD0
106
SPC1
105
SPD1
104
PWM_IN
103
PWM_OUT
102
AVCC
101
BLL_EN
100
VDDEN
98
AVSS
97
BLR_EN
99
GNDRX
122
RXP3
123
RXN3
124
VDDRX
125
VDDBG
126
RBIAS
127
GNDBG
128
LC1P
49
AVDD
47
LC1N
50
LD14P
37
LC0N
62
LD9P
51
LD15N
34
LD7N
56
LD15P
33
AGND
48
LD8N
54
LC2N
36
LD7P
55
LC0P
61
LD9N
52
LD6P
57
LD10P
45
LD10N
46
LD13
40
LD4P
63
LD12N
42
LD5N
60
LD13P
39
LD12P
41
LD14N
38
LD11P
43
LD11N
44
LD6N
58
LD4N
64
LD5P
59
LD8P
53
LC2P
35
Note:
The resetb is 1.8V level. It need 10Kohm
resister to 1.8V and 0.1uf capacitor to GND.
So if the system reset signal is 3.3V,the level shift
circuit is necessary.
NOTE: CH7515/CH7516 supports three kinds of clock input ways
Option1: use 27MHz crystal with 22pf capacitors
Option 2: inject clock 14.318MHz(3.3V) in REFCK pin(Pin 10)
Option 3: inject clock 27MHz (3.3V) in REFCK pin(Pin 10)
Customer must choose one option for CH7515/CH7516 clock. We
suggest that the customers use crystal or 27Mhz clock ways
R38
10K
R39
10K
R40
10K
GPIO[2]
GPIO[3]
GPIO[1]
U3
CH9904(SOIC-8 package)
GP2
2
GP3
3
GND
4
SPD
5
SPC
6
WE
7
VCC
8
GP1
1
Note: GPIO[1]~GPIO[3] must be pull low
or high as input IO
GPIO[0]
GPIO[1]
Spdif_out
C35
1uF
SDATA
WS
SPDIF
audio(IIS)
WS
SCLK
MCLK
MCLK
audio(Spdif)
SDATA
SCLK
SPC0
SPC1
SPD0
JP10
HEADER 1x2
1
2
JP11
HEADER 1x2
1
2
SPD1
JP12
HEADER 1x2
1
2
VDDEN
GPIO[0]
Must be reserved, Jumper canbe
replace with 0 ohm resisitor
Note:It is a option that Each 100ohm resistor
should be linked in each LVDS N/P differential signals
R9
10K
SW1
R10
10K
+3.3V
BLDN
SW2
+3.3V
PWRDN
C26
0.1uF
BLUP
R17
10K
R14
10K
SW3
BLUPBLUPBLUP
C28
0.1uF
C27
0.1uF
+3.3V
R16
10K
R18
10K

CHRONTEL AN-B021
206-1000-021 Rev 1.0 2020-07-15
13
3.2 Reference Board Preliminary BOM
Table 2: CH7515A Reference Design BOM List
Item
Quantity
Reference
Part
1
29
C1, C2, C3, C4, C5, C6, C7, C8, C9, C12, C13, C14, C15, C16,
C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28,
C29, C30, C32
0.1uF
2
2
C10, C11
10uF
3
2
C31, C33
22pF
4
1
C35
1uF
5
1
JP1
Header 3
3
JP10, JP11, JP12
Header 2
6
1
J1
Header 3x2
7
2
L1, L2
Bead
8
2
Q1, Q2
PMBS3904
9
2
Q3, Q6
2N7002
10
3
Q4, Q5, Q7
MMBT3904
11
5
R1, R2, R3, R5, R6
6.8K
12
1
R4
1.8K
13
1
R7
49.9
14
24
R8, R9, R10, R11, R14, R15, R16, R17, R18, R20, R21, R22,
R23, R24, R25, R29, R30, R33, R34, R35, R37, R38, R39, R40
10K
15
1
R12
10K 1%
16
1
R13
100K
17
1
R19
1K
18
2
R26, R31
470
19
3
R27, R28, R32
49.9K
20
3
SW1, SW2, SW3
P8058ss-ND
21
1
U1
IRU1206-18
22
1
U2
DP_Sink
23
1
U3
CH9904
24
1
U4
CH7515A
25
2
U5, U6
AMP4953
26
1
Y1
27M

CHRONTEL AN-B021
14 206-1000-021 Rev 1.0 2020-07-15
4.0 REVISION HISTORY
Table 3: Revisions
Rev. #
Date
Section
Description
0.1
02/01/2013
All
Initial release
0.2
05/16/2013
2.4
Modify Boot Rom to CH9904
0.3
10/17/2014
2.3
2.4
2.5
2.6
2.8
3.1
Modify crystal name
Modify SPC0 and SPD0 schematic
Modify Aux schematic
Modify LVDS rules
Modify GPIO [0] schematic
Modify reference schematic
0.4
12/19/2017
2.1
Modify the GND pin
1.0
07/15/2020
All
Remove CH7216A

CHRONTEL AN-B021
206-1000-021 Rev 1.0 2020-07-15
15
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. CHRONTEL warrants each part to be
free from defects in material and workmanship for a period of one (1) year from date of shipment. Chrontel assumes
no liability for errors contained within this document. The customer should make sure that they have the most recent
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to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
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