Segger J-link User manual

A product of SEGGER Microcontroller GmbH & Co. KG

www.segger.com

J-Link / J-Trace

ARM

Manual Rev. 73

Document: UM08001

Date: July 3, 2009

User guide of the JTAG emulators

for ARM Cores

Disclaimer

Specifications written in this document are believed to be accurate, but are not guar-

anteed to be entirely free of error. The information in this manual is subject to

change for functional or performance improvements without notice. Please make sure

your manual is the latest edition. While the information herein is assumed to be

accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no

responsibility for any errors or omissions. The manufacturer makes and you receive

no warranties or conditions, express, implied, statutory or in any communication with

you. The manufacturer specifically disclaims any implied warranty of merchantability

or fitness for a particular purpose.

You may not extract portions of this manual or modify the PDF file in any way without

the prior written permission of the manufacturer. The software described in this doc-

ument is furnished under a license and may only be used or copied in accordance

with the terms of such a license.

Trademarks

Names mentioned in this manual may be trademarks of their respective companies.

Brand and product names are trademarks or registered trademarks of their respec-

tive holders.

Contact address

SEGGER Microcontroller GmbH & Co. KG

In den Weiden 11

D-40721 Hilden

Germany

Tel.+49 2103-2878-0

Fax.+49 2103-2878-28

Email: support@segger.com

Internet: http://www.segger.com

Revisions

This manual describes the J-Link and J-Trace device.

For further information on topics or routines not yet specified, please contact us.

Revision Date By Explanation

73 090701 KN

Chapter "Introduction"

* Section "J-Link and J-Trace models" added

* Sections "Model comparison chart" &

"J-Link bundle comparison chart"added

Chapter "J-Link and J-Trace models" removed

Chapter "Hardware" renamed to

"Target interfaces & adapters"

* Section "JTAG Isolator" added

Chapter "Target interfaces and adapters"

* Section "Target board design" updated

Several corrections

72 090618 AG

Chapter "Working with J-Link"

* Section "J-Link control panel" updated.

Chapter "Flash download and flash breakpoints"

* Section "Supported devices" updated.

Chapter "Device specifics"

* Section "NXP" updated.

71 090616 AG Chapter "Device specifics"

* Section "NXP" updated.

70 090605 AG

Chapter "Introduction"

* Section "Common features of the J-Link

product family" updated.

69 090515 AG

Chapter "Working with J-Link"

* Section "Reset strategies" updated.

* Section "Indicators" updated.

Chapter "Flash download and flash breakpoints"

* Section "Supported devices" updated.

68 090428 AG

Chapter "J-Link and J-Trace related software"

* Section "J-Link STM32 Commander" added.

Chapter "Working with J-Link"

* Section "Reset strategies" updated.

67 090402 AG Chapter "Working with J-Link"

* Section "Reset strategies" updated.

66 090327 AG

Chapter "Background information"

* Section "Embedded Trace Macrocell (ETM)"

updated.

Chapter "J-Link and J-Trace related software"

* Section "Dedicated flash programming

utilities for J-Link" updated.

65 090320 AG Several changes in the manual structure.

64 090313 AG Chapter "Working with J-Link"

* Section "Indicators" added.

63 090212 AG

Chapter "Hardware"

* Several corrections.

* Section "Hardware Versions" Version 8.0 added.

62 090211 AG

Chapter "Working with J-Link and J-Trace"

* Section "Reset strategies" updated.

Chapter J-Link and J-Trace related software

* Section "J-Link STR91x Commander

(Command line tool)" updated.

Chapter "Device specifics"

* Section "ST Microelectronics" updated.

Chapter "Hardware" updated.

61 090120 TQ Chapter "Working with J-Link"

* Section "Cortex-M3 specific reset strategies"

60 090114 AG Chapter "Working with J-Link"

* Section "Cortex-M3 specific reset strategies"

59 090108 KN

Chapter Hardware

* Section "Target board design for JTAG"

updated.

* Section "Target board design for SWD" added.

58 090105 AG

Chapter "Working with J-Link Pro"

* Section "Connecting J-Link Pro the first time"

updated.

57 081222 AG

Chapter "Working with J-Link Pro"

* Section "Introduction" updated.

* Section "Configuring J-Link Pro

via web interface" updated.

Chapter "Introduction"

* Section "J-Link Pro overview" updated.

56 081219 AG

Chapter "Working with J-Link Pro"

* Section "FAQs" added.

Chapter "Support and FAQs"

* Section "Frequently Asked Questions" updated.

55 081218 AG Chapter "Hardware" updated.

54 081217 AG Chapter "Working with J-Link and J-Trace"

* Section "Command strings" updated.

53 081216 AG Chapter "Working with J-Link Pro" updated.

52 081212 AG

Chapter "Working with J-Link Pro" added.

Chapter "Licensing"

* Section "Original SEGGER products" updated.

51 081202 KN Several corrections.

50 081030 AG Chapter "Flash download and flash breakpoints"

* Section "Supported devices" corrected.

49 081029 AG Several corrections.

48 080916 AG

Chapter "Working with J-Link and J-Trace"

* Section "Connecting multiple J-Links /

J-Traces to your PC" updated.

47 080910 AG Chapter "Licensing" updated.

46 080904 AG

Chapter "Licensing" added.

Chapter "Hardware"

Section "J-Link OEM versions" moved to chapter

"Licensing"

45 080902 AG

Chapter "Hardware"

Section "JTAG+Trace connector" JTAG+Trace

connector pinout corrected.

Section "J-Link OEM versions" updated.

44 080827 AG

Chapter "J-Link control panel" moved to chapter

"Working with J-Link".

Several corrections.

43 080826 AG Chapter "Flash download and flash breakpoints"

Section "Supported devices" updated.

42 080820 AG Chapter "Flash download and flash breakpoints"

Section "Supported devices" updated.

41 080811 AG

Chapter "Flash download and flash breakpoints"

updated.

Chapter "Flash download and flash breakpoints",

section "Supported devices" updated.

Revision Date By Explanation

40 080630 AG

Chapter "Flash download and flash breakpoints"

updated.

Chapter "J-Link status window" renamed to "J-Link

control panel"

Various corrections.

39 080627 AG

Chapter "Flash download and flash breakpoints"

Section "Licensing" updated.

Section "Using flash download and flash

breakpoints with different debuggers" updated.

Chapter "J-Link status window" added.

38 080618 AG

Chapter "Support and FAQs"

Section "Frequently Asked Questions" updated

Chapter "Reset strategies"

Section "Cortex-M3 specific reset strategies"

updated.

37 080617 AG

Chapter "Reset strategies"

Section "Cortex-M3 specific reset strategies"

updated.

36 080530 AG

Chapter "Hardware"

Section "Differences between different versions"

updated.

Chapter "Working with J-Link and J-Trace"

Section "Cortex-M3 specific reset strategies"

added.

35 080215 AG

Chapter "J-Link and J-Trace related software"

Section "J-Link software and documentation

package in detail" updated.

34 080212 AG

Chapter "J-Link and J-Trace related software"

Section "J-Link TCP/IP Server (Remote J-Link /

J-Trace use)" updated.

Chapter "Working with J-Link and J-Trace"

Section "Command strings" updated.

Chapter "Flash download and flash breakpoints"

Section "Introduction" updated.

Section "Licensing" updated.

Section "Using flash download and flash

breakpoints with different debuggers" updated.

33 080207 AG

Chapter "Flash download and flash breakpoints"

added

Chapter "Device specifics:"

Section "ATMEL - AT91SAM7 - Recommended init

sequence" added.

32 0080129 SK

Chapter "Device specifics":

Section "NXP - LPC - Fast GPIO bug" list of

device enhanced.

31 0080103 SK Chapter "Device specifics":

Section "NXP - LPC - Fast GPIO bug" updated.

30 071211 AG

Chapter "Device specifics":

Section "Analog Devices" updated.

Section "ATMEL" updated.

Section "Freescale" added.

Section "Luminary Micro" added.

Section "NXP" updated.

Section "OKI" added.

Section "ST Microelectronics" updated.

Section "Texas Instruments" updated.

Chapter "Related software":

Section "J-Link STR91x Commander" updated

Revision Date By Explanation

29 070912 SK Chapter "Hardware", section "Target board design"

updated.

28 070912 SK

Chapter "Related software":

Section "J-LinkSTR91x Commander" added.

Chapter "Device specifics":

Section "ST Microelectronics" added.

Section "Texas Instruments" added.

Subsection "AT91SAM9" added.

28 070912 AG Chapter "Working with J-Link/J-Trace":

Section "Command strings" updated.

27 070827 TQ Chapter "Working with J-Link/J-Trace":

Section "Command strings" updated.

26 070710 SK

Chapter "Introduction":

Section "Features of J-Link" updated.

Chapter "Background Information":

Section "Embedded Trace Macrocell" added.

Section "Embedded Trace Buffer" added.

25 070516 SK

Chapter "Working with J-Link/J-Trace":

Section "Reset strategies in detail"

- "Software, for Analog Devices ADuC7xxx

MCUs" updated

- "Software, for ATMEL AT91SAM7 MCUs"

added.

Chapter "Device specifics"

Section "Analog Devices" added.

Section "ATMEL" added.

24 070323 SK

Chapter "Setup":

"Uninstalling the J-Link driver" updated.

"Supported ARM cores" updated.

23 070320 SK Chapter "Hardware":

"Using the JTAG connector with SWD" updated.

22 070316 SK Chapter "Hardware":

"Using the JTAG connector with SWD" added.

21 070312 SK

Chapter "Hardware":

"Differences between different versions"

supplemented.

20 070307 SK Chapter "J-Link / J-Trace related software":

"J-Link GDB Server" licensing updated.

19 070226 SK

Chapter "J-Link / J-Trace related software" updated

and reorganized.

Chapter "Hardware"

"List of OEM products" updated

18 070221 SK Chapter "Device specifics" added

Subchapter "Command strings" added

17 070131 SK

Chapter "Hardware":

"Version 5.3": Current limits added

"Version 5.4" added

Chapter "Setup":

"Installating the J-Link USB driver" removed.

"Installing the J-Link software and documentation

pack" added.

Subchapter "List of OEM products" updated.

"OS support" updated

16 061222 SK Chapter "Preface": "Company description" added.

J-Link picture changed.

Revision Date By Explanation

15 060914 OO

Subchapter 1.5.1: Added target supply voltage and

target supply current to specifications.

Subchapter 5.2.1: Pictures of ways to connect J-

Trace.

14 060818 TQ Subchapter 4.7 "Using DCC for memory reads"

added.

13 060711 OO Subchapter 5.2.2: Corrected JTAG+Trace connec-

tor pinout table.

12 060628 OO Subchapter 4.1: Added ARM966E-S to List of sup-

ported ARM cores.

11 060607 SK Subchapter 5.5.2.2 changed.

Subchapter 5.5.2.3 added.

10 060526 SK

ARM9 download speed updated.

Subchapter 8.2.1: Screenshot "Start sequence"

updated.

Subchapter 8.2.2 "ID sequence" removed.

Chapter "Support" and "FAQ" merged.

Various improvements

9 060324 OO

Chapter "Literature and references" added.

Chapter "Hardware":

Added common information trace signals.

Added timing diagram for trace.

Chapter "Designing the target board for trace"

added.

8 060117 OO Chapter "Related Software": Added JLinkARM.dll.

Screenshots updated.

7 051208 OO Chapter Working with J-Link: Sketch added.

6 051118 OO

Chapter Working with J-Link: "Connecting multiple

J-Links to your PC" added.

Chapter Working with J-Link: "Multi core debug-

ging" added.

Chapter Background information: "J-Link firm-

ware" added.

5 051103 TQ Chapter Setup: "JTAG Speed" added.

4 051025 OO

Chapter Background information: "Flash program-

ming" added.

Chapter Setup: "Scan chain configuration" added.

Some smaller changes.

3 051021 TQ Performance values updated.

2 051011 TQ Chapter "Working with J-Link" added.

1 050818 TW Initial version.

Revision Date By Explanation

About this document

This document describes J-Link and J-Trace. It provides an overview over the major

features of J-Link and J-Trace, gives you some background information about JTAG,

ARM and Tracing in general and describes J-Link and J-Trace related software pack-

ages available from Segger. Finally, the chapter Support and FAQs on page 187 helps

to troubleshoot common problems.

For simplicity, we will refer to J-Link ARM as J-Link in this manual.

For simplicity, we will refer to J-Link ARM Pro as J-Link Pro in this manual.

Typographic conventions

This manual uses the following typographic conventions:

Style Used for

Body Body text.

Keyword Text that you enter at the command-prompt or that appears on the

display (that is system functions, file- or pathnames).

Reference Reference to chapters, tables and figures or other documents.

GUIElement Buttons, dialog boxes, menu names, menu commands.

Table 1.1: Typographic conventions

EMBEDDED SOFTWARE

(Middleware)

emWin

Graphics software and GUI

emWin is designed to provide an effi-

cient, processor- and display control-

ler-independent graphical user

interface (GUI) for any application that

operates with a graphical display.

Starterkits, eval- and trial-versions are

available.

embOS

Real Time Operating System

embOS is an RTOS designed to offer

the benefits of a complete multitasking

system for hard real time applications

with minimal resources. The profiling

PC tool embOSView is included.

emFile

File system

emFile is an embedded file system with

FAT12, FAT16 and FAT32 support.

emFile has been optimized for mini-

mum memory consumption in RAM and

ROM while maintaining high speed.

Various Device drivers, e.g. for NAND

and NOR flashes, SD/MMC and Com-

pactFlash cards, are available.

emUSB

USB device stack

A USB stack designed to work on any

embedded system with a USB client

controller. Bulk communication and

most standard device classes are sup-

ported.

SEGGER TOOLS

Flasher

Flash programmer

Flash Programming tool primarily for microcon-

trollers.

J-Link

JTAG emulator for ARM cores

USB driven JTAG interface for ARM cores.

J-Trace

JTAG emulator with trace

USB driven JTAG interface for ARM cores with

Trace memory. supporting the ARM ETM (Embed-

ded Trace Macrocell).

J-Link / J-Trace Related Software

Add-on software to be used with SEGGER’s indus-

try standard JTAG emulator, this includes flash

programming software and flash breakpoints.

SEGGER Microcontroller GmbH & Co. KG develops

and distributes software development tools and ANSI

C software components (middleware) for embedded

systems in several industries such as telecom, medi-

cal technology, consumer electronics, automotive

industry and industrial automation.

SEGGER’s intention is to cut software development-

time for embedded applications by offering compact flexible and easy to use middleware,

allowing developers to concentrate on their application.

Our most popular products are emWin, a universal graphic software package for embed-

ded applications, and embOS, a small yet efficient real-time kernel. emWin, written

entirely in ANSI C, can easily be used on any CPU and most any display. It is comple-

mented by the available PC tools: Bitmap Converter, Font Converter, Simulator and

Viewer. embOS supports most 8/16/32-bit CPUs. Its small memory footprint makes it

suitable for single-chip applications.

Apart from its main focus on software tools, SEGGER develops and produces programming

tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in develop-

ment, debugging and production, which has rapidly become the industry standard for

debug access to ARM cores.

Corporate Office:

http://www.segger.com

United States Office:

http://www.segger-us.com

1 Introduction....................................................................................................................17

1.1 J-Link / J-Trace models ............................................................................18

1.1.1 Comparison chart .................................................................................... 18

1.1.2 J-Link ARM .............................................................................................19

1.1.3 J-Link ARM Pro ........................................................................................22

1.1.4 J-Trace ARM ........................................................................................... 23

1.1.5 Flasher ARM............................................................................................24

1.1.6 J-Link ColdFire ........................................................................................24

1.1.7 J-Trace for Cortex-M3 ..............................................................................25

1.2 Common features of the J-Link product family .............................................26

1.3 Supported ARM cores ............................................................................... 27

1.3.1 Upcoming supported cores........................................................................27

1.4 Requirements..........................................................................................28

2 Licensing........................................................................................................................29

2.1 Introduction............................................................................................30

2.2 Software components requiring a license ....................................................31

2.3 License types ..........................................................................................32

2.3.1 Built-in license ........................................................................................32

2.3.2 Key-based license.................................................................................... 32

2.3.3 Device-based license................................................................................ 33

2.4 Legal use of SEGGER J-Link software.......................................................... 35

2.4.1 Use of the software with 3rd party tools......................................................35

2.5 Original SEGGER products......................................................................... 36

2.5.1 J-Link ....................................................................................................36

2.5.2 J-Link Pro ...............................................................................................36

2.5.3 J-Trace................................................................................................... 37

2.5.4 Flasher ARM............................................................................................37

2.6 J-Link OEM versions ................................................................................. 38

2.6.1 mIDASLink (Analog Devices)..................................................................... 38

2.6.2 SAM-ICE (Atmel) .....................................................................................38

2.6.3 Digi JTAG Link (Digi International) .............................................................39

2.6.4 IAR J-Link / IAR J-Link KS (IAR) ................................................................ 39

2.6.5 IAR J-Trace.............................................................................................40

2.7 J-Link OBs ..............................................................................................41

2.8 Illegal Clones ..........................................................................................42

3 Setup..............................................................................................................................43

3.1 Installing the J-Link ARM software and documentation pack .......................... 44

3.1.1 Setup procedure......................................................................................44

3.2 Setting up the USB interface .....................................................................47

3.2.1 Verifying correct driver installation.............................................................47

3.3 Uninstalling the J-Link USB driver ..............................................................49

3.4 Setting up the IP interface ........................................................................50

3.4.1 Connecting the first time ..........................................................................50

3.4.2 Configuring the J-Link ..............................................................................51

3.4.3 FAQs......................................................................................................53

4 J-Link and J-Trace related software...............................................................................55

4.1 J-Link related software .............................................................................56

Table of Contents

4.1.1 J-Link software and documentation package ............................................... 56

4.1.2 List of additional software packages........................................................... 57

4.2 J-Link software and documentation package in

detail..................................................................................................... 58

4.2.1 J-Link Commander (Command line tool)..................................................... 58

4.2.2 J-Link STR91x Commander (Command line tool) ......................................... 59

4.2.3 J-Link STM32 Commander (Command line tool) .......................................... 60

4.2.4 J-Link TCP/IP Server (Remote J-Link / J-Trace use) ..................................... 61

4.2.5 J-Mem Memory Viewer............................................................................. 62

4.2.6 J-Flash ARM (Program flash memory via JTAG) ........................................... 63

4.2.7 J-Link RDI (Remote Debug Interface)......................................................... 64

4.2.8 J-Link GDB Server ................................................................................... 65

4.3 Dedicated flash programming utilities for J-Link........................................... 66

4.3.1 Introduction ........................................................................................... 66

4.3.2 Supported Eval boards ............................................................................. 66

4.3.3 Supported flash memories........................................................................ 67

4.3.4 How to use the dedicated flash programming utilities ................................... 67

4.3.5 Using the dedicated flash programming utilities for production and commercial

purposes 67

4.3.6 F.A.Q..................................................................................................... 68

4.4 Additional software packages in detail ........................................................ 69

4.4.1 JTAGLoad (Command line tool) ................................................................. 69

4.4.2 J-Link Software Developer Kit (SDK).......................................................... 69

4.4.3 J-Link Flash Software Developer Kit (SDK).................................................. 69

4.5 Using the J-LinkARM.dll............................................................................ 70

4.5.1 What is the JLinkARM.dll?......................................................................... 70

4.5.2 Updating the DLL in third-party programs................................................... 70

4.5.3 Determining the version of JLinkARM.dll ..................................................... 71

4.5.4 Determining which DLL is used by a program.............................................. 71

5 Working with J-Link and J-Trace....................................................................................73

5.1 Connecting the target system ................................................................... 74

5.1.1 Power-on sequence ................................................................................. 74

5.1.2 Verifying target device connection ............................................................. 74

5.1.3 Problems................................................................................................ 74

5.2 Indicators .............................................................................................. 75

5.2.1 Main indicator......................................................................................... 75

5.2.2 Input indicator ........................................................................................ 77

5.2.3 Output indicator...................................................................................... 77

5.3 JTAG interface ........................................................................................ 78

5.3.1 Multiple devices in the scan chain.............................................................. 78

5.3.2 Sample configuration dialog boxes............................................................. 78

5.3.3 Determining values for scan chain configuration .......................................... 81

5.3.4 JTAG Speed............................................................................................ 82

5.4 SWD interface ........................................................................................ 83

5.4.1 SWO ..................................................................................................... 83

5.5 Multi-core debugging ............................................................................... 85

5.5.1 How multi-core debugging works............................................................... 85

5.5.2 Using multi-core debugging in detail .......................................................... 86

5.5.3 Things you should be aware of .................................................................. 87

5.6 Connecting multiple J-Links / J-Traces to your PC ........................................ 89

5.6.1 How does it work? ................................................................................... 89

5.6.2 Configuring multiple J-Links / J-Traces ....................................................... 90

5.6.3 Connecting to a J-Link / J-Trace with non default USB-Address...................... 91

5.7 J-Link control panel ................................................................................. 92

5.7.1 Tabs...................................................................................................... 92

5.8 Reset strategies ...................................................................................... 98

5.8.1 Strategies for ARM 7/9 devices ................................................................. 98

5.8.2 Strategies for Cortex-M3 devices..............................................................100

5.9 Using DCC for memory access .................................................................101

5.9.1 What is required? ...................................................................................101

5.9.2 Target DCC handler ............................................................................... 101

5.9.3 Target DCC abort handler ....................................................................... 101

5.10 Command strings .................................................................................. 102

5.10.1 List of available commands ..................................................................... 102

5.10.2 Using command strings .......................................................................... 108

5.11 Switching off CPU clock during debug ....................................................... 110

5.12 Cache handling...................................................................................... 111

5.12.1 Cache coherency ................................................................................... 111

5.12.2 Cache clean area ................................................................................... 111

5.12.3 Cache handling of ARM7 cores................................................................. 111

5.12.4 Cache handling of ARM9 cores................................................................. 111

6 Flash download and flash breakpoints.........................................................................113

6.1 Introduction.......................................................................................... 114

6.2 Licensing .............................................................................................. 115

6.3 Supported devices ................................................................................. 117

6.4 Using flash download and flash breakpoints with different debuggers............ 124

6.4.1 IAR Embedded Workbench...................................................................... 124

6.4.2 Keil MDK .............................................................................................. 125

6.4.3 J-Link GDB Server ................................................................................. 127

6.4.4 J-Link RDI ............................................................................................ 127

7 Device specifics...........................................................................................................129

7.1 Analog Devices...................................................................................... 130

7.1.1 ADuC7xxx ............................................................................................ 130

7.2 ATMEL ................................................................................................. 132

7.2.1 AT91SAM7............................................................................................ 132

7.2.2 AT91SAM9............................................................................................ 134

7.3 Freescale.............................................................................................. 135

7.3.1 MAC71x ............................................................................................... 135

7.4 Luminary Micro ..................................................................................... 136

7.4.1 Stellaris LM3S100 Series ........................................................................ 137

7.4.2 Stellaris LM3S300 Series ........................................................................ 137

7.4.3 Stellaris LM3S600 Series ........................................................................ 137

7.4.4 Stellaris LM3S800 Series ........................................................................ 137

7.4.5 Stellaris LM3S2000 Series....................................................................... 137

7.4.6 Stellaris LM3S6100 Series....................................................................... 137

7.4.7 Stellaris LM3S6400 Series....................................................................... 137

7.4.8 Stellaris LM3S6700 Series....................................................................... 137

7.4.9 Stellaris LM3S6900 Series....................................................................... 137

7.5 NXP ..................................................................................................... 138

7.5.1 LPC...................................................................................................... 139

7.6 OKI ..................................................................................................... 141

7.6.1 ML67Q40x ............................................................................................ 141

7.7 ST Microelectronics ................................................................................ 142

7.7.1 STR 71x ............................................................................................... 143

7.7.2 STR 73x ............................................................................................... 143

7.7.3 STR 75x ............................................................................................... 143

7.7.4 STR91x ................................................................................................ 143

7.7.5 STM32 ................................................................................................. 143

7.8 Texas Instruments................................................................................. 145

7.8.1 TMS470................................................................................................ 145

8 Target interfaces and adapters....................................................................................147

8.1 20-pin JTAG/SWD connector ................................................................... 148

8.1.1 Pinout for JTAG ..................................................................................... 148

8.1.2 Pinout for SWD...................................................................................... 150

8.2 38-pin Mictor JTAG and Trace connector ................................................... 153

8.2.1 Connecting the target board.................................................................... 153

8.2.2 Pinout .................................................................................................. 154

8.2.3 Assignment of trace information pins between ETM architecture versions .......156

8.2.4 Trace signals .........................................................................................156

8.3 19-pin JTAG/SWD and Trace connector .....................................................158

8.3.1 Target power supply ...............................................................................159

8.4 Adapters ...............................................................................................160

8.4.1 JTAG isolator .........................................................................................160

8.4.2 JTAG 14 pin adapter ...............................................................................161

8.4.3 5 Volt adapter........................................................................................162

9 Background information...............................................................................................165

9.1 JTAG ....................................................................................................166

9.1.1 Test access port (TAP) ............................................................................166

9.1.2 Data registers........................................................................................166

9.1.3 Instruction register.................................................................................166

9.1.4 The TAP controller ..................................................................................167

9.2 The ARM core ........................................................................................169

9.2.1 Processor modes ....................................................................................169

9.2.2 Registers of the CPU core ........................................................................169

9.2.3 ARM / Thumb instruction set....................................................................170

9.3 EmbeddedICE ........................................................................................171

9.3.1 Breakpoints and watchpoints ...................................................................171

9.3.2 The ICE registers ...................................................................................172

9.4 Embedded Trace Macrocell (ETM) .............................................................173

9.4.1 Trigger condition ....................................................................................173

9.4.2 Code tracing and data tracing ..................................................................173

9.4.3 J-Trace integration example - IAR EWARM .................................................173

9.5 Embedded Trace Buffer (ETB) ..................................................................177

9.6 Flash programming ................................................................................178

9.6.1 How does flash programming via J-Link / J-Trace work? ..............................178

9.6.2 Data download to RAM............................................................................178

9.6.3 Data download via DCC...........................................................................178

9.6.4 Available options for flash programming....................................................178

9.7 J-Link / J-Trace firmware.........................................................................180

9.7.1 Firmware update ....................................................................................180

9.7.2 Invalidating the firmware ........................................................................180

10 Designing the target board for trace ..........................................................................183

10.1 Overview of high-speed board design........................................................184

10.1.1 Avoiding stubs .......................................................................................184

10.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths) ...............................184

10.1.3 Minimizing Crosstalk ...............................................................................184

10.1.4 Using impedance matching and termination ...............................................184

10.2 Terminating the trace signal ....................................................................185

10.2.1 Rules for series terminators .....................................................................185

10.3 Signal requirements ...............................................................................186

11 Support and FAQs.....................................................................................................187

11.1 Measuring download speed......................................................................188

11.1.1 Test environment ...................................................................................188

11.2 Troubleshooting .....................................................................................189

11.2.1 General procedure..................................................................................189

11.2.2 Typical problem scenarios .......................................................................189

11.3 Signal analysis.......................................................................................191

11.3.1 Start sequence ......................................................................................191

11.3.2 Troubleshooting .....................................................................................191

11.4 Contacting support .................................................................................192

11.5 Frequently Asked Questions.....................................................................193

12 Glossary.....................................................................................................................195

13 Literature and references...........................................................................................201

Chapter 1

Introduction

This chapter gives a short overview about J-Link and J-Trace.

18 CHAPTER 1 Introduction

1.1 J-Link / J-Trace models

J-Link / J-Trace is available in different variations, each designed for different pur-

poses / target devices. Currently, the following models of J-Link / J-Trace are avail-

able:

•J-LinkARM

•J-LinkARMPro

•J-TraceARM

•FlasherARM

• J-Link ColdFire

•J-TraceforCortex-M3

In the following, the different J-Link / J-Trace models are described and the changes

between the different hardware versions of each model are listed. To determine the

hardware version of your J-Link / J-Trace, the first step should be to look at the label

at the bottom side of the unit. J-Links / J-Traces have the hardware version printed

on the back label.

If this is not the case with your J-Link / J-Trace, start JLink.exe. As part of the initial

message, the hardware version is displayed.

1.1.1 Model comparison chart

The following table shows the features which are included in each J-Link/J-Trace

model.

1Most IDEs come with their own flashloaders, so in most cases this feature is not

essential for debugging your applications in flash. The J-Link flash download

(FlashDL) feature is mainly used in debug environments where the debugger does

not come with an own flashloader (e.g. the GNU Debugger). For more information

about how flash download via FlashDL works, please refer to Flash download and

flash breakpoints on page 113.

2In order to use the flash breakpoints with J-Link no additional license for flash

download is required. The flash breakpoint feature allows setting an unlimited num-

ber of breakpoints even if the application program is not located in RAM, but in flash

memory. Without this feature, the number of breakpoints which can be set in flash is

limited to the number of hardware breakpoints (typically two for ARM 7/9, six for

Cortex-M3) For more information about flash breakpoints, please refer to Flash

download and flash breakpoints on page 113.

1.1.2 J-Link bundle comparison chart

The following table shows the features which are included in the available J-Link bun-

dles and Non-commercial package

J-Link J-Link Pro J-Trace Flasher

ARM J-Link CF J-Trace

CM-3

FlashDL1yes(opt) yes yes(opt) yes(opt) yes yes(opt)

FlashBP2yes(opt) yes yes(opt) yes(opt) yes yes(opt)

GDB Server yes(opt) yes yes(opt) yes(opt) no yes(opt)

RDI yes(opt) yes yes(opt) yes(opt) no yes(opt)

J-Flash yes(opt) yes yes(opt) yes yes(opt) yes(opt)

JTAG yes yes yes yes no yes

SWD yes yes no yes no yes

SWO yes yesnononono

USB yes yes yes yes yes yes

Ethernet no yes no no no no

Trace no no yes no no yes

Supported

cores

ARM7/9/

11, Cor-

tex-M0/

M1/M3

ARM7/9/

11, Cor-

tex-M0/

M1/M3

ARM 7/9 ARM 7/9,

Cortex-M3

ColdFire

V2/3/4

ARM 7/9

(no trac-

ing), Cor-

tex-M3

J-Link NCU

(non commer-

cial use)

J-Link

RDI bundle

J-Link

RDI Pro

J-Link

J-Flash

J-Link

GDB Server

Flash DL yes no yes no no

Flash BP yes no yes no no

GDB Server yes no no no yes

RDI no yes yes yes(opt) no

J-Flash no yes yes yes no

20 CHAPTER 1 Introduction

1.1.3 J-Link ARM

J-Link is a JTAG emulator designed for ARM cores. It connects

via USB to a PC running Microsoft Windows 2000, Windows XP,

Windows 2003 or Windows Vista. J-Link has a built-in 20-pin

JTAG connector, which is compatible with the standard 20-pin

connector defined by ARM.

1.1.3.1 Additional features

• Serial Wire Debug supported *

• Serial Wire Viewer supported *

• Download speed up to 720 KBytes/second **

• DCC speed up to 800 Kbytes/second **

• RDI interface available, which allows using J-Link with RDI

compliant software

* = Supported by J-Link hardware version 6

** = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG

speed.

1.1.3.2 Specifications*

* = J-Link hardware revision 5 and up.

Power Supply USB powered <50mA if target power is

off.

USB Interface USB 2.0, full speed

Target Interface JTAG 20-pin (14-pin adapter available)

Serial Transfer Rate between J-Link and Tar-

get up to 12 MHz

Supported Target Voltage 1.2 - 3.3 V, 5V tolerant

Target supply voltage 4.5V .. 5V (if powered with 5V on USB)

Target supply current Max. 300mA

Operating Temperature +5°C ... +60°C

Storage Temperature -20°C ... +65 °C

Relative Humidity (non-condensing) <90% rH

Size (without cables) 100mm x 53mm x 27mm

Weight (without cables) 70g

Electromagnetic Compatibility (EMC) EN 55022, EN 55024

Supported OS

Microsoft Windows 2000

Microsoft Windows XP

Microsoft Windows XP x64

Microsoft Windows 2003

Microsoft Windows 2003 x64

Microsoft Windows Vista

Microsoft Windows Vista x64

Table 1.1: J-Link specifications

Other manuals for J-Link

This manual suits for next models

Table of contents

Segger J-Link User manual