Texas Instruments TPA3124D2 User manual

1
FEATURES APPLICATIONS
DESCRIPTION
1 Fm
SD
Mute Control
PVCCL
TPA3124D2
SIMPLIFIED APPLICATION CIRCUIT
PVCCR
VCLAMP
GAIN1
BYPASS
1 Fm
1 Fm
0.22 Fm
AGND
Left Channel
Right Channel
10 V to 26 V 10 V to 26 V
4-Step Gain Control
Shutdown Control
LIN
RIN
BSR
BSL
PGNDR
PGNDL
0.22 Fm
33 Hm
33 Hm470 Fm
0.22 Fm
1 Fm
470 Fm
GAIN0
AVCC
MUTE
ROUT
LOUT
S0267-02
0.22 Fm
TPA3124D2
www.ti.com ........................................................................................................................................................................................................ SLOS578 – MAY 2008
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER
•Flat Panel Televisions234
•10-W/Ch Into an 8- ΩLoad From a 24-V Supply
•DLP
®
TVs•15-W/Ch into a 4- ΩLoad from a 22-V Supply
•CRT TVs•30-W/Ch into a 8- ΩLoad from a 22-V Supply
•Powered Speakers•Operates From 10 V to 26 V•Can Run From +24 V LCD Backlight Supply•Efficient Class-D Operation Eliminates Need
The TPA3124D2 is a 15-W (per channel), efficient,for Heat Sinks
class-D audio power amplifier for driving stereo•Four Selectable, Fixed-Gain Settings
speakers in a single-ended configuration; or, a mono•Internal Oscillator (No External Components
speaker in a bridge-tied-load configuration. TheTPA3124D2 can drive stereo speakers as low as 4 Ω.Required)
The efficiency of the TPA3124D2 eliminates the need•Single-Ended Analog Inputs
for an external heat sink when playing music.•Thermal and Short-Circuit Protection With
The gain of the amplifier is controlled by two gainAuto Recovery
select pins. The gain selections are 20, 26, 32, and•Space-Saving Surface Mount 24-Pin TSSOP
36 dB.Package
The patented start-up and shutdown sequences•Advanced Power-Off Pop Reduction
minimize pop noise in the speakers without additionalcircuitry.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DLP is a registered trademark of Texas Instruments.3System Two, Audio Precision are trademarks of Audio Precision, Inc.4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

1
2
3
4
5
6
7
8
9
10
11
12
PVCCL
SD
PVCCL
MUTE
LIN
RIN
BYPASS
AGND
AGND
PVCCR
VCLAMP
PVCCR
24
23
22
21
20
19
18
17
16
15
14
13
PGNDL
PGNDL
LOUT
BSL
AVCC
AVCC
GAIN0
GAIN1
BSR
ROUT
PGNDR
PGNDR
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
PWP (TSSOP) PACKAGE
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O/P DESCRIPTION24-PINNAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance toSD 2 I
AVCCRIN 6 I Audio input for right channelLIN 5 I Audio input for left channelGAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCCGAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCCMute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCCBSL 21 I/O Bootstrap I/O for left channelPVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCCLOUT 22 O Class-D -H-bridge positive output for left channelPGNDL 23, 24 P Power ground for left-channel H-bridgeVCLAMP 11 P Internally generated voltage supply for bootstrap capacitorsBSR 16 I/O Bootstrap I/O for right channelROUT 15 O Class-D -H-bridge negative output for right channelPGNDR 13, 14 P Power ground for right-channel H-bridge.PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCCAGND 9 P Analog ground for digital/analog cells in coreAGND 8 P Analog ground for analog cells in coreReference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time viaBYPASS 7 O
external capacitor sizing.AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCLConnect to ground. Thermal pad should be soldered down on all applications to secure theThermal pad Die pad P
device properly to the printed wiring board.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPA3124D2
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over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage AVCC, PVCC – 0.3 to 30 VV
I
Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V
CC
+ 0.3 VV
IN
Analog input voltage RIN, LIN – 0.3 to 7 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range – 40 to 85 °CT
J
Operating junction temperature range – 40 to 150 °CT
stg
Storage temperature range – 65 to 150 °CSE Output Configuration 3.2R
L
Load resistance (minimum value) ΩBTL Output Configuration 6.4Human body model (all pins) ± 2 kVESD Electrostatic Discharge
Charged-device model (all
± 500 Vpins)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE
(1) (2)
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °C
24-pin TSSOP 4.16 W 33.3 mW/ °C 2.67 W 2.16 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad mustbe soldered to a thermal land on the printed-circuit board. See the PowerPAD Thermally Enhanced Package application note(SLMA002 ).
MIN MAX UNIT
V
CC
Supply voltage PVCC, AVCC 10 26 VV
IH
High-level input voltage SD, MUTE, GAIN0, GAIN1 2 VV
IL
Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 VSD, V
I
= V
CC
, V
CC
= 30 V 125I
IH
High-level input current MUTE, V
I
= V
CC
, V
CC
= 30 V 125 µAGAIN0, GAIN1, V
I
= V
CC
, V
CC
= 24 V 125SD, V
I
= 0, V
CC
= 30 V 1I
IL
Low-level input current MUTE, V
I
= 0 V, V
CC
= 30 V 1 µAGAIN0, GAIN1, V
I
= 0 V, V
CC
= 24 V 1T
A
Operating free-air temperature – 40 85 °C
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DC CHARACTERISTICS
AC CHARACTERISTICS
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
T
A
= 25 °C, V
CC
= 24 V, R
L
=8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage| V
OS
| (measured differentially in BTL V
I
= 0 V, A
V
= 36 dB 7.5 50 mVmode as shown in Figure 36 )V
(BYPASS)
Bypass output voltage No load AVCC/8 VI
CC(q)
Quiescent supply current SD = 2 V, MUTE = 0 V, no load 16 30 mAI
CC(q)
Quiescent supply current in
MUTE = 0.8 V, no load 16 mAmute modeI
CC(q)
Quiescent supply current in
SD = 0.8 V, no load 0.39 1 mAshutdown moder
DS(on)
Drain-source on-state 450210 m Ωresistance
GAIN0 = 0.8 V 18 20 22GAIN1 = 0.8 V
GAIN0 = 2 V 24 26 28G Gain dBGAIN0 = 0.8 V 30 32 34GAIN = 2 V
GAIN0 = 2 V 34 36 38Mute attenuation V
I
= 1 Vrms – 80 dB
T
A
= 25 °C, V
CC
= 24 V, R
L
= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
= 24, V
ripple
= 200 mV
PP
100 Hz – 48ksvr Supply ripple rejection dBGain = 20 dB
1 kHz – 52Output power at 1% THD+N V
CC
= 24 V, f = 1 kHz 8P
O
WOutput power at 10% THD+N V
CC
= 24 V, f = 1 kHz 10Total harmonic distortion + f = 1 kHz, P
O
= 5 W 0.04%THD+N
noise
125 µV20 Hz to 22 kHz, A-weighted filter,V
n
Output integrated noise floor
Gain = 20 dB
– 78 dBVCrosstalk P
O
= 1 W, f = 1 kHz; gain = 20 dB – 70 dBMax output at THD+N < 1%, f = 1 kHz,SNR Signal-to-noise ratio – 92 dBgain = 20 dBThermal trip point 150 °CThermal hysteresis 30 °Cf
OSC
Oscillator frequency 250 300 350 kHz
Δt mute Mute delay Time from mute input switches high until 30 µsecoutputs muted
Δt unmute Unmute delay Time from mute input switches low until 120 msecoutputs unmuted
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FUNCTIONAL BLOCK DIAGRAM
LS
HS
OSC/RAMP
BYPASS
AVDDAVCC
LIN
RIN
MUTE
BYPASS
GAIN1
GAIN0
SD
BSL
PVCCL
LOUT
PGNDL
VCLAMP
BSR
PVCCR
ROUT
PGNDR
VCLAMP
AVDD
AVDD
AVDD/2
AVDD AVDD
AVDD/2
REGULATOR
AGND
+
+
–
–
CONTROL
BIAS
THERMAL
MUTE
CONTROL
AV
CONTROL
SC
DETECT
SC
DETECT
LS
HS
VCLAMP
TPA3124D2
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TYPICAL CHARACTERISTICS
f − Frequency − Hz
20
VCC = 12 V
RL= 4 Ω(SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G001
1
PO= 0.5 W
PO= 2.5 W
0.01
PO= 1 W
f − Frequency − Hz
20
VCC = 18 V
RL= 6 Ω(SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G002
1
PO= 0.5 W
PO= 2.5 W
0.01
PO= 1 W
f − Frequency − Hz
20
VCC = 18 V
RL= 8 Ω(SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G003
1
PO= 2.5 W
0.01 PO= 1 W
f − Frequency − Hz
20
VCC = 24 V
RL= 8 Ω(SE)
Gain = 20 dB
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
0.001
10
20k
0.1
G004
1
PO= 1 W
PO= 5 W
0.01
PO= 2.5 W
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 1. Figure 2.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY
Figure 3. Figure 4.
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PO− Output Power − W
0.01
RL= 4 Ω(SE)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G005
1
VCC = 12 V
PO− Output Power − W
0.01
RL= 6 Ω(SE)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G006
1
VCC = 12 V
VCC = 18 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G008
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 12 V
VO= 1 Vrms
RL= 4 Ω(SE)
PO= 0.25 W
Gain = 20 dB
PO− Output Power − W
0.01
RL= 8 Ω(SE)
Gain = 20 dB
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G007
1
VCC = 12 V
VCC = 18 V
VCC = 24 V
TPA3124D2
www.ti.com ........................................................................................................................................................................................................ SLOS578 – MAY 2008
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsOUTPUT POWER OUTPUT POWER
Figure 5. Figure 6.
TOTAL HARMONIC DISTORTION + NOISE CROSSTALKvs vsOUTPUT POWER FREQUENCY
Figure 7. Figure 8.
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−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G009
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 18 V
VO= 1 Vrms
RL= 8 Ω(SE)
PO= 0.125 W
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
f − Frequency − Hz
Crosstalk − dB
G010
20 100 1k 10k 20k
Left to Right
Right to Left
VCC = 24 V
VO= 1 Vrms
RL= 8 Ω(SE)
PO= 0.125 W
Gain = 20 dB
f − Frequency − Hz
Phase − °
20 100 1k 100k10k
G011
600
500
400
300
200
100
0
−100
−200
0
5
10
15
20
25
30
35
40
Gain − dB
Phase
Gain
VCC = 24 V
RL= 4 Ω(SE)
Gain = 20 dB
Lfilt = 22 µH
Cfilt = 0.68 µF
Cdc = 1000 µF
f − Frequency − Hz
Phase − °
20 100 1k 100k10k
G012
600
500
400
300
200
100
0
−100
−200
0
5
10
15
20
25
30
35
40
Gain − dB
Phase
Gain
VCC = 24 V
RL= 8 Ω(SE)
Gain = 20 dB
Lfilt = 33 µH
Cfilt = 0.22 µF
Cdc = 470 µF
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
CROSSTALK CROSSTALKvs vsFREQUENCY FREQUENCY
Figure 9. Figure 10.
GAIN/PHASE GAIN/PHASEvs vsFREQUENCY FREQUENCY
Figure 11. Figure 12.
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VCC − Supply Voltage − V
0
1
2
3
4
5
6
7
8
9
10
10 11 12 13 14 15
PO− Output Power − W
G013
THD+N = 1%
THD+N = 10%
RL= 4 Ω(SE)
Gain = 20 dB
VCC − Supply Voltage − V
0
2
4
6
8
10
12
14
10 12 14 16 18 20 22 24 26
PO− Output Power − W
G014
THD+N = 1%
THD+N = 10%
RL= 8 Ω(SE)
Gain = 20 dB
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
01234567
Efficiency − %
G015
RL= 4 Ω(SE)
Gain = 20 dB
VCC = 12 V
PO− Output Power − W
0
10
20
30
40
50
60
70
80
90
100
0 2 4 6 8 10 12
Efficiency − %
G016
VCC = 18 V
RL= 8 Ω(SE)
Gain = 20 dB
VCC = 24 V
TPA3124D2
www.ti.com ........................................................................................................................................................................................................ SLOS578 – MAY 2008
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
OUTPUT POWER OUTPUT POWERvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 14.A. Dashed line represents thermally limitedregion.
Figure 13.
EFFICIENCY EFFICIENCYvs vsOUTPUT POWER OUTPUT POWER
Figure 15. Figure 16.
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PO− Output Power − W
0.0
0.3
0.6
0.9
1.2
1.5
0 3 6 9 12 15
ICC − Supply Current − A
G017
RL= 4 Ω(SE)
Gain = 20 dB
VCC = 12 V
PO− Output Power − W
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25
ICC − Supply Current − A
G018
VCC = 24 V
VCC = 18 V
RL= 8 Ω(SE)
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Power Supply Rejection Ratio − dB
G019
20 100 1k 10k 20k
VCC = 24 V
VO(ripple) = 0.2 VPP
RL= 4 Ω(SE)
Gain = 20 dB
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Power Supply Rejection Ratio − dB
G025
20 100 1k 10k 20k
VCC = 24 V
VO(ripple) = 0.2 VPP
RL= 8 Ω(SE)
Gain = 20 dB
TPA3124D2
SLOS578 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.
SUPPLY CURRENT SUPPLY CURRENTvs vsOUTPUT POWER OUTPUT POWER
Figure 17.
A. Dashed line represents thermally limitedregion.
Figure 18.
POWER SUPPLY REJECTION RATIO POWER SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 19. Figure 20.
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