Texas Instruments 5-6K User manual

1 Introduction
User's GuideSLAU104C – May 2004 – Revised March 2009
5–6K Interface Board
The 5-6K Interface Board provides a complete system development platform using evaluation modulesfrom the Data Acquisition Products Group. This board passes signals from TMS320C5000™ andTMS320C6000™ DSK platforms featuring the 80-pin daughtercard connectors defined in the TMS320Cross-Platform Daughtercard Interface (SPRA711 ), to a variety of analog-to-digital and digital-to-analogconverters. When combined with sensor or amplifier boards, it can provide a complete data acquisitionsystem for a variety of applications.
Contents1 Introduction ................................................................................................................... 12 Power Connections to the Interface Card ................................................................................ 23 Serial EVM Sites ............................................................................................................. 34 Parallel EVM Site ............................................................................................................ 55 5-6K Interface Bill of Material .............................................................................................. 86 Related Documentation from Texas Instruments ........................................................................ 97 5-6K Interface Board Assembly and Schematics ........................................................................ 9
List of Tables
1 External Power Connections ............................................................................................... 22 Signal Conditioning I/O Connections ...................................................................................... 23 Signal Conditioning Power Connections—JP1, JP2, JP3, and JP4 .................................................. 34 Digital I/O Connections—J15 and J16 .................................................................................... 35 EVM Power Connections—JP5 and JP6 ................................................................................. 46 EVM Analog I/O Connections—J10 and J12 ............................................................................ 47 Parallel Control Connections ............................................................................................... 58 Parallel EVM Clocking Options via J14 ................................................................................... 69 External Interrupt Source via J13 .......................................................................................... 610 Parallel Control Connections ............................................................................................... 711 Bill of Material ................................................................................................................ 8
The 5-6K Interface Board provides data converter customers with flexibility for the evaluation of dataacquisition products from Texas Instruments. The Interface Board maintains a compatible interface withthe TMS320™ DSP family according to the guidelines set forth in the TMS320 Cross-PlatformDaughtercard Specification (SPRA711 ). Signal names and references to the multichannel buffered serialport (McBSP) found throughout this document are common to those found in the SPRA711 document.
The Interface Board consists of two signal conditioning sites, two serial EVM sites, and a parallel EVMsite. Regardless of the interface type, all EVMs compatible with the 5-6K Interface Board have a standardanalog interface and standard power connector. Three-position screw terminals J1 and J2 andtwo-position screw terminals J6, J8, J9, and J11 provide access to a common power bus routed to allsites.
TMS320C5000, TMS320C6000, TMS320 are trademarks of Texas Instruments.
SLAU104C – May 2004 – Revised March 2009 5–6K Interface Board 1Submit Documentation Feedback

2 Power Connections to the Interface Card
2.1 Signal Conditioning Sites
2.1.1 Signal Conditioning Analog I/O Connection
Power Connections to the Interface Card www.ti.com
The screw terminals along the bottom edge of the Interface Board give access to the common power bus.Three-port terminals J1 and J2 provide analog power. Two-port terminals J6, J8, J9, and J11 provide thedigital voltages. Two jumpers, W2 and W3, located on the Interface Board give the user the option ofusing DSK +5 V and +3.3 V for the digital power. Analog power must be supplied from an external source.Table 1 shows the typical external power connections.
Table 1. External Power Connections
Screw Terminal Applied Voltage Typical Function
Analog Voltage—provides analog power for signal conditioning, sensorJ1 ±VA ( ±18 V Max)
boards, amplifiers, etc.Analog Voltage—provides analog power for signal conditioning, sensorJ2 ±5V ( ±5.5 V Max)
boards, amplifiers, etc.J6 +5 (5.5 V Max) Digital Voltage—power to digital logic - ADCs, DACs, etc.J8 +VD (undefined) Digital Voltage—Reserved for future useJ9 +1.8 V (2.3 V Max) Digital Voltage—core logic voltage for Codecs etc.J11 +3. 3 V (3.7 V Max) Digital Voltage—power to digital logic – ADCs, DACs, etc.
The signal conditioning sites provide a 20-pin analog I/O header and a 6-pin header for the analog powersupply connections.
The analog I/O connectors, J3 and J4, provide up to eight single-ended or four differential channelsto/from the data converter. External reference voltages can also be applied to the data converter throughthe analog I/O connector. Because the reference requirements vary by converter type, no restrictions areplaced on the input voltage levels. Be sure to check the documentation for the EVM before applying anyinput signals. Single- and dual-channel converters leave the unused pins open. Table 2 shows thestandard analog connector pinout. See Section 3.3 for details on applying differential signals.
Table 2. Signal Conditioning I/O Connections
Signal Pin Number Signal
A0- 1 2 A0A1- 3 4 A1A2- 5 6 A2A3- 7 8 A3AGND 9 10 A4AGND 11 12 A5AGND 13 14 A6VCOM 15 16 A7AGND 17 18 REF-AGND 19 20 REF+
The 20-pin headers located beside JP1 and JP2 provide stability for the signal conditioning boards—nosignals are routed to or from these connectors. These connectors are labeled Analog 1 and Analog 2 inthe assembly drawing found in Section 7 .
List of Tables2 SLAU104C – May 2004 – Revised March 2009Submit Documentation Feedback

2.2 Signal Conditioning Power Connector
3 Serial EVM Sites
3.1 Serial Digital I/O Connections
3.2 Chip Select, Frame Sync and Interrupt Options
www.ti.com Serial EVM Sites
The Interface Board provides a common power bus to both signal conditioning sites. The power connectorused on the Interface Board is a 6-pin male header. Four power connectors JP1, JP2, JP3, and JP4 areprovided—each with the same pinout. This allows an analog-to-digital (ADC) converter to use the samesignal conditioning board as a digital-to-analog (DAC) converter, simply by rotating the signal conditioningboard 180 degrees.
Table 3 shows the power connector voltages supplied to the signal conditioning module.
Table 3. Signal Conditioning Power Connections—JP1, JP2, JP3, and JP4
Signal Pin Number Signal
+VA 1 2 -VA+5VA 3 4 -5VAAGND 5 6 AGND
The serial interface consists of two digital I/O connectors (J15 and J16), two power connectors (JP5 andJP6), and two analog I/O connectors (J10 and J12). The analog I/O connectors are configured as passthrough connections from/to the signal conditioning sites. See Section 2.1 for more information.
The serial site digital I/O connectors are 20-pin headers that provide access to the serial interface signalsdefined in the TMS320 Cross-Platform Daughtercard Specification (SPRA711 ). These signals are basedon the multichannel buffered serial port (McBSP) interface found on most Texas Instruments DSPs.Table 4 shows the standard serial connector pinout.
Table 4. Digital I/O Connections—J15 and J16
Signal
(1)
Signal
(1)Pin NumberSite 1 (J15) Site 2 (J16) Site 1 (J15) Site 2 (J16)
DC_CNTLa DC_CNTLb 1 2 TP Access TP AccessDC_CLKXa DC_CLKXb 3 4 DGND DGNDDC_CLKRa DC_CLKRb 5 6 TP Access TP AccessDC_FSXa DC_FSXb 7 8 TP Access TP AccessDC_FSRa DC_FSRb 9 10 DGND DGNDDC_DXa DC_DXb 11 12 TP Access TP AccessDC_DRa DC_DRb 13 14 TP Access TP AccessEVM_INTa EVM_INTb 15 16 TP Access TP AccessDC_TOUTa DC_TOUTb 17 18 DGND DCNDTP Access TP Access 19 20 TP Access TP Access
(1)
Revision B boards include 470- Ωpulldown resistors at all points listed as TP Access via 6-position slide switches SW1 andSW2.
DC_CNTLa and DC_CNTLb are routed directly to pin 1 of the Digital I/O connectors (J15 and J16respectively) on Revision A Interface Boards. Revision B interface boards include jumpers W12 and W13which apply the DC_CNTLx signal (default) or digital ground (shunt pins 2-3) to pin 1 of the digital I/Oconnectors.
SLAU104C – May 2004 – Revised March 2009 List of Tables 3Submit Documentation Feedback

3.3 EVM Power Connector
3.4 EVM Analog I/O Connector
Serial EVM Sites www.ti.com
Revision B interface boards also include jumpers W10 and W11 which allow the user to apply the FSXsignal (default) or DC_CNTLx signal (shunt pins 2-3) to pin 7 of the digital I/O connectors. W10 controlsthe application of DC_FSXa or DC_CNTLa on J15, while W11 controls the application of DC_FSXb orDC_CNTLb on J16.
Jumpers W8 and W9 allow the signals applied to EVM_INTa or EVM_INTb to be directly sourced from thedata-converter EVM when the shunts are installed on pins 1-2 (default). Moving the shunt on W8 to pins2-3 sends the EVM interrupt signal through a single-gate inverter (U5) before being sent to DC-INTa onthe DSK. W9 controls the polarity of the signal applied to DC-INTc via U6.
The Interface Board provides a common power bus to both serial sites. The power connector used on theInterface Board is a 10-pin male header. Two power connectors JP5 and JP6 are provided—each with thesame pinout. JP5 services serial Site 2, while JP6 services serial Site 1. Table 5 shows thepower-connector voltages supplied to the EVM.
Table 5. EVM Power Connections—JP5 and JP6
Signal Pin Number Signal
+VA 1 2 -VA+5VA 3 4 -5VADGND 5 6 AGND+1.8VD 7 8 VD1+3.3VD 9 10 +5VD
As mentioned previously, the analog I/O connectors act as pass-through connectors to the signalconditioning sites. Table 6 shows the analog I/O connections to the serial and parallel EVM sites.
Table 6. EVM Analog I/O Connections—J10 and J12
(1)
Signal Pin Number Signal
A0- 1 2 A0A1- 3 4 A1A2- 5 6 A2A3- 7 8 A3AGND 9 10 A4AGND 11 12 A5AGND 13 14 A6VCOM 15 16 A7AGND 17 18 REF-AGND 19 20 REF+
(1)
J10 and J12 are also used for the parallel EVM site.
When applying differential signals to a data converter EVM, the signal pairs may be applied between pinpairs 1-2, 3-4, 5-6, and 7-8, or pin pairs 2-4, 6-8, 10-12, and 14-16. The pin assignment for the signal pairis determined by the EVM being used. See the specific EVM user’s guide for implementation details.
List of Tables4 SLAU104C – May 2004 – Revised March 2009Submit Documentation Feedback

4 Parallel EVM Site
4.1 Parallel Analog I/O and Power Connections
4.2 Parallel Control Connector—J18
www.ti.com Parallel EVM Site
The parallel interface consists of a 48-pin header (J17), which provides access to up to 24 parallel databits and a 20-pin parallel control header (J18). The parallel control header provides four multiplexedaddress lines, configurable read and write strobes, configurable interrupts, and chip-select and clocksignals. Analog I/O and power is also provided.
The parallel site uses the same analog I/O and power connections described in the serial interface sectionof this manual. Typically, a parallel-ADC EVM uses the analog interface connector located at J10 and thepower connector located at JP5. See Section 3 for pinout details. A parallel-DAC EVM typically uses theanalog interface connector J12, presenting the opportunity to stack certain EVMs.
The parallel control connector feeds chip-select, read, write, and address lines to the parallel EVMs. Theaddress decoding for most parallel EVMs is done on the EVM card itself, allowing the possibility ofstacking several cards together. Table Table 7 shows the typical signals found on parallel interface EVMs,designed to be used with the 5–6K Interface Board
Table 7. Parallel Control Connections
Signal Pin Number Signal
DC_CSx 1 2 DGNDWR (R/W) 3 4 DGNDRD 5 6 DGNDEVM_A0 7 8 DGNDEVM_A1 9 10 DGNDEVM_A2 11 12 DGNDEVM_A3 13 14 DGNDGPIO (SPARE–NC) 15 16 DGNDTOUTa 17 18 DGNDINT 19 20 DGND
DC_CSx is defined in the TMS320 Cross-Platform Daughtercard Specification. This signal is intended toact as a chip-select to the EVM, not necessarily the actual data converter being evaluated. Carefully readthe documentation that came with your EVM for details on how this signal is used. Revision-B Interfaceboards include jumper W16 which applies DC_CSa (default) or DC_CSb (shunt pins 2-3) to J18 pin 1.
The write and read strobes can be controlled through jumpers W4 and W5 on the Interface Card. With W4and W5 in their default positions (shunt on pins 2-3), WR and RD are defined as in the TMS320Cross-Platform Daughtercard Specification. With the shunts on W4 and W5 in positions 1-2, combinationlogic located on the interface card can provide a simple strobing arrangement which may be useful withthe TMS320C5402 DSK.
The EVM address lines EVM_A0 through EVM_A3 are fed from a four-bit 2:1 bus switch, U1. Typically,this provides access to DSP address lines A2..A5, or A14..A17. A shunt on W1 (default) applies the DSKaddress lines A2..A4 to the parallel control connector; removing the shunt from W1 applies address linesA14..A17. The actual address lines vary depending on the DSK used; see your DSK documentation forthe exact address locations.
SLAU104C – May 2004 – Revised March 2009 List of Tables 5Submit Documentation Feedback

4.3 Inverted Interrupts
Parallel EVM Site www.ti.com
The interface card provides four options for a clock source to the parallel EVM interface with use of a2-mm shunt on J14.
Table 8. Parallel EVM Clocking Options via J14
Shunt on Pins Clock Source
1–2 DC_TOUTa3–4 DC_TOUTa5–6 DC_CLKXa7–8 DC_CLKXb
The interface card provides two options for an external interrupt source to the DSP with use of a 2-mmshunt on J15.
Table 9. External Interrupt Source via J13
(1)
Shunt on Pins Connects To:
Rev A PWB Rev B PWB
1–2 DC_INTa DC_INTb3–4 DC_INTb DC_INTb5–6 DC_INTc DC_INTd7–8 DC_INTd DC_INTd
(1)
External interrupts shown in this table are based on the TMS320C6711 DSK.
Jumper W7 on the 5–6K Interface Board revision B expands the interrupt capabilities of certaindata-converter EVMs. W7 controls the signal applied to J13 via single-gate inverter U7. When a shunt isinstalled on W7-pins 1-2 (default), the interrupt signal is applied directly to J13. Installing the shunt onW7-pins 2-3 provides an interrupt inverted signal to J13 via U7.
List of Tables6 SLAU104C – May 2004 – Revised March 2009Submit Documentation Feedback

4.4 Parallel Data Bus Connector—J17
www.ti.com Parallel EVM Site
The parallel data connector used on the Interface Card is a 48-pin male header. Typical parallel EVMshave a data bus that is a minimum of 16 bits wide and a maximum of 24 bits. Bus expansion is done in4-bit increments. Data is aligned LSB to LSB.
Table 10 shows the parallel data bus connections.
Table 10. Parallel Control Connections
Signal Pin Number Signal
D0 1 2 DGNDD1 3 4 DGNDD2 5 6 DGNDD3 7 8 DGNDD4 9 10 DGNDD5 11 12 DGNDD6 13 14 DGNDD7 15 16 DGNDD8 17 18 DGNDD9 19 20 DGNDD10 21 22 DGNDD11 23 24 DGNDD12 25 26 DGNDD13 27 28 DGNDD14 29 30 DGNDD15 31 32 DGNDD16 33 34 DGNDD17 35 36 DGNDD18 37 38 DGNDD19 39 40 DGNDD20 41 42 DGNDD21 43 44 DGNDD22 45 46 DGNDD23 47 48 DGND
SLAU104C – May 2004 – Revised March 2009 List of Tables 7Submit Documentation Feedback

5 5-6K Interface Bill of Material
5-6K Interface Bill of Material www.ti.com
Table 11. Bill of Material
Item Qty Designators Description Manufacturer Mfg. Part Number
1 1 N/A Printed Wiring Board Texas InstrumentsC1 C2 C3 C4 C52 6 0.1uF, 0805, Ceramic, X7R, 50V, 10% Panasonic ECJ-2YB1H104KC63 2 J1 J2 3 Terminal Screw Connector OST ED1515J3 J4 ANALOG4 4 10 Pin, Dual Row, TH Header (20 Pos.) Samtec TSW-110-07-L-D1 & 25 4 J6 J8 J9 J11 2 Terminal Screw Connector OST ED1514J10 J12 J15 J16 10 Pin, Dual Row, SMT Header6 5 Samtec TSM-110-01-T-DV-PJ18 (20 Pos.)7 2 J13 J14 4 Pin, Dual Row, 2mm Header (8 Pos.) Samtec TMM-104-03-T-D24 Pin, Dual Row, SMT Header8 1 J17 Samtec TSM-124-01-T-DV-P(48 Pos.)9 2 J19 J20 80 Pin SMT connector Samtec TFM-140-32-S-D-LC10 4 JP1 JP2 JP3 JP4 3 Pin, Dual Row, TH Header (6 Pos.) Samtec TSW-103-07-L-D11 2 JP5 JP6 5 Pin, Dual Row, SMT Header (10 Pos.) Samtec TSM-105-01-T-DV-P12 2 R1 R3 10K ohm, 0805, .1W Resistor Yageo America 9C08052A1002JLHFT13 1 R2 49.9 ohm, 0805, 1%, .1W Resistor Yageo America 9C08052A49R9FKHFT14 2 R5 R7 470 ohm, 8 Element Array CTS 742C163471JTR15 2 SW1 SW2 CTS 219 Series SMT SPST Switch CTS 219-6LPSTTP1 TP2 CLKs16 4 Red Test Point Loop Keystone 5000DGND17 1 U1 SN74CBT3257 TI SN74CBT3257PWR18 4 U2 U5 U6 U7 1G04 TI SN74AHC1G04DBVR19 2 U3 U4 1G32 TI SN74AHC1G32DBVR20 1 W1 2 Pin Header - .1"centers Samtec TSW-102-07-L-S21 3 W2 W3 W6 3 Pin Header - .1" centers Samtec TSW-103-07-L-SW4 W5 W7 W8 W922 9 W10 W11 W12 3 Pin 2mm Header Samtec TMM-103-03-T-SW13
8List of Tables SLAU104C – May 2004 – Revised March 2009Submit Documentation Feedback

Parallel Data Bus
Parallel Control
Analog 2
Analog 1
Analog I/O = J10
Digital I/O = J16
Power = JP6
Analog I/O = J12
Digital I/O = J15
Power = JP5
Analog I/O = J4
Power = JP2 or JP4
Analog I/O = J10 (ADC’s) or J12 (DAC’s)
Parallel Data Bus = J17
Parallel Control = J18
Power = JP5
Analog I/O = J3
Power = JP1 or JP3
Assy. Revison
Label
Indicates Jumper
Defaults

#4-40 x ¼ inch - 3 places
(optional)

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Revision History
REV ECN Number Approved
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DC_A14DC_A15 DC_A16DC_A17
DC_D0DC_D1 DC_D2DC_D3 DC_D4DC_D5 DC_D6DC_D7
DC_D8DC_D9 DC_D10DC_D11 DC_D12DC_D13 DC_D14DC_D15
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Peripheral Connector
3.3Vdsk
DC_CLKXb
DC_FSXb DC_DXb
DC_CLKRb
DC_FSRb DC_DRb
DC_CLKXa
DC_FSXa DC_DXa
DC_CLKRa
DC_FSRa DC_DRa
DC_TOUTa DC_TINa
DC_INTb
DC_TOUTb DC_TINb
DC_INTa
DC_CNTLb
DC_INTc
DC_CLKOUT
DC_INTd
DC_CNTLa
I/O Strobe
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J17
24X2X.1
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DC_CNTLa
DC_CLKXa
DC_CLKRa
DC_FSXa
DC_FSRa
DC_DXa
DC_DRa
DC_INTa
DC_TOUTa
GPIO_5a
DC_CNTLb
DC_CLKXb
DC_CLKRb
DC_FSXb
DC_FSRb
DC_DXb
DC_DRb
DC_INTc
DC_TOUTb
DC_D0
DC_D1
DC_D2
DC_D3
DC_D4
DC_D5
DC_D6
DC_D7
DC_D8
DC_D9
DC_D10
DC_D11
DC_D12
DC_D13
DC_D14
DC_D15
+5VD+3.3VD
3.3Vdsk
Memory Connector
5Vdsk
5Vdsk
5Vdsk
5Vdsk
DC_IS#
C1
0.1uF
C4
0.1uF
C3
0.1uF
C2
0.1uF
DC_D16
DC_D17
DC_D18
DC_D19
DC_D20
DC_D21
DC_D22
DC_D23
DC_D16DC_D17 DC_D18DC_D19 DC_D20DC_D21 DC_D22DC_D23
CLKSx
CLKSx
R2
49.9ohm
CLKSx
DC_A14
DC_A15
DC_A16
DC_A17
DC_A2
DC_A3
DC_A4
DC_A5
S1
VCC
16 GND 8
OE
15
1A 4
2A 7
3A 9
4A 12
3B1
11 3B2
10
1B1
21B2
32B1
52B2
6
4B1
14 4B2
13
U1
SN74CBT3257PWR R1
10K
W1
+3.3VD
+5VD DC_CSa#
DC_AWE#
DC_TOUTa
GPI/A0
GPI/A1
GPI/A2
GPI/A3
GPI/A4
53
U4
SN74AHC1G32
53
U3
SN74AHC1G32
2 4
53
U2
SN74AHC1G04
I/O Strobe
DC_AWE#
+3.3VD
+3.3VD+3.3VD
WR#
RD#
W5
W4
DC_ARE#
WR#
RD#
SCL SCL
SDA SDA
GPIO_0a
GPIO_1a
GPIO_2a
GPIO_3a
GPIO_4a
GPIO_0b
GPIO_1b
GPIO_2b
GPIO_3b
GPIO_4b
GPIO_5b
W6
CLKs
DGND
1 2
3 4
5 6
7 8
J13
DC_INTb
DC_INTd
1 2
3 4
5 6
7 8
J14
DC_CLKXb
DC_CLKXa
DC_TOUTb
EDGE #6441282
B
1 2
B
5-6K Interface Board Schematic
A Initial Release TH
Serial EVM Digital Interface
SPRA711 Daughtercard Interface
Parallel Data
Parallel Control
R3
10K
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SCL
SDA
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SN74AHC1G04
+3.3VD
W7
HPI Interface
24
53
U6
SN74AHC1G04
+3.3VD
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U5
SN74AHC1G04
+3.3VD
W8
EVM_INTa
EVM_INTa
EVM_INTb
EVM_INTb
W10 W11
FS/CSa FS/CSb
FS/CSa FS/CSb
DC_CNTLb DC_CNTLa
C5
0.1uF
C6
0.1uF
Note: GPIO Test Points to Switch - See Page 2
W12 W13
DC_STAT0DC_STAT1
TP20 TP21
DC_STAT0 DC_STAT1
I2C Connections
from C6713 DSK
(User Installed)
User Option User Option
B Design Enhancements 04/02/04

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+5VD
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JP5
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J1
-VA
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2
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J10
W2W3
5Vext
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+VA -VA+5VA -5VA
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EDGE #6441282
B
2 2
B
Amplifier Card Power Connections
DAP EVM Power Connections Interface Card Digital Power Connections
Interface Card Analog Power Connections
Signal Conditioning In/Out to EVM Analog In/Out
Site 1
Site 2
Site 1
Site 2
Site 1
Site 2
1
2
3
4
5
6 7
8
9
10
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SW1
R6A
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R6C
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R6F
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R6H
GPIO_0a
GPIO_1a
GPIO_2a
GPIO_3a
GPIO_4a
GPIO_5a
1
2
3
4
5
6 7
8
9
10
11
12
SW2
R7A
R7B
R7C
R7D
R7E
R7F
R7G
R7H
GPIO_0b
GPIO_1b
GPIO_2b
GPIO_3b
GPIO_4b
GPIO_5b
GPIO Switches
5-6K Interface Board Schematic
470 Ohms
470 Ohms

6 Related Documentation from Texas Instruments
7 5-6K Interface Board Assembly and Schematics
www.ti.com Related Documentation from Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas Instruments Literature ResponseCenter at [phone] or the Product Information Center (PIC) at [phone]. When ordering,please identify this booklet by its title and literature number. Updated documents can also be obtainedthrough our website at www.ti.com .
Data Sheets: Literature Number:TMS320 Cross-Platform Daughtercard Specification SPRA711SN74CBT3257, 4-Bit 1-Of-2 FET Multiplexer/Demultiplexer SCDS017SN74AHC1G04, Single Inverter Gate SCLS318SN74AHC1G32, Single 2-Input Positive-OR Gate SCLS317Designing Modular EVMs for Data Acquisition Products SLAA185
The board assembly and schematics are attached on the following pages.
SLAU104C – May 2004 – Revised March 2009 List of Tables 9Submit Documentation Feedback

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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, andcan radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of thisequipment in other environments may cause interference with radio communications, in which case the user at his own expensewill be required to take whatever measures may be required to correct this interference.
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of -15 V to +15 V and the output voltage range of -15 V to +15 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there arequestions concerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to theEVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the loadspecification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 23 °C. The EVM is designed tooperate properly with certain components above 40 °C as long as the input and output ranges are maintained. These componentsinclude but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types ofdevices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes nearthese devices during operation, please be aware that these devices may be very warm to the touch.
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