Connect Tech FreeForm/PCI-104 User manual

Connect Tech FreeForm/PCI-104 FreeForm/PCI-104
Document: CTIM-00040
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FreeForm/PCI-104
Connect Tech Inc. Tel: [phone]
42 Arrow Road Toll: 800-426-8979 (North America only)
Guelph, Ontario Fax: [phone]
N1K 1S6 Email: [e-mail]
www.connecttech.com [e-mail]
CTIM-00040 Revision 0.09 2018-07-16

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Table of Contents
Table of Contents ....................................................................................................................... 1
List of Tables.............................................................................................................................. 3
List of Figures ............................................................................................................................ 3
Preface........................................................................................................................................ 4
Disclaimer.......................................................................................................................... 4
Customer Support Overview.............................................................................................. 4
Contact Information........................................................................................................... 4
Limited Product Warranty ................................................................................................. 5
Copyright Notice................................................................................................................ 5
Trademark Acknowledgment............................................................................................. 5
ESD Warning..................................................................................................................... 6
Revision History......................................................................................................................... 6
Introduction ................................................................................................................................ 7
Product Features ................................................................................................................ 7
About this manual.............................................................................................................. 7
System Overview ....................................................................................................................... 8
Reference Design ......................................................................................................................10
Hardware Description................................................................................................................11
Jumpers and Switches.......................................................................................................11
Slot Selection (RSW1) .............................................................................................11
FPGA Configuration Settings (J1) ...........................................................................11
Connector Pinouts.............................................................................................................12
PCI-104 Header (P1)................................................................................................12
JTAG Programming Header (P2).............................................................................12
SPI Flash Programming Header (P3) .......................................................................12
High-speed Serial (P4) .............................................................................................13
RS-485 Headers (P5, P6)..........................................................................................14
GPIO Header (P7)....................................................................................................15
External Power Connector (P8)................................................................................16
Connector’s Mating Components and Cables ...................................................................17
Hardware Installation ................................................................................................................18
Heat Sink Installation........................................................................................................18
Stand-alone Operation ......................................................................................................18
Software Installation..................................................................................................................19
FPGA Development Environment....................................................................................19
PLX Software Development Kit (SDK) ...........................................................................19
Reference Design & Application Examples .....................................................................19
FPGA Configuration .................................................................................................................20
FPGA Ethernet MAC Addresses...............................................................................................20
Power and Thermal Considerations...........................................................................................21
Reference Design FPGA power analysis..........................................................................21
Specifications ............................................................................................................................22
Appendix A: ISE iMPACT Procedures.....................................................................................23
Preparing the iMPACT Project.........................................................................................23
Programming the FPGA ...................................................................................................26
Programming the Flash.....................................................................................................28
Generating a PROM (MCS) File ......................................................................................31
Appendix B: Power calculations ...............................................................................................34
Scenario 1: Heatsink attached, 250 LFM .................................................................34
Scenario 2: No Heatsink, 250 LFM..........................................................................35
Scenario 3: No heatsink, 0 LFM...............................................................................36
Appendix C: Hardware Changes from Revision B....................................................................37
Reference Design..............................................................................................................38

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Hardware Description.......................................................................................................39
Connector Pinouts ....................................................................................................39
Specifications....................................................................................................................40
Appendix D: Identifying Configuration Flash Size...................................................................41
List of Tables
Table 1: FreeForm/PCI-104 Components .................................................................................. 9
Table 2: Slot Selection (RSW1) ................................................................................................11
Table 3: FPGA Configuration Settings (J1) ..............................................................................11
Table 4: JTAG Programming Header Pinout (P2).....................................................................12
Table 5: SPI Flash Programming Header Pinout (P3)...............................................................12
Table 6: High-Speed serial Connector Pinout (P4) ...................................................................13
Table 7: RS-485 Port 1 Pinout (P5)...........................................................................................14
Table 8: RS-485 Port 2 Pinout (P6)...........................................................................................14
Table 9: GPIO Header Pinout....................................................................................................15
Table 10: External Power Connector Pinout (P8) .....................................................................16
Table 11: Connector Mate Listing.............................................................................................17
List of Figures
Figure 1: FreeForm/PCI-104 Block Diagram............................................................................. 8
Figure 2: FreeForm/PCI-104 Layout.......................................................................................... 9
Figure 3: External Power Connection........................................................................................16

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Preface
Disclaimer
The information contained within this user’s guide, including but not limited to any product specification,
is subject to change without notice.
Connect Tech assumes no liability for any damages incurred directly or indirectly from any technical or
typographical errors or omissions contained herein or for discrepancies between the product and the user’s
guide.
Customer Support Overview
If you experience difficulties after reading the manual and/or using the product, contact the Connect Tech
reseller from which you purchased the product. In most cases the reseller can help you with product
installation and difficulties.
In the event that the reseller is unable to resolve your problem, our highly qualified support staff can assist
you. Our support section is available 24 hours a day, 7 days a week on our website at:
http://connecttech.com/support/resource-center/. See the contact information section below for more
information on how to contact us directly. Our technical support is always free.
Contact Information
Mail/Courier
Connect Tech Inc.
Technical Support
42 Arrow Road
Guelph, Ontario
Canada N1K 1S6
Email/Internet
[email protected]m
[email protected]m
www.connecttech.com
Note:
Please go to the Connect Tech Resource Center for product manuals, installation guides, device
drivers, BSPs and technical tips. Submit your technical support questions to our support engineers.
Telephone/Facsimile
Technical Support representatives are ready to answer your call Monday through Friday, from 8:30
a.m. to 5:00 p.m. Eastern Standard Time. Our numbers for calls are:
Toll Free: 800-426-8979 (North America only)
Telephone: [phone] (Live assistance available 8:30 a.m. to 5:00 p.m. EST,
Monday to Friday)
Facsimile: 519-836-4878 (on-line 24 hours)

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Limited Product Warranty
Connect Tech Inc. provides a Limited Warranty for this product. Should this product, in
Connect Tech Inc.'s opinion, fail to be in good working order during the warranty period,
Connect Tech Inc. will, at its option, repair or replace this product at no charge, provided that
the product has not been subjected to abuse, misuse, accident, disaster or non-Connect Tech
Inc. authorized modification or repair.
You may obtain warranty service by delivering this product to an authorized Connect Tech
Inc. business partner or to Connect Tech Inc. along with proof of purchase. Product returned to
Connect Tech Inc. must be pre-authorized by Connect Tech Inc. with an RMA (Return
Material Authorization) number marked on the outside of the package and sent prepaid,
insured and packaged for safe shipment.
The Connect Tech Inc. Limited Warranty is only valid over the serviceable life of the product.
This is defined as the period during which all components are available. Should the product
prove to be irreparable, Connect Tech Inc. reserves the right to substitute an equivalent product
if available or to retract the Warranty if no replacement is available.
The above warranty is the only warranty authorized by Connect Tech Inc. Under no
circumstances will Connect Tech Inc. be liable in any way for any damages, including any lost
profits, lost savings or other incidental or consequential damages arising out of the use of, or
inability to use such product.
Copyright Notice
The information contained in this document is subject to change without notice. Connect Tech
Inc. shall not be liable for errors contained herein or for incidental consequential damages in
connection with the furnishing, performance, or use of this material. This document contains
proprietary information that is protected by copyright. All rights are reserved. No part of this
document may be photocopied, reproduced, or translated to another language without the prior
written consent of Connect Tech, Inc.
Copyright © 2016 by Connect Tech, Inc.
Trademark Acknowledgment
Connect Tech, Inc. acknowledges all trademarks, registered trademarks and/or copyrights
referred to in this document as the property of their respective owners.
Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of
acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this
document.

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ESD Warning
Electronic components and circuits are sensitive to
ElectroStatic Discharge (ESD). When handling any circuit
board assemblies including Connect Tech COM Express carrier
assemblies, it is recommended that ESD safety precautions be
observed. ESD safe best practices include, but are not limited
to:
Leaving circuit boards in their antistatic packaging
until they are ready to be installed.
Using a grounded wrist strap when handling circuit
boards, at a minimum you should touch a grounded
metal object to dissipate any static charge that may be
present on you.
Only handling circuit boards in ESD safe areas, which
may include ESD floor and table mats, wrist strap
stations and ESD safe lab coats.
Avoiding handling circuit boards in carpeted areas.
Try to handle the board by the edges, avoiding contact
with components.
Revision History
Revision
Date
Changes
0.09
2018-07-16
Updated format; Updated dev kit references

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Introduction
Connect Tech’s FreeForm/PCI-104 features Xilinx’s Virtex-5 multi-platform FPGA offering users a
flexible, reconfigurable computing platform that also takes advantage of the high bandwidth capabilities
of the PCI bus while communicating with various I/O interfaces.
Product Features
oPCI-104 form factor –32-Bit/33MHz, both 3.3V and 5V signaling are supported
oXilinx multi-platform Virtex-5 FPGA with 3 million logic gates
o2 or 4 MB Flash for FPGA configuration storage
o8MB Flash for embedded code storage
oDesigned for embedded processing using MicroBlaze™
o100MHz input clock
o128MB DDR2-400 memory
o2 x 10/100 Ethernet with modular jacks
o2 x RS-485 serial interface
oHigh-speed serial connector 4 x Rocket I/O (GTP) channels
o64 single ended or 32 LVDS general purpose I/O
oExternal 5V power connection for programming and development
oJTAG test and programming chain
oIndustrial temperature range of -40°C to 85°C
oShips preconfigured with a reference design
About this manual
This manual will provide the user with the following information:
oSystem overview
oIntroduction to the reference design
oDescription of jumpers, switches, and connector pinouts
oHardware installation instructions
oSoftware installation instructions
oFPGA configuration details
oSpecifications

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System Overview
The following conceptual block diagram provides a high level overview of the FreeForm/PCI-104 and
illustrates the general interconnection between components and connectors.
For the actual orientation and description of components refer to Figure 2 and Table 1 respectively.
FPGA
[Xilinx Virtex-5]
PCI-104 Bus
2x40
Header
JTAG Connector
1x7 Header
64 I/O, 32 LVDS Pairs
Ext Power Connector
Dual Ethernet PHY
RS-485 Transceiver
PCI Bus Interface
[PLX 9056]s
SPI Flash
(FPGA
Config.)
Local Bus
1x6
Header
RJ-45
2x5
Header
Peripheral Circuitry
Core Circuitry
RS-485 Transceiver
2x5
Header
RJ-45
Connector
DDR2 RAM
SPI Flash
(Embedded
Code)
EEPROM
(Parameters)
DDR2 RAM
100 Mhz
Osc.
High Speed Serial
EEPROM
(Config
Registers)
Figure 1: FreeForm/PCI-104 Block Diagram

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Figure 2: FreeForm/PCI-104 Layout
Table 1: FreeForm/PCI-104 Components
Connectors
Description
P1
PCI-104 connector
P2
JTAG programming header
P3
SPI flash programming header
P4
High-speed serial connector
P5, P6
RS-485 header
P7
GPIO header
P8
External power header
P9
RJ-45 A
P10
RJ-45 B
Jumpers /Switches
Description
RSW1
Slot selection
J1
FPGA configuration settings
Components
Description (not all on top side)
D1-D4
User LEDs
D5
FPGA load complete LED
U4
PLX PCI-local bus bridge
U5
Virtex-5 FPGA
U10
FPGA configuration flash
U11
Embedded code flash
U12, U13
DDR2 memory
U14
Parameter EEPROM
U15, U16
RS-485 transceiver

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U17
Dual 10/100 PHY
O1,O2, O3
Oscillators
Reference Design
The FreeForm/PCI-104 ships with a pre-installed reference design that is loaded into the FPGA’s
configuration flash. This reference design demonstrates how to interface the FreeForm/PCI-104
(Virtex-5 FPGA) with the PLX PCI 9056 PCI to Local Bus Bridge, as well as the various peripherals.
The PLX 9056 provides a generic local bus that is capable of operating at up to 66MHz (this design
forwards a 50MHz clock to the PLX). The PLX bridge has been set in the C-Mode of operation. The
reference logic operates as a local bus slave, as well as a local bus master.
The reference design contains examples demonstrating:
oLoading of PLX 9056’s registers via the local bus
oLocal bus slave transfers
oLocal bus master transfers
oGPIO control
oProgramming the SPI Flash
oInterfacing to the built-in Virtex-5 TEMACs
oRS-485 serial data transfers
oReading/writing to the serial EEPROM
oReading/writing to DDR2 memory
oInterfacing to the Virtex-5 Rocket I/O transceivers
Most of the example VHDL modules demonstrate how to interface with the various peripherals through
a register set, which is accessible by the host system over the PCI bus. A set of software applications
has been created to show how the host system can communicate with each FPGA sub-module. In most
applications, the host system will not directly control these peripherals. In a custom application, these
modules can be easily modified to interconnect with each other through the FPGA fabric.
To obtain the source code, refer to Software Installation. For further details on the reference design,
refer to FreeForm/PCI-104 Reference Design Guide (CTIM-00042)

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Hardware Description
The following sections describe the function of all switches/jumpers and provide details on connector
pinouts.
Jumpers and Switches
Slot Selection (RSW1)
This rotary switch selects a slot position in the PCI-104 stack. When mounting on a PCI adapter
card, ensure slot one is selected.
Table 2: Slot Selection (RSW1)
Position
Slot
0,4
0
1,5
1
2,6
2
3,7
3
FPGA Configuration Settings (J1)
Jumper J1 is used to control FPGA configuration.
Table 3: FPGA Configuration Settings (J1)
Location
Function
FPGA waits for configuration over JTAG (using P2)
FPGA reads configuration from SPI flash
FPGA is tri-stated, flash is isolated from FPGA and
can be programmed directly

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Connector Pinouts
PCI-104 Header (P1)
Refer to PCI-104 specifications.
Note: The FreeForm/PCI-104 only requires the 5V power supply,. The board is compatible with
PCI-104 mother boards that supply just 5V or both 3.3V & 5V.
JTAG Programming Header (P2)
Use P2 to configure the FPGA via JTAG. Refer to FPGA Configuration for more information.
Power pins are for voltage reference only; they do not provide power to the configuration
circuitry.
Note that the FPGA can always be programmed via JTAG, regardless of the J1 configuration
setting.
Table 4: JTAG Programming Header Pinout (P2)
Pin
Signal
Direction
P2 JTAG
Header
1
Top View
1
TRST
Input
2
TMS
Input
3
TDI
Input
4
TDO
Output
5
TCK
Input
6
GND
Reference
7
3.3V
Reference
SPI Flash Programming Header (P3)
P3 may be used to directly program the SPI flash, providing that J1 is set correctly to the tri-state
FPGA position. The power pins are for voltage reference only. They do not provide power to the
configuration circuitry.
Table 5: SPI Flash Programming Header Pinout (P3)
Pin
Signal
Direction
1
P3 SPI Flash
Header
Top View
1
SPI_CSN
Input
2
SPI_MOSI
Input
3
SPI_MISO
Output
4
SPI_CLK
Input
5
GND
Reference
6
3.3V
Reference

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High-speed Serial (P4)
The high-speed serial connector carries four Rocket (GTP) I/O channels, each with a dedicated
transmit and receive differential pair. These channels are capable of operating up 3.125 Gbps,
depending on configuration. For more information on Rocket I/O capabilities, visit the Xilinx
website: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/
Table 6: High-Speed serial Connector Pinout (P4)
Pin
Signal
Direction
Notes
1
MTGRXN0_112
Input
(b)
3
MTGRXP0_112
Input
(b)
2
MTGTXN0_112
Output
(b)
4
MTGTXP0_112
Output
(b)
5
HSS_USER_IO(0)
Input/Output
(a), (d)
7
HSS_USER_IO(1)
Input/Output
(a), (d)
6
HSS_USER_IO(2)
Input/Output
(a), (d)
8
HSS_USER_IO(3)
Input/Output
(a), (d)
9
MTGRXN1_112
Input
(b)
11
MTGRXP1_112
Input
(b)
10
MTGTXN1_112
Output
(b)
12
MTGTXP1_112
Output
(b)
13
3.3V
Power
(a)
15
3.3V
Power
(a)
14
3.3V
Power
(a)
16
3.3V
Power
(a)
17
MTGRXN0_114
Input
(c)
19
MTGRXP0_114
Input
(c)
18
MTGTXN0_114
Output
(c)
20
MTGTXP0_114
Output
(c)
21
3.3V
Power
(a)
23
3.3V
Power
(a)
22
3.3V
Power
(a)
24
3.3V
Power
(a)
25
MTGRXN1_114
Input
(c)
27
MTGRXP1_114
Input
(c)
26
MTGTXN1_114
Output
(c)
28
MTGTXP1_114
Output
(c)
29
GND
Power
(f)
30
GND
Power
(f)
31
GND
Power
(f)
32
GND
Power
(f)
Notes:
a) Pins have a different function from Revision B.
b) The Rocket I/O (GTP) are organized into tiles, where each tile has two transceivers and
shares a common PLL. In this design, tiles 112 and 114 are used.
c) Tile 112 has AC coupling capacitors on the TX pairs, validated at PCI Express data rates
(2.5 Gbps).
d) Tile 114 has AC coupling capacitors on both the RX and TX pairs, validated at SATA
data rates (1.5 Gbps).
e) HSS_USER_IO are flexible LVCMOS side-band signals.
f) Pins 29-32 are the ground blades running down the center of the high speed connector

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WARNING If connecting two FreeForm/PCI-104’s together using the Rocket I/O
interface in a cross-over fashion; care must be taken when building a
custom Samtec EQDP cable.
Special considerations are required when connecting a
FreeForm/PCI104 Rev B to later revisions. See Appendix C: Hardware
Changes from Revision B.
Top View
RS-485 Headers (P5, P6)
Table 7: RS-485 Port 1 Pinout (P5)
Pin
Signal
Direction
1
P5 10
485Port 0
Top View
1
RXD+1
Input
2
3
RXD-1
Input
4
5
TXD+1
Output
6
7
TXD-1
Output
8
9
GND
Power
10
Table 8: RS-485 Port 2 Pinout (P6)
Pin
Signal
Direction
10 P6
1
485Port 1
Top View
1
RXD+2
Input
2
3
RXD-2
Input
4
5
TXD+2
Output
6
7
TXD-2
Output
8
9
GND
Power
10
29

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GPIO Header (P7)
When in differential mode, the GPIO header positive (P) and negative (N) signals are adjacent on
a standard ribbon cable. Note that the GPIO voltage level is set via hardware.
oFCG001: L12 populated, enabling 2.5V I/O, including LVDS
oFCG002: L13 populated, enabling 3.3V I/O
Table 9: GPIO Header Pinout
Pin
Signal
Direction
Pin
Signal
Direction
1
GPION(0)
Input/Output
41
GPION(16)
Input/Output
2
GPIOP(0)
Input/Output
42
GPIOP(16)
Input/Output
3
GPION(1)
Input/Output
43
GPION(17)
Input/Output
4
GPIOP(1)
Input/Output
44
GPIOP(17)
Input/Output
5
GPION(2)
Input/Output
45
GPION(18)
Input/Output
6
GPIOP(2)
Input/Output
46
GPIOP(18)
Input/Output
7
GPION(3)
Input/Output
47
GPION(19)
Input/Output
8
GPIOP(3)
Input/Output
48
GPIOP(19)
Input/Output
9
GND
Power
49
GND
Power
10
GND
Power
50
GND
Power
11
GPION(4)
Input/Output
51
GPION(20)
Input/Output
12
GPIOP(4)
Input/Output
52
GPIOP(20)
Input/Output
13
GPION(5)
Input/Output
53
GPION(21)
Input/Output
14
GPIOP(5)
Input/Output
54
GPIOP(21)
Input/Output
15
GPION(6)
Input/Output
55
GPION(22)
Input/Output
16
GPIOP(6)
Input/Output
56
GPIOP(22)
Input/Output
17
GPION(7)
Input/Output
57
GPION(23)
Input/Output
18
GPIOP(7)
Input/Output
58
GPIOP(23)
Input/Output
19
GND
Power
59
GND
Power
20
GND
Power
60
GND
Power
21
GPION(8)
Input/Output
61
GPION(24)
Input/Output
22
GPIOP(8)
Input/Output
62
GPIOP(24)
Input/Output
23
GPION(9)
Input/Output
63
GPION(25)
Input/Output
24
GPIOP(9)
Input/Output
64
GPIOP(25)
Input/Output
25
GPION(10)
Input/Output
65
GPION(26)
Input/Output
26
GPIOP(10)
Input/Output
66
GPIOP(26)
Input/Output
27
GPION(11)
Input/Output
67
GPION(27)
Input/Output
28
GPIOP(11)
Input/Output
68
GPIOP(27)
Input/Output
29
GND
Power
69
GND
Power
30
GND
Power
70
GND
Power
31
GPION(12)
Input/Output
71
GPION(28)
Input/Output
32
GPIOP(12)
Input/Output
72
GPIOP(28)
Input/Output
33
GPION(13)
Input/Output
73
GPION(29)
Input/Output
34
GPIOP(13)
Input/Output
74
GPIOP(29)
Input/Output
35
GPION(14)
Input/Output
75
GPION(30)
Input/Output
36
GPIOP(14)
Input/Output
76
GPIOP(30)
Input/Output
37
GPION(15)
Input/Output
77
GPION(31)
Input/Output
38
GPIOP(15)
Input/Output
78
GPIOP(31)
Input/Output
39
GND
Power
79
GND
Power
40
GND
Power
80
GND
Power

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Side View
External Power Connector (P8)
The external connector provides 5V to the power regulation circuitry.
The external power connector should only be used when the FreeForm/PCI-104 is being
programmed outside of a PCI/PCI-104 system.
Table 10: External Power Connector Pinout (P8)
Pin
Signal
Direction
1 2
3 4
P8
Standalone
Power Input
1
5V
Power
2
3
GND
Power
4
VIO (connect to 5V)
Power
It is recommended that a Connect Tech Inc. FreeForm/PCI-104 power supply is used for providing
external power. Orientation of the power supply connector is important. Ensure that the clip on
the cable aligns with the catch on P8, as shown below.
Figure 3: External Power Connection

Connect Tech FreeForm/PCI-104 FreeForm/PCI-104
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Date: 2018-07-16
Connector’s Mating Components and Cables
The following table lists the manufacturer and part number for connectors on the FreeForm/PCI-104, as
well as potential mating components.
Table 11: Connector Mate Listing
Connector
Component on
FreeForm/PCI-104
Mating components
Mating cable assembly
P2
Samtec
TSW-107-07-L-S
(0.100” pitch, 1x7)
Samtec
SSW-107-xx-G-S
(Socket, other options available)
Connect Tech Inc.
CBG303
(JTAG programming cable)
P3
Samtec
TSW-106-07-L-S
(0.100” pitch, 1x6)
Samtec
SSW-106-xx-G-S
(Socket, other options available)
Connect Tech Inc.
CBG303
(JTAG programming cable)
P4
Samtec
QSE-014-01-L-D-DP-A
(0.8mm pitch, 2x14,
arranged as 14 differentials
pairs)
Samtec
QTE-014-01-L-D-DP-A
(5mm mated height, other
heights available)
Samtec EQDP [Note 2]
P5/P6
Samtec
TSW-105-07-L-D
(0.100” pitch, 2x5)
Samtec
SSW-105-xx-G-D
(Socket, other options available)
Connect Tech Inc.
CAG104
(Header to DB9)
P7
Tyco
5-104069-3
(0.050”x0.100” pitch, 2x40)
Tyco
3-111196-3
(ribbon cable mate)
or
Tyco
8-487937-0
(discrete wire housing)
Tyco
1-487547-1
(crimps for housing)
-
P8
Samtec
IPL1-102-01-S-D
(0.100” pitch, 2x2)
Samtec
IPD1-02-D
(discrete wire housing)
Samtec
CC79L-2024-01-S
(crimps for housing)
or
Samtec
MMSD-02-22-S-03-25-S
(pre-assembled housing and
wiring)
Connect Tech Inc.
MSG037
(5V power supply, for
development purposes)
Note:
[1] CBG303 and MSG037 are available as part of development kit DEV017
[2] Connect Tech does not carry stock of the Samtec EQDP cable. The EQDP has many options,
allowing for a configuration to meet the specific application. Care must be taken when selecting these
options, to ensure the correct connectivity between boards.

FreeForm/PCI-104
Users Guide
www.connecttech.com
Document: CTIM-00040
Revision: 0.09
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Connect Tech Inc. 800-426-8979 | 519-836-1291
Date: 2018-07-16
Hardware Installation
Before installing the FreeForm/PCI-104 into a PCI-104 stack, ensure the following:
oSlot selection is properly set using the rotary switch RSW1.
oFPGA configuration jumper J1 is set to read from flash.
Once installed in the system and power is applied, the LED D1 will illuminate to indicate that
FreeForm/PCI-104 is functioning.
Heat Sink Installation
Each FreeForm/PCI-104 ships with a FPGA heat sink (27 mm x 27 mm); to be installed by the user.
Simply peel of the sticker backing and press firmly onto the FPGA, using proper ESD precautions.
If the heat sink size is not suitable for your application, please contact Connect Tech Inc.
WARNING In many applications, including high speed memory operations, the
FPGA dissipates a significant amount of power. Failure to use any heat
sinking will result in the product warranty being voided.
Stand-alone Operation
Operating the FreeForm/PCI-104 outside of a PCI-104 stack or a PCI system for extended periods of
time is not recommended. The PCI to local bus bridge (PCI PLX 9056) requires the pull-up/pull-down
resistors provided on a system’s main board.
Configuring or programming the FreeForm/PCI-104 in stand-alone mode is acceptable, providing that it
is not left powered on in stand-alone state for an extended period of time.
WARNING The power supply MSG037 included with the development kit
DEV017 is intended for desktop programming only. It is not intended
or warranted to be used in any other situation.

Connect Tech FreeForm/PCI-104 FreeForm/PCI-104
Document: CTIM-00040
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Date: 2018-07-16
Software Installation
FPGA Development Environment
FreeForm/PCI-104 has been developed with Xilinx WebPACK 9.2, available free of charge at:
http://www.xilinx.com/ise/logic_design_prod/webpack.htm
PLX Software Development Kit (SDK)
PLX provides a software development kit (SDK) to aid in the creation of applications using the PLX
9056 bridge. The SDK provides a generic driver for Windows 2000/XP and Linux. A common API is
also included; which encapsulates functions like:
oConfiguration register read / write
oBlock read / block write to local address space (i.e. memory / registers in the FPGA)
oPhysical memory allocation, for bus mastering or DMA purposes
oInterrupt handling
oEEPROM read/write by address
The SDK is available for download from:
http://www.plxtech.com/products/sdk/
In order to download the SDK, you will need to register with PLX.
Reference Design & Application Examples
The FreeForm/PCI-104 ships with a CD containing:
oDocumentation and manuals
oFPGA VHDL reference design
oSoftware program examples
The reference design and example programs help users quickly develop custom hardware and software
applications. Refer to the CD for installation instructions.
The latest reference design is always available from:
http://devel.connecttech.com/
If a username and password have not already been provided, please contact Connect Tech Support via
email [e-mail].

Connect Tech FreeForm/PCI-104 FreeForm/PCI-104
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Revision: 0.09
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Date: 2018-07-16
FPGA Configuration
The Virtex-5 FPGA can be configured via two methods:
oJTAG programming chain, using P2
oSPI Flash, read on, power-up by FPGA
The configuration flash can be programmed (loaded) through three methods:
oJTAG programming chain (through FPGA), using P2
oDirect with cable, using P3 [No longer supported after in ISE 12.x and later]
oIndirect programming through FPGA, only possible after configuration is complete (refer
to reference design for more details)
To configure the FPGA via the JTAG / boundary scan programming chain, three items are required:
oFPGA bitstream (*.bit), generated at end FPGA implementation using ISE
oPLX 9056 boundary scan definition file (*.bdsl)
oEthernet PHY boundary scan definition file
To program the SPI flash, a hex file must be generated (*.mcs) then written to the flash. To generate
the hex file, the following is required:
oFPGA Bitstream
oSetting PROM file format to MCS (important since bits are swapped)
oSetting SPI PROM density to 16M
oSetting SPI Flash type to M25P16
For a complete procedure, refer to Appendix A.
FPGA Ethernet MAC Addresses
The FreeForm/PCI-104’s FPGA contains 2 dual Tri-Mode Ethernet MACs. One dual MAC is
connected to the on-board Ethernet PHY, and the other is free for general use. In either case, the
Ethernet MAC address is set by the user application, either HDL or embedded software –it is not
hard coded as part of the FPGA silicon.
As such, the user is required to provide a valid Ethernet MAC address. If the end product usage is
in the public domain, then this Ethernet MAC address must have a registered IEEE OUI
designator.
If your organization or parent company does not have a registered IEEE OUI listing, please
contact Connect Tech Inc. to obtain a valid Ethernet MAC address for your product.