CyberResearch CYDIO 96P User manual

USER’S MANUAL
VER. 2 • NOV 2000
&
No part of this manual may be reproduced without permission.
CyberResearch®, Inc.
www.cyberresearch.com
25 Business Park Dr., Branford, CT 06405 USA
203-483-8815 (9am to 5pm EST) FAX: [phone]
Digital I/O
CYDIO 96P
Multi-Channel Digital I/O Board
96-Channel, TTL-Level PCI Board
with 100-Pin Connection
®

© Copyright 2003
All Rights Reserved.
November 2000
The information in this document is subject to change without prior notice in order
to improve reliability, design, and function and does not represent a commitment
on the part of CyberResearch, Inc.
In no event will CyberResearch, Inc. be liable for direct, indirect, special,
incidental, or consequential damages arising out of the use of or inability to use
the product or documentation, even if advised of the possibility of such damages.
This document contains proprietary information protected by copyright. All rights
are reserved. No part of this manual may be reproduced by any mechanical,
electronic, or other means in any form without prior written permission of
CyberResearch, Inc.
TRADEMARKS
“CyberResearch,” and “CYDIO 96P,” are trademarks of CyberResearch, Inc. Other
product names mentioned herein are used for identification purposes only and
may be trademarks and/or registered trademarks of their respective companies.
• NOTICE •
CyberResearch, Inc. does not authorize any CyberResearch product for use in life
support systems, medical equipment, and/or medical devices without the written
approval of the President of CyberResearch, Inc. Life support devices and
systems are devices or systems which are intended for surgical implantation into
the body, or to support or sustain life and whose failure to perform can be
reasonably expected to result in injury. Other medical equipment includes devices
used for monitoring, data acquisition, modification, or notification purposes in
relation to life support, life sustaining, or vital statistic recording. CyberResearch
products are not designed with the components required, are not subject to
the testing required, and are not submitted to the certification required to ensure
a level of reliability appropriate for the treatment and diagnosis of humans.

TABLE OF CONTENTS
23
7.3 VOLTAGE DIVIDERS.....................................22
7.2 TTL TO SOLID STATE RELAYS..........................21
7.1 PULL UP & PULL DOWN RESISTORS...................21
7 ELECTRONICS AND INTERFACING.......................19
6 SPECIFICATIONS............................................18
5.4.7 Counter Interrupt Source Configure....................17
5.4.6 8255 Interrupt Source Configure.......................16
5.4.5 8254 Configuration & Data............................15
5.4.4 Group 3 8255 Configuration & Data...................15
5.4.3 Group 2 8255 Configuration & Data...................14
5.4.2 Group 1 8255 Configuration & Data...................12
5.4.1 Group 0 8255 Configuration & Data...................12
5.4 BADR3....................................................11
5.3 BADR2.................................................... 10
5.2.1 INTCSR Configure.................................... 10
5.2 BADR1.................................................... 10
5.1 BADR0....................................................10
5 REGISTER MAPS............................................. 9
4.2 PACKAGED APPLICATION PROGRAMS.................9
4.1 UNIVERSAL LIBRARY....................................9
4 SOFTWARE....................................................8
3.4 CYERB 24 & CYSSR 24 CONNECTIONS.............. 5
3.3 SIGNAL CONNECTION CONSIDERATIONS ..............4
3.2 CONNECTOR DIAGRAM ..................................3
3.1 CABLES AND SCREW TERMINAL BOARDS.............3
3 I/O CONNECTIONS ...........................................2
2 INSTALLATION ...............................................1
1 INTRODUCTION ..............................................

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1INTRODUCTION
The CyDIO 96P isa 96-bit linedigitalI/O board. The board providesthe96 bitsin
four 24-bit groups. Eachgroupprovidesan8-bit portAand portB, aswell asan
8-bit port C that can besplit intoindependent 4-bit portC-HIanda 4-bit portC-LO.
See Figure 1-1 below.
On power upandreset, all I/O bits are set toinput mode.Ifyou are using the board
tocontrolitemsthat must beOFF onreset, youwill needtoinstall pull-down
resistors. Provisions have been madeonthe boardtoallowusers toquicklyand
easily install SIP resistor networks in either pull-up or pull-down configurations.
Figure 1-1. CyDIO 96P Block Diagram
CyDIO 96P
Block Diagram
PCI BUS (5V, 32-BIT, 33MHZ)
PCI
CONTROLLER BADR3
Boot
EEPROM
Control
Registers
Decode/Status
CONTROLLER FPGA and LOGIC
LOCAL BUS
CONTROL
BUS
Port A
Port B
Control
(7:0)
(7:0)
DIO Group 0
Port C
(7:0)
Port A
Port B
Control
(7:0)
(7:0)
DIO Group 1
Port C
(7:0)
Port A
Port B
Control
(7:0)
(7:0)
DIO Group 2
Port C
(7:0)
Port A
Port B
Control
(7:0)
(7:0)
DIO Group 3
Port C
(7:0)
PLX-9052
COUNTERS
82C54
INT.
82C55
82C55
82C55
82C55
1

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2INSTALLATION
The CyDIO 96P boards are completelyplug-and-play. There are noswitches or
jumpersontheboard. All board addressesare setbyyour computer’splug-and-play
software.
InstaCal is the installation, calibration andtest software suppliedwith your data
acquisition / IO hardware. Refer tothe Extended SoftwareInstallation Manualto
install InstaCal.
If you need it, there is some on-line help in the InstaCal program.
Owners oftheUniversal Libraryshould read themanual andexamine theexample
programs prior to attempting any programming tasks.
2

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3.1CABLES AND SCREW TERMINAL BOARDS
The board hasa 100-pin,high-densityRobinson-Nugentmaleconnector (Figure 3-1).
ACBL 100xx cable isused to split the100 I/O linesinto two, 50-wire cables. One
connector haspins1 to50, theother has51 to100. The twoI/O connectorscanbe
connected directlyto two screw-terminal boards suchas the CYSTP 50E,
STA 100, STA 50H or CYSTP 502E. See Figures3-2 and3-3 for
configuration and pin out.
3 I/O Connections
3

3.2CONNECTOR DIAGRAM
The CyDIO 96P I/O connector isa 100-pintype connector accessible fromthe rear of
the PC at the expansion backplate See Figure 3-1 below for the board pin out.
Figure 3-1. CyDIO 96P 100-Pin Connector Pin Out
4
Port A7 B 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
+5V 49
GND 50
Port A6 B
Port A5 B
Port A4 B
Port A3 B
Port A2 B
Port A1 B
Port A0 B
Port B7 B
Port B6 B
Port B5 B
Port B4 B
Port B3 B
Port B2 B
Port B1 B
Port B0 B
Port C7 B
Port C6 B
Port C5 B
Port C4 B
Port C3 B
Port C2 B
Port C1 B
Port C0 B
Port A7 A
Port A6 A
Port A5 A
Port A4 A
Port A3 A
Port A2 A
Port A1 A
Port A0 A
Port B7 A
Port B6 A
Port B5 A
Port B4 A
Port B3 A
Port B2 A
Port B1 A
Port B0 A
Port C7 A
Port C6 A
Port C5 A
Port C4 A
Port C3 A
Port C2 A
Port C1 A
Port C0 A
51 Port A7 D
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99 +5V
100 GND
Port A6 D
Port A5 D
Port A4 D
Port A3 D
Port A2 D
Port A1 D
Port A0 D
Port B7 D
Port B6 D
Port B5 D
Port B4 D
Port B3 D
Port B2 D
Port B1 D
Port B0 D
Port C7 D
Port C6 D
Port C5 D
Port C4 D
Port C3 D
Port C2 D
Port C1 D
Port C0 D
Port A7 C
Port A6 C
Port A5 C
Port A4 C
Port A3 C
Port A2 C
Port A1 C
Port A0 C
Port B7 C
Port B6 C
Port B5 C
Port B4 C
Port B3 C
Port B2 C
Port B1 C
Port B0 C
Port C7 C
Port C6 C
Port C5 C
Port C4 C
Port C3 C
Port C2 C
Port C1 C
Port C0 C
DIO
Group 1
DIO
Group 2
DIO
Group 0
DIO
Group 3

Figure 3-2. Cable CBL 100xx Configuration
5
SIGNAL CONDITIONINGOR
50-PINSCREWTERMINALBOARD
SIGNAL
CONDITIONINGor
50-PINSCREW
TERMINALBOARD.
CBL 100xx
CABLE
BOARD’S
100-PIN I/O
CONNECTOR
I/O PINS 1 TO 50
I/O PINS 51 TO 100

Figure 3-3. Pin Translation - Pins 51 to 100 DI/O Signals
6
1PortA7D
PortA6D2
3PortA5D
PortA4D4
5PortA3D
PortA2D6
7PortA1D
PortA0D8
9PortB7D
PortB6D10
11PortB5D
PortB4D12 13PortB3D
PortB2D14
15PortB1D
PortB0D16
17PortC7D
PortC6D18
19PortC5D
PortC4D20
21PortC3D
PortC2D22
23PortC1D
PortC0D24
25PortA7C
PortA6C26
PortA4C28
PortA2C30
45PortC3CPortC2C46
27PortA5C
29PortA3C
31PortA1C
PortA0C32
PortB6C34
PortB4C36
33PortB7C
35PortB5C
37PortB3C
PortB2C38
39PortB1C
40PortB0C
41PortC7C
PortC6C42
43PortC5C
PortC4C44
47PortC1C
PortC0C48
49+5V
Ground50
2ndof2
CBL 100xx
50-Pin Connectors
From board pins 51 to 100
(1st connector is pin 1 to 1, etc.,
DIO Groups 0 and 1)
Pins 51- 100 of 100-Pin Conn.
51 Port A7 D
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99 +5V
100 GND
Port A6 D
Port A5 D
Port A4 D
Port A3 D
Port A2 D
Port A1 D
Port A0 D
Port B7 D
Port B6 D
Port B5 D
Port B4 D
Port B3 D
Port B2 D
Port B1 D
Port B0 D
Port C7 D
Port C6 D
Port C5 D
Port C4 D
Port C3 D
Port C2 D
Port C1 D
Port C0 D
Port A7 C
Port A6 C
Port A5 C
Port A4 C
Port A3 C
Port A2 C
Port A1 C
Port A0 C
Port B7 C
Port B6 C
Port B5 C
Port B4 C
Port B3 C
Port B2 C
Port B1 C
Port B0 C
Port C7 C
Port C6 C
Port C5 C
Port C4 C
Port C3 C
Port C2 C
Port C1 C
Port C0 C
DIO
Group 3
DIO
Group 3
DIO
Group 2
DIO
Group 2

3.3SIGNAL CONNECTION CONSIDERATIONS
All the digitalinputsonthe CyDIO 96P are 8255 CMOSTTL.The CyDIO 96P
output signals are 8255 CMOS.
CyberResearch, Inc. offers a widevarietyofdigital signalconditioning
products that provide anideal interface betweenhigh voltage and/or high current
signals andtheCyDIO 96P.Ifyou needcontrolormonitornon-TTLlevel signals
withyourboard, pleaserefer toour catalogor our websiteforthe following
products:
CYERB series, electromechanical relay output boards
CYERB "S" series, 10A electromechanical relay output boards
CYSSR series solid state relay I/O module racks
A description of digital interfacing is in the Interface Electronics section.
IMPORTANT NOTE
The 82C55 digital I/O chipinitializes all ports as inputs onpower-
upandreset. ATTLinput is a high impedance input. Ifyou
connectanotherTTLinputdevice tothe 82C55 it couldbe turned
ON or OFF every time the 82C55 is reset.
Remember, the 82C55 is reset to the INPUT mode.
There are positions forpull-upandpull-down resistorpacks onyour CyDIO 96P
board. To implement these, please refer to section 7.1.
7

3.4CYERB 24 & CYSSR 24 CONNECTIONS
CyDIO 96P boards provide digital I/O intwo majorgroups of48 bits each(96 total,
but eachside ofthe CBL 100xx cable provides48 bits). However, manypopular
relayandSSRboardsprovide only24-bitsofI/O. TheCYERB 24 and
CYSSR 24 eachimplements a connector scheme where all 96 bits ofthe
CyDIO 96P boardmaybeusedtocontrol relaysand/orSSRs. This configuration is
showninFigure 3-4below.The24-bitsofdigitalI/OonCyDIO 96P connector pins
1-24 (baseaddress +0through +3)controlthefirst relayboard.The24-bits onpins
25-50 will controlthe secondrelay/SSR boardonthe daisychain andsoonupto
100 pins.
Figure 3-4. Relay Rack Cabling
8
CYERB 24
or
CYSSR 24
CYERB 24
or
CYSSR 24
CBL 100xx
CYERB 24
or
CYSSR 24
CYERB 24
or
CYSSR 24
IN
IN IN
IN
OUT
OUT OUT
OUT
CyDIO
96P

4SOFTWARE
We highlyrecommendthat users take advantage ofourUniversal Librarypackage's
easy-to-use programming interfaces. However, ifyouare anexperienced
programmer, and wishtoread and writedirectlytothe board, wehaveprovided a
detailed register map in the next chapter.
4.1UNIVERSAL LIBRARY
The Universal Libraryprovides complete access to the CyDIO 96P functionsfroma
rangeofprogramming languages.Ifyou areplanning towriteprograms,orwould
liketorun theexampleprogramsforVisualBasicoranyotherlanguage,pleaseturn
now to the Universal Library manual.
4.2PACKAGED APPLICATION PROGRAMS
Most packaged applicationprograms, suchas SoftWIRE, DASWizard and HP-VEE
have drivers for theCyDIO 96P. Ifthe package youowndoes not appear to have
drivers for the boards, please faxor e-mail the package name and the revision
number fromthe install disks. Wewill research the package foryou andadvise how
to utilize the CyDIO 96P boards with the driver available.
Some application drivers are included with the Universal Library package, but not
with the application package. If you have purchased an application package directly
from the software vendor, you may need to purchase our Universal Library and
drivers. Please contact us for more information on this topic.
9

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5 REGISTER MAPS
The PCI Controller, a PLX-9052, has four configuration, control, and status registers
(Table 5-1). They are described in the following section.
Table 5-1. I/O Region Register Operations
8-bit byteDigital I/O registersBADR3 N/AN/ABADR2 32-bit double wordPCI I/O-mapped config. registersBADR1
32-bit double wordPCI memory-mapped configuration
registers
BADR0 OperationsFunctionI/O Region
5.1 BADR0
BADR0 is reserved for the PLX-9052 configuration registers. There is no reason to
access this region of I/O space.
5.2 BADR1
BADR1 is a 32 bit register for control and configuration of interrupts.
5.2.1 INTCSR Configure
BADR1 +4C hex
LEVEL/EDGEXINTCLRXISAMDXXX 89101112131432:15
READ/WRITE
INTEINTPOLINTXXXPCINTX01234567
Note: For applications requiring edge triggered interrupts (LEVEL/EDGE bit 8 = 1),
the user must configure the INTPOL bit for active high polarity (bit 1=1).
The INTCSR (Interrupt Control/Status Register) controls the interrupt features of the
PLX-9052 controller. As with all of the PLX-9052 registers, it is 32-bits in length.
Since the rest of the register have specific control functions, those bits must be
masked off in order to access the specific interrupt control functions listed below.
10

INTE Interrupt enable (local):
0 = disabled, 1 = enabled (default)
INTPOL Interrupt polarity:
0 = active low (default), 1 = active high
INT Interrupt status:
0 = interrupt not active, 1 = interrupt active
PCINT PCI interrupt enable:
0 = disabled (default), 1 = enabled
LEVEL/EDGE Interrupt trigger control:
0 = level triggered mode (default), 1 = edge triggered mode
INTCLR Interrupt clear (edge triggered mode only):
0 = N/A, 1 = clear interrupt
ISAMD ISA mode enable control (must be set to 1)
0 = ISA mode disabled, 1 = ISA mode enabled (default)
5.3 BADR2
BADR2 is not used.
11