FAST ComTec 2128N User manual

2128N
Constant Fraction Discriminator
User Manual
© Copyright FAST ComTec GmbH
Grünwalder Weg 28a, -82041 Oberhaching
Germany
Version 1.2, May 11, 2021

Version 1.0, May 11, 2021
2F ComTec GmbH

Grünwalder Weg 28A . 82041 Oberhaching . Germany
phone: [phone] . fax: [phone] . www.fastcomtec.com
Model 2128N
Constant Fraction Discriminator
2128N 11052021
FEATURES
100 Mh Count Rate
1000 : 1 Dynamic range
Three Operating Modes: CFT, CFRR
constant fraction discriminator with
slow risetime reject, and LET leading
edge trigger
Walk < 30 ps typically for 100 : 1 Range
Simultaneous Dual Positive and
Negative Outputs
Multicolor Count Rate Indicator
DC coupling
DESCRIPTION
The Model 2128N replaces the Model 2128. It is a
fully dc-coupled constant fraction discriminator
with a dynamic range of up to 1000:1. Selectable
fraction and three operating modes provide
optimum time resolution for many detector types
and applications. For example:
CFT – Constant fraction mode for fast detectors
CFRR – Slow rise time reject mode for Ge
detectors
LET – Leading edge mode for single photon
counting
The unit accepts negative polarity pulses to the
50Ω terminated dc-coupled inputs. On customer
request the module can be modified to accept
positive input signals. The constant fraction
composite signal is formed by the sum of a direct,
attenuated (fraction f=0.4 standard signal path
and a delayed, unattenuated path. The delay time
is selectable according to the propagation delay of
a (external 50Ω BNC cable. Careful selection of
fraction and delay cable provides full
compensation of timing distortions due to both
amplitude and risetime variations in the input
signal. Output signals are generated whenever the
input signal exceeds the selected threshold set by
a front panel potentiometer.
Four simultaneous, independent output signals
are provided. The two positive outputs are
adjustable in width, the width then determines the
internal deadtime required to suppress spurious
outputs due to input signal anomalies. The two
negative outputs are fixed-width pulses keyed to
the start of the dead time period.
The front panel ADJUST control and INSPECT
output permit the user to trim the walk
characteristics of the experimental setup for
optimum timing resolution. A frontpanel LED
indicates count rate by color change.
The wide dynamic range of the pent CFT permits

Grünwalder Weg 28A . 82041 Oberhaching . Germany
phone: [phone] . fax: [phone] . www.fastcomtec.com
2128N 11052021
SPECIFICATIONS
Inputs
Input: - accepts -5 mV to about -3.0 V linear
pulses: width > 1ns, Zin = 50 Ohms, dc
coupled; front panel BNC connector.
Delay: two front panel BNC connectors
accept 50 Ohm delay cable in order to form
the internal constant fraction signal.
Outputs
Inspect displays signal of zero crossing
discriminator for use in trimming time walk.
Neg output two independent negative
current outputs, each providing -32 mA into
50Ω, risetime < 3 ns, pulsewidth 5 ns nominal,
dc coupled.
Pos output two independent positive voltage
outputs, providing 2 V (minimum into 50Ω,
risetime < 10 ns, width adjustable by front
panel width trimming potentiometer, which
also determines the internal dead time.
Controls
Threshold Front panel 10-turn locking dial
potentiometer to set acceptance threshold for
input pulses (range ≈ -5 mV to -1 V .
Adjust front panel trimming potentiometer
(screwdriver to compensate walk of the
internal zero crossing discriminator
Leading edge width of the leading edge
signal is internally set by the trimming
potentiometer on the printed board to 20 ns.
CFRR-CFT-LET Frontpanel three-position
switch to select constant fraction with slow rise
time reject (CFRR , basic constant fraction
(CFT , or leading edge timing (LET modes of
operation.
OUTPUT WIDTH Front panel 22-turn
screwdriver adjustable potentiometer to set
width of slow positive output pulse, which is
equal to the internal dead time of the
discriminator – max setting: 1.5 micro sec.
PERFORMANCE
Dynamic range 1000 : 1
CF mode Walk < ±50ps (typically +30ps
for -30mV to -3V range with <2ns rise time.
Count rate up to 100 MHz, limited by dead
time (OUTPUT WIDTH setting
Pulse pair resolution <10 ns, or as limited
by dead time.
Threshold stability better than ±0.02% / 0C
(± 200 ppm / 0C
Threshold linearity ± 0.25 % integral
Temperature range 0 0C to + 50 0C
Delay cable typical lengths (RG-58)
for Plastic, NaI and Si (S.B. detectors 0.5m
to 1m,
for Planar Germanium detectors 1m to 2m
for Coaxial Ge 2.0 to 4m
Typical Power requirements
Standard version
+6.0V 150mA
-6.0V 450 mA
Physical
Si e single width 1/12 NIM module
(3.43 x 22.13 cm; 1.35 x 8.71 inches as per
TID – 20893 (rev.
Net weight 0.7 kg (2.0 lbs
Options
- can be modified to accept positive pulses
- 12V Version available on request
- on request 220 V (ac / 110V (ac
independent from a NIM bin
- Output width for negative output can be
modified
- threshold setting supplied externally via rear
panel connector
- signal shaping using small fractions and RC
shaping by modifying f and capacitors.

Copyright In ormation
Copyright 2021 FAST ComTec GmbH,
D-82041 Oberhaching, Germany. All rights reserved.
This manual contains proprietary information; no part of it may be reproduced by any means without prior
written permission of FAST ComTec, Grünwalder Weg 28a, -82041 Oberhaching, Germany.
Tel: [phone], FAX: [phone]
mail: [email protected]
The information in this manual describes the hardware and the software as accurately as possible, but is
subject to change without notice.
F ComTec GmbH 3

Table o Contents
1 Introduction.................................................................................................................................................... 6
1.1 General description................................................................................................................................ 6
1.2 Setup information................................................................................................................................... 6
1.2.1 Selection of modes........................................................................................................................ 6
1.2.2 Fraction.......................................................................................................................................... 6
2 Specifications................................................................................................................................................. 7
2.1 Inputs..................................................................................................................................................... 7
2.2 Outputs.................................................................................................................................................. 7
2.3 Controls................................................................................................................................................. 7
2.4 Indicators............................................................................................................................................... 7
2.5 Performance.......................................................................................................................................... 8
2.6 elay cable............................................................................................................................................ 8
2.7 Power requirements............................................................................................................................... 8
2.8 Physical................................................................................................................................................. 8
3 Controls, connectors and indicators............................................................................................................... 9
3.1 Front panel............................................................................................................................................. 9
4 Operation..................................................................................................................................................... 10
4.1 General................................................................................................................................................ 10
4.2 Laboratory bench tests........................................................................................................................ 10
4.2.1 Input............................................................................................................................................. 10
4.2.2 Operating mode........................................................................................................................... 10
4.2.3 elay cable.................................................................................................................................. 11
4.2.4 Walk trim...................................................................................................................................... 11
4.2.5 Outputs........................................................................................................................................ 11
5 Circuit description........................................................................................................................................ 12
5.1 General................................................................................................................................................ 12
5.2 LET mode ........................................................................................................................................... 12
5.3 CFT and CFRR mode.......................................................................................................................... 12
6 Special features and options........................................................................................................................ 13
6.1 Power supply....................................................................................................................................... 13
6.2 Input polarity........................................................................................................................................ 13
6.3 Output width......................................................................................................................................... 13
6.4 Threshold............................................................................................................................................. 13
6.5 Signal shaping..................................................................................................................................... 13
7 iagrams..................................................................................................................................................... 14
7.1 Circuit diagram..................................................................................................................................... 14
7.2 Board................................................................................................................................................... 15
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Table o Figures
Fig. 3.1: The Front Panel.................................................................................................................................. 9
Fig. 7.1: The Circuit diagram........................................................................................................................... 14
Fig. 7.2: The Board......................................................................................................................................... 15
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Introduction
1 Introduction
1.1 General description
The model 2128N is a fully dc-coupled constant fraction discriminator with a dynamic range of up to 1000:1.
Selectable fraction and three operating modes provide optimum time resolution for many detector types and
applications, for example
CFT constant fraction mode for fast detectors
CFRR slow rise time reject mode (e.g. germanium detectors)
LET leading edge mode for single photon counting
(more features are given in section 6)
The model 2128N accepts negative polarity pulses to its 50Ω terminated dc-coupled input. For positive
polarity input pulses see section 6.
The constant fraction composite signal is formed by the sum of a direct, attenuated (fraction f) signal path
and a delayed, unattenuated path. The delay time is selectable according to the propagation delay of a
(external) 50Ω BNC cable. Careful selection of fraction and delay cable provides full compensation of timing
distortions due to both amplitude and rise time variations in the input signal. Output signals are generated
whenever the the input signal exceeds the selected threshold set by a front panel 10 – turn dial
potentiometer.
Four simultaneous, independent output signals are provided. The two positive NIM voltage outputs are
adjustable in width; the width duration sets the internal dead time as required to suppress spurious outputs
due to input signal anomalies. The two independent negative NIM current outputs are derived as fixed width
pulses (see also section 3 and 4).
The wide dynamic range of the model 2128N permits its use in many timing applications without the need of
fast pulse amplifiers.
1.2 Setup in ormation
1.2.1 Selection o modes
Front panel mode switch
CFT constant fraction discriminator
CFRR constant fraction discriminator with slow rise time reject
LET leading edge trigger
1.2.2 Fraction
The factory set fraction is f = 0.4. If a different fraction is required, the resistors R1 and R2
( printed board ) have to be modified as follows:
Z0 = 50
R1 = Z0 · f
R2 = Z0 / f
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2 Speci ications
2.1 Inputs
Input proceeds -5mV to about -3.0V linear pulses (ref. to the common
mode range of ultra fast comparators),
rise time ≥ 700ps typically,
Zin = 50Ω; dc-coupled front panel BNC connector;
minimum input width ≥ 1 ns,
in the LET mode the CF 2128N accepts shorter input pulses
Delay two BNC connectors for an external delay cable in order to form the
internal constant fraction signal. For specific length see section
4.2.3.
2.2 Outputs
Inspect displays output signal of zero crossing discriminator for use in
trimming the time walk.
Neg. outputs two independent negative current outputs, each providing -32mA
into 50Ω, rise time ≈ 2 ns, pulse width ≤ 5 ns nominal (for longer
pulse width capacitor C4 has to be changed).
Pos. outputs two independent positive voltage outputs, providing 2V into 50Ω,
rise time ≈ 4 ns, width adjustable by front panel trimming
potentiometer, the width then determines the internal dead time.
The maximum width should not exceed 300 ns.
2.3 Controls
Threshold front panel 10-turn locking dial potentiometer to set acceptance
level for input pulses (range ≈ -5 mV to -1V)
Walk adjust front panel trimming potentiometer (screwdriver) to compensate
walk of the internal zero crossing discriminator
CFT-CFRR-LET front panel three position switch to select basic constant fraction
timing (CFT), constant fraction with slow rise time reject (CFRR) or
leading edge timing (LET)
Width front panel trimming potentiometer (screwdriver) to set the width of
the positive output pulse. The width determines the internal dead
time.
2.4 Indicators
Rate LE indicates activity of the discriminator, colour of LE changes by
count rate; yellow-green up to ≈ 5 kHz, orange 5 to about 10 kHz,
red above 10 kHz
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Speci ications
2.5 Per ormance
Dynamic range 1000:1 (regarding the linearity of the input pulses)
Walk (CFT mode) in CFT mode for a 1 ns rise time input pulse over a 100:1 dynamic
range (reference – 2.5 V) ≈ 60 ps: typically ± 30 ps
Count rate up to 100 MHz, limited by dead time (width setting)
Pulse pair less than 10 ns, or as limited by dead time
Resolution
Threshold better than ± 0.02% / 0C (± 200 ppm / 0C)
Stability
Threshold ± 25 % integral
Linearity
Temperature 0 0C to + 50 0C
Range
2.6 Delay cable
Typical lengths - for fast pulses ≈ 0,25 m to 1 m
- for pulses from slow detectors (e.g. germanium detectors) 1.5 m
to 4 m
For a better determination of the cable length see also section 4.2.3
for very fast rise times the internal cable lengths have to be taken
into account, see also section 4.2.3.
2.7 Power requirements
+6 V / 150 mA
-6 V / 450 mA (standard version), this power exceeds the normal
BIN power allotment of 167 mA for a single 1/12 width NIM module.
2.8 Physical
Size single width NIM module (3.43 x 22.13 cm;
1.35 x 8.71 inches) per TI – 20893 (rev.)
Net weight 0.7 kg (1.6 lbs)
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3 Controls, connectors and indicators
3.1 Front panel
Fig. 3.1: The Front Panel
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CFT – CFRR – LEFT selects
- Constant fraction trigger
- Constant fraction with
slow rise time reject
- leading edge mode
Threshold sets threshold
from -5mV to -1,0V
for signal acceptance
elay for external delay cable
used in CFT and CFRR modes
Walk adjust varies
zero crossing discriminator
adjustment
Positive output connectors,
each supplies a TTL logic
signal into a 50 Ohms load
Width control sets positive
output signal width -
also sets signal dead time
Negative output connectors
each supplies -32mV into
50 Ohms load
Rate LE indicates discriminator
count rate: yellow to 5kHz
orange 5 -10 kHz
red above 10 kHz
Walk inspect allow observation
of zero crossing discriminator
adjustment
Input accepts
-5mV to -3.0V linear pulses
min. input pulse width = 700ps

Operation
4 Operation
4.1 General
The purpose of this section is to familiarize the user with the operation of the model 2128N and to
prove that the unit is working properly. The module can be operated in many different system
configurations, therefore it is difficult to give explicit operating instructions. However, if the guide line
of the listed procedures is followed, the experimentalist will gain sufficient experience with this unit in
order to use it properly.
4.2 Laboratory bench tests
Basic performance tests of the model 2128N may be exercised either in a rack mounted NIM-BIN
(Nuclear Instrumentation Module) power supply or on a laboratory bench with the unit powered by an
extender cable from a NIM-BIN (TI -20893). It is recommended that electrical connections be made
with BIN power off.
4.2.1 Input
Suitable driving pulses may be obtained from laboratory pulsers or pulse generators, or readily
available detector pulse signals. The input network is protected for pulses exceeding 5V in
amplitude. But the user should keep in mind that the linearity is limited by the common mode range
of the ultra fast comparators in the input stages.
4.2.2 Operating mode
The selection of the operating mode depends on the requirements of the experiment.
In the CFT mode (normal constant fraction) the timing is derived from a comparison between an
attenuated pulse (fraction f = 0.4; factory set; f can be easily changed by the user) and a delayed
pulse (delay time td; external delay cable). The derived time mark is (theoretically) independent of the
pulse height of the input signal. For a detailed description of the principle see e.g.:
.A. Gedcke and W.J. Mc onald, Nucl. Instr.& Meth. 56(1968)253
M.R. Maier and P. Sperr, Nucl. Instr. & Meth. 87(1970)13
The choice of the fraction f and the time td (see also section 4.2.3) depends on the detector and the
experimental setup.
In the CFRR mode (constant fraction with slow rise time reject) an option is provided to handle
longer rise times (e.g. solid state Ge-detectors). Normally the timing mark for the CF is derived with
the presumption that the threshold level has been set quite low and this level is exceeded prior to to
the derivation of the time mark. In the case of long varying wavefronts of the input pulses (and if
relatively short delay cables are used) the timing conditions as given above may not be valid. In that
case the level discriminator may switch late. The resulting timing mark will represent some mixture of
the intended CFT timing with leading edge timing. This effect causes tails or even a satellite peak in
a time spectrum. In the CFRR mode an option is given which rejects pulses which have not
exceeded the threshold level prior to the derived CF timing mark. Some loss in the count rate is
obvious.
In the LET mode the model 2128N can be used as a simple leading edge trigger up to very high
count rates. The leading edge mode should only be used with signals having a very short rise time
and a very limited range of amplitudes as change in amplitude will cause walk (see also section 5.1).
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4.2.3 Delay cable
Normally the delay cable used should provide a delay less than the risetime t r of the input pulses.
Theoretically the total delay required can be estimated from the following relation:
td ≈ (1 – f) · tr (f = fraction; tr = risetime of the input signal; td = total delay)
which was found to be the optimum for most applications. The internal delay (cable length front
panel BNC connectors to printed board) is about 0.5 ns. For very fast pulses it is recommended to
measure the delay direct at the input of the high speed comparator (pin 2 and pin 3) and if necessary
to directly install a delay cable omitting the front panel BNC connectors. elay for RG-58 cables is ≈
1.46 ns per foot or ≈ 4.8 ns per meter.
4.2.4 Walk trim
The adjustment of the amplitude sensitive variation of the timing mark (time walk) has to be carried
out very carefully (in the CFT and the CFRR mode). Proper adjustment is only possible when the dc-
offset present at the input is very small. Thus detector leakage or dark current errors must be
minimized before attempting adjustment.
Laboratory trimming of the unit using a fast pulse generator for the first test measurements is
recommended. ifferent settings of the walk adjust potentiometer should be tried in order to find the
optimum time resolution. When the model 2128N is used with the intended detector, time resolution
has to be trimmed experimentally by successive measurements with the setup at hand, because the
resolution depends on many parameters such as fraction, threshold, delay td and walk trim. A
quantitative control is available by monitoring the front panel inspect output with an oscilloscope,
externally triggered with the fast output of the unit.
For fast detectors it turned out that in most cases the inspect signal (not to be terminated with 50Ω)
should be a sharp signal from – 0.4 V to – 0.2 V. (walk trim is already factory set as described). For
slower detectors, a noise band between the levels may be seen, with transitions to high and low of
about equal intensity. Symmetrical center setting should be avoided as the ultra fast comparators
deviate from their optimum performance in this setting.
4.2.5 Outputs
The output pulses from the model 2128N are intended to drive 50Ω loads through any reasonable
length of suitable 50Ω coaxial cable (such as RG-58). As the setting of the width of the positive
output signal is consistent with the internal dead time, the user should set this control due to the
requirements of the pulse rate for the given experiment. The width of the positive output signal
should be less than 300 ns.
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Circuit description
5 Circuit description
5.1 General
The model 2128N provides the advantage that various modes of operation (CFT, CFRR, LET) can
be chosen by selecting the front panel switch. The fraction (factory set to f = 0.4) can be changed
with the resistors R1 and R2 on the printed board. This model utilizes a direct coupled negative input
to perform integral discrimination or/and to derive a constant fraction timing mark. The bulk of the
logic signal processing is executed in emitter-coupled fast integrated circuit logic (ECL using SM
parts). Reference diodes are used to pin all threshold voltages.
5.2 LET mode
Since the model can be operated in various modes, its operation is best appreciated by
understanding the simple LET mode. The input signal is split in a network to serve the two identical
ultra fast comparators (IC1 and IC2, see figure). In the LET mode, both pulse amplitude
discrimination and timing are derived in the comparator IC1. The pulse acceptance level is
established by the front panel threshold potentiometer from -5 mV to – 1.0 V dc. Since the timing
mark for the comparator is derived from the point where the pulse intercepts the threshold setting, it
is quite obvious that the timing mark changes with amplitude and rise time of the input pulse. The
output signal of the comparator (IC1) is accepted through gate IC3 (1/4 of a 10H102) appearing at
the outputs as positive going signal (- 1.7 V to – 0.8 V) and as negative going signal (- 0.8V to -
1.7V). The width of these signals depends on the setting of the leading edge width potentiometer on
the printed board (factory set to about 20ns).
The width can be monitored with a signal probe on the scope. It is recommended, to set the width as
wide as the input signal. The negative output signal of IC3 is accepted through the gate IC6. Note
that with the LET mode (front panel switch) the outputs of the gates IC4 and IC5 are always set to
logic LOW (- 1.7V). The output of gate IC6 is fed to the clock input of a master-slave type flip-flop
IC7 (1/2 of 10H131). The Q – output is fed to a bus driver (10192) and converting the ECL levels to
fast NIM levels (- 32 mA in 50Ω). The width of the output pulse is either determined by a RC
combination. The output of IC7 goes to the clock enable input of a second master-slave flip-flop IC8
(second half of the 10H131). The output of IC8 is converted by the following ECL - to – TTL
translator (10H125) to positive TTL output pulses. The width of the positive output signal is set by the
front panel potentiometer (WI TH control). This width (< 300 ns) also determines the internal dead
time of the module.
5.3 CFT and CFRR mode
In the normal constant fraction mode the applied input signal is sensed for the amplitude by IC1 as
described above, but also routed to the front panel ELAY cable BNC connectors. The delayed
pulse is applied to the inverting input of the comparator IC2. The non delayed but attenuated signal
is applied to the non-inverting input of IC2. The attenuation is determined by the fraction module. The
difference signal between this inputs is a bipolar signal whose zero crossing is the time mark.
Theoretically the time mark for the bipolar signal is zero. Finite errors, such as small dc-offsets on
the input signal, the offset bias of the comparator, as well as the finite gain bandwidth of the device
can cause some time shift or walk in the normal case. With the front panel WALK A JUST, by
monitoring the inspect signal one has the possibility to minimise the time walk. The optimum setting
has to be found experimentally. One logic output of IC2 is applied to gate IC5. Switch S-A is not
grounded in CFT operation. The outputs of IC3 and IC5 are applied to gate IC6. In normal operation
the first negative going pulse is provided from IC3. The following pulse logic is identical as described
above. In the CFT operation switch S-B is grounded, the level at the -input of the flip-flop (IC7) is
always logic LOW (-1.7V).
In cases where slower rise time pulses may cause poor timing performance, the CFRR mode locks
out and rejects those pulses which do not satisfy the THRESHOL setting prior to the derived
constant fraction timing mark.
In the CFRR mode switch S-B is left open. The output signal of IC3 is processed through IC4 and
applied to the data input of the flip-flop IC7. Therefore output signals are only generated when the
threshold signal is prior to the derived timing mark of IC2. Inadvertent timing marks derived from the
leading edge discriminator switching late are blocked.
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6 Special eatures and options
In this section some special features of the model 2128N which are available on request are listed.
6.1 Power supply
Normally ± 6 V from a standard NIM BIN, or on customer request, ± 12 V from a NIM BIN. Or on
customer request, 220 V (ac)/110 V (ac) independent from a NIM BIN. In this case the unit is
mounted in a special housing, for details the supplier should be contacted.
6.2 Input polarity
The standard version of the model 2128N requires negative input polarity. In some cases the output
pulses of detectors have positive polarity. If signal transformers (e.g. Ortec IT 100) are not suitable,
the module can be modified on customer request to accept positive input signals.
6.3 Output width
As already stated above the model 2128N is available with a fixed output width for the negative
output. On customer request the width of the negative output can be enlarged within meaningful
values regarding internal settings.
6.4 Threshold
In the standard version the threshold setting is performed via a front panel potentiometer. On
customer request the threshold voltage can also be supplied externally (e.g. computer controlled) via
a rear panel connector.
6.5 Signal shaping
For some detector systems considerable improvements in time resolution can be achieved using
small fractions ( f ≈ 0.1) and “RC-shaping” of the input signal or the attenuated signal (examples are
given in the literature). The capacitors (to ground) for the signal shaping (input or attenuated signal)
can be easily implemented. If the capacitor is set at the attenuated signal the delay time td has to be
adjusted as follows
td ≈ Z0 · C + (1-f) · tr
The best values for the fraction f, the capacitor C and the delay td have to be determined
experimentally.
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Diagrams
7 Diagrams
7.1 Circuit diagram
Fig. 7.1: The Circuit diagram
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7.2 Board
Fig. 7.2: The Board
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