Hotenda MPC8349EA Instruction manual
Electronic Component Distributor. Source::Freescale Semiconductor
P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
© 2006–2011 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
Technical Data
The MPC8349EA PowerQUICC II Pro is a next generation
PowerQUICC II integrated host processor. The
MPC8349EA contains a processor core built on Power
Architecture® technology with system logic for networking,
storage, and general-purpose embedded applications. For
functional characteristics of the processor, refer to the
MPC8349EA PowerQUICC II Pro Integrated Host
Processor Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC8349EA product summary page on our website,
as listed on the back cover of this document, or contact your
local Freescale sales office.
Document Number: MPC8349EAEC
Rev. 13, 09/2011
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 15
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Ethernet: Three-Speed Ethernet, MII Management . 22
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 53
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
21. System Design Information . . . . . . . . . . . . . . . . . . . 79
22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 82
23. Document Revision History . . . . . . . . . . . . . . . . . . . 84
MPC8349EA PowerQUICC II Pro
Integrated Host Processor Hardware
Specifications
1 / 87
Electronic Component Distributor. Source::Freescale Semiconductor
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
2Freescale Semiconductor
Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See Section 22.1, “Part Numbers Fully Addressed by This Document,” for
silicon revision level determination.
1 Overview
This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8349EA.
Figure 1. MPC8349EA Block Diagram
Major features of the device are as follows:
• Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
TSEC
Coherent System Bus
PCI1
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII
SPI
Serial
IRQs
ROM
I2CI2C Interfaces TSEC
DDR/DDR2
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller
DUART
e300 Core
DMA Controller
Serial Peripheral
Interface
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Sequencer
SEQ
64/32b PCI Controller
PCI2
0/32b PCI Controller
Security Engine
Arbiter Bus
Monitor
USB Hi-Speed
Host Device
General Purpose I/O
USB0
USB1
GPIO
SDRAM
DDR/DD
R2
DMA
MII, GMII, TBI,
RTBI, RGMII
10/100/1Gb
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor 3
Overview
• Double data rate, DDR1/DDR2 SDRAM memory controller
— Programmable timing supporting DDR1 and DDR2 SDRAM
— 32- or 64-bit data interface, up to 400 MHz data rate
— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports
— Full error checking and correction (ECC) support
— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep-mode support for SDRAM self refresh
— Auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
• Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™,
802.3ac™ standards
— Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
• Dual PCI interfaces
— Designed to comply with PCI Specification Revision 2.3
— Data bus width options:
– Dual 32-bit data PCI interfaces operating at up to 66 MHz
– Single 64-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities on both interfaces
— PCI agent mode on PCI1 interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
4Freescale Semiconductor
Overview
— On-chip arbitration supporting five masters on PCI1, three masters on PCI2
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI
• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard (DES) execution unit (DEU)
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits
– ECB, CBC, CCM, and counter (CTR) modes
— XOR parity generation accelerator for RAID applications
— ARC four execution unit (AFEU)
– Stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
• Universal serial bus (USB) dual role controller
— USB on-the-go mode with both device and host functionality
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor 5
Overview
— Complies with USB specification Rev. 2.0
— Can operate as a stand-alone USB device
– One upstream facing port
– Six programmable USB endpoints
— Can operate as a stand-alone USB host controller
– USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
• Universal serial bus (USB) multi-port host controller
— Can operate as a stand-alone USB host controller
– USB root hub with one or two downstream-facing ports
– Enhanced host controller interface (EHCI) compatible
– Complies with USB Specification Rev. 2.0
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Direct connection to a high-speed device without an external hub
— External PHY with serial and low-pin count (ULPI) interfaces
• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects for eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
6Freescale Semiconductor
Electrical Characteristics
• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded
hardware
• DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
DMA_DACK[0:3], DMA_DDONE[0:3]
— All channels accessible to local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
• DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
• Serial peripheral interface (SPI) for master or slave
• General-purpose parallel I/O (GPIO)
— 64 parallel I/O pins multiplexed on various chip interfaces
• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
• Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
• Integrated PCI bus and SDRAM clock generation
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8349EA. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor 7
Electrical Characteristics
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Parameter Symbol Max Value Unit Notes
Core supply voltage VDD –0.3 to 1.32 (1.36 max
for 667-MHz core
frequency)
V—
PLL supply voltage AVDD –0.3 to 1.32 (1.36 max
for 667-MHz core
frequency)
V—
DDR and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75
–0.3 to 1.98
V—
Three-speed Ethernet I/O, MII management voltage LVDD –0.3 to 3.63 V —
PCI, local bus, DUART, system control and power management, I2C,
and JTAG I/O voltage
OVDD –0.3 to 3.63 V —
Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5
DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5
Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5
Local bus, DUART, CLKIN, system control and
power management, I2C, and JTAG signals
OVIN –0.3 to (OVDD + 0.3) V 3, 5
PCI OVIN –0.3 to (OVDD + 0.3) V 6
Storage temperature range TSTG –55 to 150 °C—
Notes:
1Functional and tested operating conditions are given in Ta b l e 2 . Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.
5(M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 3.
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
8Freescale Semiconductor
Electrical Characteristics
2.1.2 Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8349EA. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside these
conditions is not guaranteed.
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349EA.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
Table 2. Recommended Operating Conditions
Parameter Symbol Recommended
Value Unit Notes
Core supply voltage for 667-MHz core frequency VDD 1.3 V ± 60 mV V 1
Core supply voltage VDD 1.2 V ± 60 mV V 1
PLL supply voltage for 667-MHz core frequency AVDD 1.3 V ± 60 mV V 1
PLL supply voltage AVDD 1.2 V ± 60 mV V 1
DDR and DDR2 DRAM I/O voltage GVDD 2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Three-speed Ethernet I/O supply voltage LVDD1 3.3 V ± 330 mV
2.5 V ± 125 mV
V—
Three-speed Ethernet I/O supply voltage LVDD2 3.3 V ± 330 mV
2.5 V ± 125 mV
V—
PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
OVDD 3.3 V ± 330 mV V —
Note:
1GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
G/L/OVDD + 20%
G/L/OVDD
G/L/OVDD + 5%
of tinterface1
1. tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor 9
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349EA for the
3.3-V signals, respectively.
Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling
2.1.3 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2 Power Sequencing
This section details the power sequencing considerations for the MPC8349EA.
2.2.1 Power-Up Sequencing
MPC8349EA does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD,
LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power
Table 3. Output Drive Capability
Driver Type Output Impedance
(Ω)
Supply
Voltag e
Local bus interface utilities signals 40 OVDD = 3.3 V
PCI signals (not including PCI output clocks) 25
PCI output clocks (including PCI_SYNC_OUT) 40
DDR signal 18 GVDD = 2.5 V
DDR2 signal 18
36 (half-strength mode)
GVDD = 1.8 V
TSEC/10/100 signals 40 LVDD = 2.5/3.3 V
DUART, system control, I2C, JTAG, USB 40 OVDD = 3.3 V
GPIO signals 40 OVDD = 3.3 V,
LVDD = 2.5/3.3 V
Undervoltage
Waveform
Overvoltage
Waveform
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
4 ns
(Max)
–3.5 V
7.1 V p-to-p
(Min)
62.5 ns
+3.6 V
0 V
4 ns
(Max)
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
10 Freescale Semiconductor
Power Characteristics
supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current from
3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the
core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.
Figure 4. Power Sequencing Example
I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one
another.
3 Power Characteristics
The estimated typical power dissipation for the MPC8349EA device is shown in Table 4.
Table 4. MPC8349EA Power Dissipation1
1The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Tabl e 5 .
Core Frequency (MHz) CSB Frequency (MHz) Typical at TJ= 65 Typical2, 3Maximum4Unit
TBGA 333 333 2.0 3.0 3.2 W
166 1.8 2.8 2.9 W
400 266 2.1 3.0 3.3 W
133 1.9 2.9 3.1 W
450 300 2.3 3.2 3.5 W
150 2.1 3.0 3.2 W
500 333 2.4 3.3 3.6 W
166 2.2 3.1 3.4 W
533 266 2.4 3.3 3.6 W
133 2.2 3.1 3.4 W
6675, 6 333 3.5 4.6 5 W
I/O Voltage (GVDD, LVDD, OVDD)
Core Voltage (VDD, AVDD)
90%
0.7 V
Time
Voltage
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Freescale Semiconductor 11
Power Characteristics
Table 5 shows the estimated typical I/O power dissipation for MPC8349EA.
2Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ= 105°C, and a Dhrystone benchmark
application.
3Thermal solutions may need to design to a value higher than typical power based on the end application, TAtarget, and I/O
power.
4Maximum power is based on a voltage of VDD = 1.2 V, worst case process, a junction temperature of TJ=105°C, and an
artificial smoke test.
5Typical power is based on a voltage of VDD = 1.3 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark
application.
6Maximum power is based on a voltage of VDD = 1.3 V, worst case process, a junction temperature of TJ=105°C, and an
artificial smoke test.
Table 5. MPC8349EA Typical I/O Power Dissipation
Interface Parameter GVDD
(1.8 V)
GVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V) Unit Comments
DDR I/O
65% utilization
2.5 V
Rs = 20 Ω
Rt = 50 Ω
2 pair of clocks
200 MHz, 32 bits 0.31 0.42 — — — W —
200 MHz, 64 bits 0.42 0.55 — — — W —
266 MHz, 32 bits 0.35 0.5 — — — W —
266 MHz, 64 bits 0.47 0.66 — — — W —
300 MHz, 32 bits 0.37 0.54 — — — W —
300 MHz, 64 bits 0.50 0.7 — — — W —
333 MHz, 32 bits 0.39 0.58 — — — W —
333 MHz, 64 bits 0.53 0.76 — — — W —
400MHz,32bits0.44————— —
400MHz,64bits0.59————— —
PCI I/O
load = 30 pF
33 MHz, 64 bits — — 0.08 — — W —
66 MHz, 64 bits — — 0.14 — — W —
33 MHz, 32 bits — — 0.04 — — W Multiply by 2 if using
2ports.
66 MHz, 32 bits — — 0.07 — — W
Local bus I/O
load = 25 pF
133 MHz, 32 bits — — 0.27 — — W —
83 MHz, 32 bits — — 0.17 — — W —
66 MHz, 32 bits — — 0.14 — — W —
50 MHz, 32 bits — — 0.11 — — W —
TSEC I/O
load = 25 pF
MII — — — 0.01 — W Multiply by number of
interfaces used.
GMII or TBI — — — 0.06 — W
RGMIIorRTBI————0.04W
USB 12 MHz — — 0.01 — — W Multiply by 2 if using
2ports.
480 MHz — — 0.2 — — W
Other I/O — — — 0.01 — — W —
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
12 Freescale Semiconductor
Clock Input Timing
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the device.
4.1 DC Electrical Characteristics
Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8349EA.
4.2 AC Electrical Characteristics
The primary clock source for the MPC8349EA can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 6. CLKIN DC Timing Specifications
Parameter Condition Symbol Min Max Unit
Input high voltage — VIH 2.7 OVDD +0.3 V
Input low voltage — VIL –0.3 0.4 V
CLKIN input current 0 V ≤VIN ≤OVDD IIN — ±10 μA
PCI_SYNC_IN input current 0 V ≤VIN ≤0.5 V or
OVDD –0.5V≤VIN ≤OVDD
IIN — ±10 μA
PCI_SYNC_IN input current 0.5 V ≤VIN ≤ OVDD – 0.5 V IIN — ±50 μA
Table 7. CLKIN AC Timing Specifications
Parameter/Condition Symbol Min Typical Max Unit Notes
CLKIN/PCI_CLK frequency fCLKIN ——66MHz1,6
CLKIN/PCI_CLK cycle time tCLKIN 15 — — ns —
CLKIN/PCI_CLK rise and fall time tKH, tKL 0.6 1.0 2.3 ns 2
CLKIN/PCI_CLK duty cycle tKHK/tCLKIN 40 — 60 % 3
CLKIN/PCI_CLK jitter — — — ±150 ps 4, 5
Notes:
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless
of input frequency.
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor 13
RESET Initialization
4.3 TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8349EA.
5.1 RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8349EA.
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter Symbol Min Typical Max Unit Notes
EC_GTX_CLK125 frequency tG125 —125—MHz—
EC_GTX_CLK125 cycle time tG125 —8—ns—
EC_GTX_CLK125 rise and fall time
LVDD = 2.5 V
LVDD = 3.3 V
tG125R/tG125F ——
0.75
1.0
ns 1
EC_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
—
55
53
%2
EC_GTX_CLK125 jitter — — — ±150 ps 2
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD =3.3V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.4, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.
Table 9. RESET Pins DC Electrical Characteristics1
Parameter Symbol Condition Min Max Unit
Input high voltage VIH —2.0OV
DD +0.3 V
Input low voltage VIL —–0.30.8V
Input current IIN ——±5μA
Output high voltage2VOH IOH = –8.0 mA 2.4 — V
Output low voltage VOL IOL = 8.0 mA — 0.5 V
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14 Freescale Semiconductor
RESET Initialization
5.2 RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the MPC8349EA.
Output low voltage VOL IOL = 3.2 mA — 0.4 V
Notes:
1. This table applies for pins PORESET
, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
Table 10. RESET Initialization Timing Specifications
Parameter Min Max Unit Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow 32 — tPCI_SYNC_IN 1
Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8349EA is in PCI host mode
32 — tCLKIN 2
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8349EA is in PCI agent mode
32 — tPCI_SYNC_IN 1
HRESET/SRESET assertion (output) 512 — tPCI_SYNC_IN 1
HRESET negation to SRESET negation (output) 16 — tPCI_SYNC_IN 1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI host mode
4—t
CLKIN 2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI agent mode
4—t
PCI_SYNC_IN 1
Input hold time for POR configuration signals with respect to negation of HRESET 0— ns—
Time for the MPC8349EA to turn off POR configuration signals with respect to the
assertion of HRESET
—4 ns 3
Time for the MPC8349EA to turn on POR configuration signals with respect to the
negation of HRESET
1—t
PCI_SYNC_IN 1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 9. RESET Pins DC Electrical Characteristics1(continued)
Parameter Symbol Condition Min Max Unit
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor 15
DDR and DDR2 SDRAM
Table 11 lists the PLL and DLL lock times.
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8349EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
NOTE
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications. See Section 22.1, “Part Numbers Fully Addressed by This
Document,” for silicon revision level determination.
6.1 DDR and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8349EA when GVDD(typ) = 1.8 V.
Table 11. PLL and DLL Lock Times
Parameter/Condition Min Max Unit Notes
PLL lock times — 100 μs—
DLL lock times 7680 122,880 csb_clk cycles 1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 1.71 1.89 V 1
I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2
I/O termination voltage VTT MVREF –0.04 MV
REF +0.04 V 3
Input high voltage VIH MVREF + 0.125 GVDD +0.3 V —
Input low voltage VIL –0.3 MVREF –0.125 V —
Output leakage current IOZ –9.9 9.9 μA4
Output high current (VOUT = 1.420 V) IOH –13.4 — mA —
15 / 87
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16 Freescale Semiconductor
DDR and DDR2 SDRAM
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when
GVDD(typ) = 2.5 V.
Output low current (VOUT = 0.280 V) IOL 13.4 — mA —
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to equal 0.5 ×GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise
on MVREF cannot exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤VOUT ≤ GVDD.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA= 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 2.375 2.625 V 1
I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2
I/O termination voltage VTT MVREF –0.04 MV
REF +0.04 V 3
Input high voltage VIH MVREF +0.18 GV
DD +0.3 V —
Input low voltage VIL –0.3 MVREF –0.18 V —
Output leakage current IOZ –9.9 –9.9 μA4
Output high current (VOUT = 1.95 V) IOH –15.2 — mA —
Output low current (VOUT = 0.35 V) IOL 15.2 — mA —
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 ×GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤VOUT ≤ GVDD.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
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Freescale Semiconductor 17
DDR and DDR2 SDRAM
Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V.
Table 16 provides the current draw characteristics for MVREF.
6.2 DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications
Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
Table 18 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.
Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA= 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 16. Current Draw Characteristics for MVREF
Parameter/Condition Symbol Min Max Unit Note
Current draw for MVREF IMVREF —500μA1
Note:
1. The voltage regulator for MVREF must supply up to 500 μA current.
Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 ± 5%.
Parameter Symbol Min Max Unit Notes
AC input low voltage VIL —MV
REF – 0.25 V —
AC input high voltage VIH MVREF + 0.25 — V —
Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions with GVDD of 2.5 ± 5%.
Parameter Symbol Min Max Unit Notes
AC input low voltage VIL —MV
REF – 0.31 V —
AC input high voltage VIH MVREF + 0.31 — V —
17 / 87
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18 Freescale Semiconductor
DDR and DDR2 SDRAM
Table 19 provides the input AC timing specifications for the DDR SDRAM interface.
Figure 5 illustrates the DDR input timing diagram showing the tDISKEW timing parameter.
Figure 5. DDR Input Timing Diagram
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS—MDQ/MECC/MDM tCISKEW ps 1, 2
400 MHz –600 600 3
333 MHz –750 750 —
266 MHz –750 750 —
200 MHz –750 750 —
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ± (T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute
value of tCISKEW.
3. This specification applies only to the DDR interface.
MCK[n]
MCK[n] tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1D0
tDISKEW
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Freescale Semiconductor 19
DDR and DDR2 SDRAM
6.2.2 DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter Symbol 1Min Max Unit Notes
ADDR/CMD/MODT output setup with respect to MCK tDDKHAS ns 3
400 MHz 1.95 —
333 MHz 2.40 —
266 MHz 3.15 —
200 MHz 4.20 —
ADDR/CMD/MODT output hold with respect to MCK tDDKHAX ns 3
400 MHz 1.95 —
333 MHz 2.40 —
266 MHz 3.15 —
200 MHz 4.20 —
MCS(n) output setup with respect to MCK tDDKHCS ns 3
400 MHz 1.95 —
333 MHz 2.40 —
266 MHz 3.15 —
200 MHz 4.20 —
MCS(n) output hold with respect to MCK tDDKHCX ns 3
400 MHz 1.95 —
333 MHz 2.40 —
266 MHz 3.15 —
200 MHz 4.20 —
MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4
MDQ/MECC/MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
ps 5
400 MHz 700 —
333 MHz 775 —
266 MHz 1100 —
200 MHz 1200 —
MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX,
tDDKLDX
ps 5
400 MHz 700 —
333 MHz 900 —
266 MHz 1100 —
200 MHz 1200 —
MDQS preamble start tDDKHMP –0.5 ×tMCK – 0.6 –0.5 ×tMCK + 0.6 ns 6
19 / 87
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20 Freescale Semiconductor
DDR and DDR2 SDRAM
Figure 6 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
Figure 6. Timing Diagram for tDDKHMH
MDQS epilogue end tDDKHME –0.6 0.6 ns 6
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from
the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
set up (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes
low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the
rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the
DQSS override bits in the TIMING_CFG_2 register and is typically set to the same delay as the clock adjust in the CLK_CNTL
register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value.
See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications
enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter Symbol 1Min Max Unit Notes
MDQS
MCK[n]
MCK[n]
tMCK
MDQS
tDDKHMH(min) = –0.6 ns
tDDKHMHmax) = 0.6 ns
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