Npm Motionnet g9001a User manual

DA70131-1/3E

G9001A/G9002A

User's Manual

(Center device / I/O device)

Remote I/O & Remote Motion

DA70131-1/3E

Thank you for considering our super high-speed serial communicator LSI, the "G9000" series.

To learn how to use the G9000 series, read this manual to become familiar with the product.

The handling precautions for installing this LSI are described at the end of this manual. Make sure to

read them before installing the LSI.

[Preface]

(1) Copying all or any part of this manual without written approval is prohibited.

(2) The specifications of this LSI may be changed to improve performance or quality without prior

notice.

(3) Although this manual was produced with the utmost care, if you find any points that are unclear,

wrong, or have inadequate descriptions, please let us know.

(4) We are not responsible for any results that occur from using this LSI, regardless of item (3) above.

(5) Please see the latest version on our website.

[Cautions]

As a next generation communication system, the Motionnet can construct faster and more volume

large, scale-systems with wire saving than conventional T-NET system (conventional LSI product to

construct serial communication system by NPM). Further, it has data communication function which

the T-NET does not have, so that it can control data control devices such as PCL series (pulse train

generation LSI made by NPM).

The Motionnet system consists of one center device connected to a CPU bus, a maximum of 64 local

devices, all connected using cables of two or three conductive cores

[What Motionnet is]

(1) Terminals and signal names with a bar above the name use negative logic.

Ex.: ___

CS means that the CS terminal uses negative logic.

[Logic indicators]

]

DA70131-1/3E

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INDEX

I. Center device (G9001A)...................................................................................................................... I-1

1. Outline................................................................................................................................................. I-3

2. Features .............................................................................................................................................. I-3

3. General specifications....................................................................................................................... I-4

3-1. Communication system specifications .................................................................................... I-4

3-2. Center device specifications (G9001A)..................................................................................... I-5

4. Hardware description ........................................................................................................................ I-6

4-1. A list of terminals (QFP-64) ........................................................................................................ I-6

4-2. Terminal allocation diagram....................................................................................................... I-8

4-3. Entire block diagram................................................................................................................... I-9

4-4. Functions of terminals.............................................................................................................. I-10

4-5. Address map..............................................................................................................................I-14

4-5-1. "Device information" area.................................................................................................I-18

4-5-2. "Cyclic communication error flags" area ...................................................................... I-19

4-5-3. "Change to Input Change Interrupt Setting" area .......................................................... I-20

4-5-4. "Input Change Interrupt Flag" area.................................................................................. I-21

4-5-5. "Port data" area..................................................................................................................I-21

4-6. Status..........................................................................................................................................I-22

4-7. Interrupt status.......................................................................................................................... I-24

4-8. Command...................................................................................................................................I-25

4-8-1. Operation command ..........................................................................................................I-25

4-8-2. Memory access command ................................................................................................ I-27

4-8-3. Register access command................................................................................................ I-28

4-9. Register......................................................................................................................................I-29

4-9-1. RENV0 register ................................................................................................................... I-29

4-9-2. RERCNT...............................................................................................................................I-30

4-9-3. RSYCNT............................................................................................................................... I-30

4-9-4. RDJADD............................................................................................................................... I-30

4-9-5. RVER.................................................................................................................................... I-30

5. Description of the software.............................................................................................................I-31

5-1. Outline of control ......................................................................................................................I-31

5-1-1. Communication control..................................................................................................... I-31

5-1-2. Communication type.......................................................................................................... I-31

5-1-3. Input change interrupt....................................................................................................... I-33

5-1-4. Break function (when RENV0(8) = 0)................................................................................ I-33

5-1-5. Control of communication errors..................................................................................... I-33

5-2. Operating procedure................................................................................................................. I-35

5-2-1. Reset....................................................................................................................................I-35

5-2-2. Cyclic communication procedures .................................................................................. I-35

5-2-3. Data communication procedure ....................................................................................... I-35

5-2-4. Exclude a device with an error ......................................................................................... I-35

5-2-5. Restoring excluded devices to cyclic communications................................................ I-35

5-3. Status after reset.......................................................................................................................I-35

6. How to calculate the communication cycle time.......................................................................... I-36

6-1. Time required for one cycle..................................................................................................... I-36

6-2. Time required for one complete data communication.......................................................... I-36

6-3. Total time of cyclic communication (including data communication)................................ I-36

7. Electrical Characteristicsi-.............................................................................................................. I-37

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7-1. Absolute maximum ratings...................................................................................................... I-37

7-2. Recommended operating conditions...................................................................................... I-37

7-3. DC characteristics..................................................................................................................... I-37

7-4. AC characteristics..................................................................................................................... I-38

7-4-1. Reference clock.................................................................................................................. I-38

7-4-2. Reset timing........................................................................................................................I-38

7-4-3. I/F mode 4 (IF1=H, IF0=H) (8-bit Z80 etc.)I- ...................................................................... I-39

7-4-4. I/F mode 3 (IF1=H, IF0=L) (16-bit 8086 etc.)..................................................................... I-40

7-4-5. I/F mode 2 (IF1=L, IF0=H) (16-bit H8 etc.)......................................................................... I-41

7-4-6. I/F mode 1 (IF1=L, IF0=L) (16-bit 68000 etc.).................................................................... I-42

8. External dimensions........................................................................................................................ I-43

II. I/O device (G9002A) .......................................................................................................................... II-1

1. Outline................................................................................................................................................ II-3

2. Features ............................................................................................................................................. II-3

3. Basic specifications.......................................................................................................................... II-3

3-1. I/O device specifications........................................................................................................... II-3

4. Hardware Description....................................................................................................................... II-4

4-1. List of terminals (QFP-80) ......................................................................................................... II-4

4-2. Terminal assignment drawings................................................................................................. II-6

4-3. Complete block diagram ........................................................................................................... II-7

4-4. Functions of terminals............................................................................................................... II-8

4-5. Status after reset.......................................................................................................................II-11

5. Electrical Characteristics...............................................................................................................II-12

5-1. Absolute maximum ratings..................................................................................................... II-12

5-2. Recommended operating conditions..................................................................................... II-12

5-3. DC characteristics.................................................................................................................... II-12

5-4. AC characteristics.................................................................................................................... II-13

5-4-1. Reference clock................................................................................................................. II-13

5-4-2. Reset timing.......................................................................................................................II-13

5-4-3. Fixed output data timing................................................................................................... II-14

5-4-4. Input data set timing ......................................................................................................... II-14

6. External dimensions....................................................................................................................... II-15

III. Connection Examples and Recommended Environments........................................................ III-1

1. Connection examples...................................................................................................................... III-3

1-1. An example of a circuit to interface a CPU to a center device............................................. III-3

1-1-1. I/F mode 4 (IF1 = H, IF0 = H) .............................................................................................. III-3

1-1-2. I/F mode3 (IF1=H, IF0=L).................................................................................................... III-4

1-1-3. I/F mode 3 (IF1 = L, IF0 = H)............................................................................................... III-5

1-1-4. I/F mode 1 (IF1 = L, IF0 = L)............................................................................................... III-6

1-1-5. Connecting to a CPU without a wait function................................................................. III-7

1-2. Access timing............................................................................................................................III-8

1-2-1. Normal access.................................................................................................................... III-8

1-2-2. Access by commands...................................................................................................... III-10

1-3. Line transceiver and pulse transformer for the center device........................................... III-14

1-4. Line transceivers and pulse transformers for local devices.............................................. III-15

1-5. Complete configuration..........................................................................................................III-17

2. Recommended environment......................................................................................................... III-18

2-1. Cable.........................................................................................................................................III-18

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2-2. Terminating resistor................................................................................................................III-18

2-3. Pulse transformer....................................................................................................................III-18

2-4. I/F chip......................................................................................................................................III-18

2-5. Parts used in our experiments............................................................................................... III-19

2-6. Other precautions ................................................................................................................... III-19

IV. Software Examples (flow chart).....................................................................................................IV-1

1. Assumption.......................................................................................................................................IV-3

1-1. Environment and precautions used for the descriptions.....................................................IV-3

1-2. Commands used .......................................................................................................................IV-3

2. Software Examples ..........................................................................................................................IV-4

2-1. Start of the simplest cyclic communication...........................................................................IV-4

2-2.Specifiy the data for the local devices that are connected ...................................................IV-5

2-3. Set up an input-change interrupt ............................................................................................IV-7

2-4. Check and clear any existing input-change interrupts.........................................................IV-9

2-5. Check and clear cyclic communication errors.................................................................... IV-11

2-6. Communication with port data (port data and data device status)....................................IV-13

2-7. Data communication 1: Put the value in the register of the PCL device ..........................IV-15

2-8. Data communication 2: Read a register in a PCL device ...................................................IV-16

2-9. Data communication 3: Start the PCL device ......................................................................IV-17

2-10. Data communication 4: Start a PCL6045B using a CPU emulation device ....................IV-19

V. Troubleshooting................................................................................................................................V-1

1. Checking the center device .............................................................................................................V-1

2. Checking the local devices..............................................................................................................V-1

3. Checking the system........................................................................................................................V-2

VI. Handling Precautions.....................................................................................................................VI-1

1. Design precautions..........................................................................................................................VI-1

2. Precautions for transporting and storing LSIs.............................................................................VI-1

3. Precautions for mounting ...............................................................................................................VI-2

3-1. Precautions about G9001A and G9002A ................................................................................VI-2

3-2. Precautions about G9002.........................................................................................................VI-3

VII. Differences between G9001 and G9001A...................................................................................VII-1

1. How to distinguish between G9001 and G9001A using a program...........................................VII-1

2. Newly added functions in the G9001A..........................................................................................VII-1

2-1. Main status................................................................................................................................VII-1

2-2. Operation commands..............................................................................................................VII-1

2-3. Register access command......................................................................................................VII-2

2-4. Register.....................................................................................................................................VII-2

2-4-1. RENV0 register ..................................................................................................................VII-2

2-4-2. RERCNT..............................................................................................................................VII-3

2-4-3. RSYCNT..............................................................................................................................VII-3

2-4-4. RDJADD..............................................................................................................................VII-3

2-4-5. RVER...................................................................................................................................VII-3

VIII. The difference between G9002 and G9002A............................................................................VIII-1

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1. G9002A's improvement of G9002A..............................................................................................VIII-1

1-1. Serial communication control terminal ................................................................................VIII-1

1-2. Function of I/O port terminal..................................................................................................VIII-1

2. Difference of electrical Characteristics.......................................................................................VIII-2

2-1. Absolute maximum ratings....................................................................................................VIII-2

2.2 Recommended operating conditions....................................................................................VIII-2

2-3. DC characteristics...................................................................................................................VIII-3

3. External dimension........................................................................................................................VIII-4

DA70131-1/3E

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I. Center device (G9001A)

User's Manual

DA70131-1/3E

I-2

DA70131-1/3E

I-3

1. Outline

This LSI is a center device of the Motionnet system.

It contains 256-byte RAM for controlling I/O and 512-byte RAM for data communication, and can control up to 64

local devices.

The local devices can be classified into I/O devices (G9002A) that control input/output signals such as G8014C on

the T-NET system, and data device (G9003, G9103A, G9004A) that control by data such as G8015. It allocates

device numbers from 0 to 63 for each local device.

One I/O device (G9002A) has 4 ports (1 port = 8 bits) for input/output (select input/output by terminals).

Therefore, all the local devices that connect to the center device use I/O devices (G9002A), you can connect I/Os

of 2048 points (64 units x 4 ports x 8 bits = 2048) by serial communication.

One data device (G9003, G9103Aor G9004A) can communicate max. 256 bytes data (maximum data length of the

PCL device (G9003) will be 8 byte communication and of the PCL device (G9103A) will be 128 byte

communication).

If all of the local devices that connect to the center device use the PCLdevices (G9003 or G9103A), 64 axes can be

controlled by serial communication.

2. Features

- Maximum data transfer speed is 20 Mbps.

- Transfer cycle time is less than 1 msec when 64 local devices are connected (in case of cyclic communication

only).

- One center device can connect up to 256 ports (2048 bits) for I/O connection.

- The center device provides input interrupt function to a CPU.

- Local devices are classified into the following devices:

* "I/O device" dedicated to control I/O port (G9002A)

* "PCL device" to generate pulse strings.(G9003 or G9103A)

* "CPU emulation device" to control data communication between CPUs and other peripheral

equipment.(G9004A)

- Local devices allocate device numbers (0 to 63) with hardware. These device numbers can be assigned at

random in a Motionnet system. Further, by system communication, device numbers can automatically be

allocated.

- The center device is integrated with a memory for I/O ports. Thus, the center device can operate I/O status just

like accessing normal memories.

- The center device is integrated with four types of CPU-I/F circuits (Z80, 8086, H8, 68000, etc.). As it applies for

typical CPU interfaces, it will offer wide possibility to interface with a variety of CPUs.

- The center device normally uses 512 bytes area as address area. However, if resource is shorted, it can use

8-byte areas.

- Input 3.3 V single power as power supply.

However, the major terminals can be connected to devices that run with 5 V.

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3. General specifications

3-1. Communication system specifications

Item

Description

Reference clock Note 1

40 MHz or 80 MHz

Communication speed Note 2

2.5 M, 5 M, 10 M, or 20 Mbps

Communication code

NRZ code

Communication protocol

NPM original method

Communication method

Half-duplex communication

Communication I/F Note 3

RS-485 or pulse transfer

Connection method

Multi-drop connection

Number of local devices

64 devices max.

Cyclic communication cycle when 20 Mbps

Note 4

When using 8 local devices

(IN: 128 points, OUT: 128 points) --- 0.12 msec.

When using 16 local devices

(IN: 256 points, OUT:256 points) --- 0.24 msec.

When using 32 local devices

(IN: 512 points, OUT: 512 points) --- 0.49 msec.

When using 64 local devices

(IN: 1024 points, OUT: 1024 points) --- 0.97 msec.

Note 1:When transferring data with 20 Mbps speed, and if the clock duty can be maintained to ideal "50:50"

condition, the center device can be operated by inputting 40 MHz clock signal.

The above ideal conditions mean that an oscillator and the center device are connected as 1:1 and close to

each other. (Actually, even these conditions cannot establish 50:50. However, a duty approximate to the

ideal one will be established.

Even if the ideal duty is broken a little, when signal lines are shorter and/or the number of local devices is

smaller, the center device can operate without any trouble. (For the details, see the section for the "CLK"

terminal.)

When the signal lines are longer and/or the number of connected local devices is greater and if it is difficult

to warranty the clock duty, you should take measures such as preparing an 80 MHz signal or preparing a 40

MHz clock proprietary to the center device.

To select clock rate, specify by using the LSI terminal. In either clock rate, the maximum speed of 20 Mbps

is the same.

Note 2:Select the communication speed by using the LSI terminal. Regardless of the selection of the

communication speed, the reference clock remains the same.

Note 3:NPM recommends using a system with a pulse transformer.

Note 4:The number of I/O ports in the parenthesis is true when the all the connected local devices are connected

as I/O device (G9002A).

When data devices are connected such as PCLdevice (G9103A), the number of available I/O points will be

decreased. However, basic cyclic cycle (alt. frequency) does not change. (When the center device

communicates data, the frequency will be changed. For this matter, see the "Calculation of communication

time" in this manual.

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3-2. Center device specifications (G9001A)

Item

Description

Address area

Normally it uses 512 bytes area (A0 to A8).

However, 8 bytes area (A0 to A2) can be used when using the I/O buffer (Note).

Address map

Communication

data length

1 to 128 word/frame (1 word = 16 bits)

Data

communication

time

When communicating 3 words (write 1 register of PCL(G9103A)) --- 19.3 μs

When communicating 128 words --- 168.1 μs

CPU-I/F

Integrated 4 types of CPU-I/F circuit (Z80, 8086, H8, 68000 etc.)

Transfer method

Cyclic transfer for I/O port, transient transfer for data communication

Package

64-pin QFP (model section: 10 x 10 x 1.4 mm)

Power source

3.0V to 3.6V

Storage

temperature range

-65 to +150°C

Operating

temperature range

-40 to +85°C

Note: By issuing an operation command to the center device, you can access the entire address area through a

single I/O buffer. (It will take more time than direct access.)

Required address area is only 8-bytes (3 address signals).

For concrete use example, see the software examples in chapter IV.

Address (h)

Writing

Reading

000 to 001

Command

Status

002 to 003

Invalid

Interrupt status

004 to 005

I/O buffer

006 to 007

Data sending FIFO

Data receiving FIFO

008 to 077

Not specified (112 bytes)

078 to 0B7

Device information (8 bits /

device)

Device information (8 bits / device)

0B8 to 0BF

Reset cyclic

communication error flag

Cyclic communication error flag

0C0 to 0DF

Set input port change

interrupt

Set input port change interrupt

0E0 to 0FF

Reset input port change

interrupt flag

Input port change interrupt flag

100 to 1FF

I/O port data

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4. Hardware description

4-1. A list of terminals (QFP-64)

No.

Name

I/O

Logic

Description

Option

1 IF0 I －

CPU-I/F mode setting bit 0

IF1

－

CPU-I/F mode setting bit 1

____

I Negative Select chip

____

WR (R/W) I Negative Write

____

RD I Negative Read

A0(LS)

Positive

Address bus bit 0 (LSB)

Positive

Address bus bit 1

Positive

Address bus bit 2

Positive

Address bus bit 3

Positive

Address bus bit 4

Positive

Address bus bit 5

Positive

Address bus bit 6

Positive

Address bus bit 7

Positive

Address bus bit 8

Positive

Data bus bit 0 (LSB)

Positive

Data bus bit 1

Positive

Data bus bit 2

Positive

Data bus bit 3

Positive

Data bus bit 4

Positive

Data bus bit 5

Positive

Data bus bit 6

Positive

Data bus bit 7

Positive

Data bus bit 8

Positive

Data bus bit 9

D10

Positive

Data bus bit 10

D11

Positive

Data bus bit 11

D12

Positive

Data bus bit 12

D13

Positive

Data bus bit 13

D14

Positive

Data bus bit 14

D15

Positive

Data bus bit 15

_____

INT O Negative Interrupt request

_____

WRQ

(ACK) O Negative Wait request (_______

DTACK signal in 68000 CPU)

_____

IFB

O Negative CPU I/F is busy

40 ______

MCRY O Negative

By detecting a communication line signal, this signal

becomes L for a rated interval.

41 ______

MERR O Negative

When received an error frame and no response, this

signal becomes L level for a rated interval.

43 ______

MERF O Negative

When receiving an error response frame, this signal

becomes L level for a rated interval.

MSYN

－

The level reverses at each cyclic cycle.

______

SOEL

O Negative Enable serial output

DA70131-1/3E

I-7

No.

Name

I/O

Logic

Description

Option

SOEH

Positive

Enable serial output

Positive

Serial output (Tristate output)

SPD0

－

Specify communication speed bit 0

SPD1

－

Specify communication speed bit 1

SIA

Positive

Serial input A

SIB

Positive

Serial input B

CKSL

－

Select clock rate (Low:40MHz High:80MHz)

58 CLK I －

Reference clock

_____

RST I Negative Reset

GND －Power GND

VDD －Power +3.3V

Note 1: "I" in the I/O column is for input, "O" is output, and "B" is both directions.

Note 2: The terminals with #5V" in the Option column can be connected to the TTL level IC of 5V. The input

terminals can be connected to 5V CMOS, 3.3V CMOS, TTL, LVTTL, and so on. The output terminals

can be connected to 3.3V CMOS (cannot be connected to 5.5V CMOS), TTL, LVTTL, and so on.

However, the connection of over 3.3V to output cannot be available. [For example, output with 5V

pull-up resistors cannot be 5V CMOS.]

Note 3: As for the terminals with "5V" in the Option column, note the following.

* These terminals can be input at 5 V level signal. These are deleted diodes for overcurrent protection

on 3.3 V lines. If over voltage may be possible to charge due to reflection, linking, or inductive noise,

we recommend inserting a diode for overcurrent protection.

* Outputs (includes bidirectional) from 5V devices can be connected to the center device as far as

these are TTL level. (Even if a signal is pulled up to 5V, the output level will be less than 3.3 V.)

However, CMOS level signals cannot be connected.

* On the CPU bus interface, pull up of 5 V level is possible for stabilizing bus lines (prevent floating).

Use 10 k-ohm or larger capacity pull up resistors.

Note 4: The terminals with "U" in the Option column contains pull-up terminals.

Note 5: The terminals with "S" in the Option column is Schmitt triggers.

DA70131-1/3E

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4-2. Terminal allocation diagram

Note: For each pin number, see the marks on the actual LSI.

As shown above, to the lower left of the NPM logo mark is the 1st pin.

G9001A

D12

GND

D11

D10

VDD

GND

XXXXXXXXX

JAPAN

SPD0

SPD1

SIA

GND

VDD

SIB

GND

CKSL

GND

CLK

VDD

GND

____

RST

VDD

SOEH

_____

SOEL

MSYN

_____

MERF

GND

_____

MERR

_____

MCRY

____

IFB

____

WRQ

____

INT

VDD

D15

D14

D13

IF0

IF1

___

GND

VDD

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4-3. Entire block diagram

Memory area

Reset control circuit

Clock control

circuit

CPU I/F circuit

Memory area

control circuit

Command

control circuit

Device information area

Cyclic communication error flag

Input change interrupt setting area

Data receiving

FIFO

Serial signal

receiving circuit

Receipt data

processing

circuit

Transfer

processing

circuit

Data transfer

FIFO

Serial signal

transfer circuit

SIA

SIB

Internal clock (20 MHz)

Internal clock(40 MHz)

Internal reset

G9001A

Input change interrupt flag area

Port 0 data area

Port 1 data area

Port 2 data area

Port 3 data area

___

IF(1:0)

A(8:0)

D(15:0)

____

INT

____

WRQ

____

IFB

SOEH

_____

SOEL

_____

MSYN

_____

MCRY

_____

MERR

_____

MERF

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4-4. Functions of terminals

4-4-1. CLK

This is an input terminal of the reference clock. By setting of the CKSL terminal, either of the following clock rate

signals can be connected.

CKSL = L: 40 MHz

CKSL = H: 80 MHz

By selecting either of these clock rates, the serial communication transfer rate does not change. This clock rate

selection affects communication precision.

For a small-scale serial communication and transfer rate below 10 Mbps, use of the center device with 40 MHz

does not give any restriction.

With 20 Mbps transfer speed; however, longer communication lines or a large number of connected local devices

may deteriorate communication precision due to collapse of signals on the circuit. This deterioration of

communication quality can be corrected inside the LSI, if the deterioration level is not much. In order to improve

correction precision; however, evenness of the clock duty is required. In other words, if the duty is ideal (50:50), the

capacity to correct collapse of the signals in the communication lines can be improved. On the contrary, if the duty

is not ideal, the center device cannot cope with collapses of the communication line.

As a result, if the duty is close to ideal, the center device can be used with 40 MHz. When connecting more than

one oscillator, the duty will not be ideal. In this case, select 80 MHz. The center device divides the frequency inside

and creates 40 MHz frequency.

If you do not want to use 80 MHz frequency, you may prepare a separate 40 MHz oscillator for this LSI.

4-4-2. ____

RST

This is an input terminal for a reset signal.

By inputting an L level signal, the center device is reset. As the center device synchronizes with a clock, arrange a

circuit so that it does not disconnect the clock while resetting. Reset signal length longer than 10 clock cycles is

required.

4-4-3. CKSL

Use to select clock rate.

L: Connect 40 MHz clock frequency to the CLK terminal.

H: Connect 80 MHz clock frequency to the CLK terminal.

Select this when the duty of the 40 MHz clock collapses too much.

4-4-4. IF0, IF1

Specify CPU-I/F mode

Set status

I/F mode

CPU signal to connect to terminals

Example of CPU

IF1 IF0

____

terminal

____

terminal

_____

WRQ

terminal

I/F mode 1

(VDD)

R/W

_____

LDS

________

DTACK

68000

I/F mode 2

____

_____

HWR

(VDD)

_______

WAIT

I/F mode 3

____

(GND)

READY

8086

I/F mode 4

____

_______

WAIT

Z80

This LSI has the following four interface modes.

The above four CPUs are typical ones among CPUs currently available on the market. Even if a CPU you are

examining is other than the above CPUs, most of the CPUs can be connected using either of the interfaces above.

For details, see the hardware specification sheets of the CPU you are planning to use, and check with which mode

you can connect.

Note: The classification of the CPU interface modes above is applicable only for the center device. The CPU

emulation device G9004A also has unique CPU interface modes. Mode classification of this is different than

the above.

DA70131-1/3E

I-11

4-4-5. ___

Input L level signal to this terminal when accessing this LSI.

4-4-6. ___

RD ,

___

WR , A0, _______

WRQ

Connect I/F signals with a CPU. Input signals vary with setting of the IF0 to 1.

For the details, see items "IF0 and IF1."

4-4-7. ____

INT

Outputs an interrupt request signal.

When not using this terminal, keep this terminal open.

4-4-8. ____

IFB

Use this terminal when connecting with a CPU having no wait control input terminal.

By reading a command from a CPU, this signal becomes L level. When the command process is complete, this

signal returns to H level. After confirming that this terminal is H level, access the center device.

4-4-9. A1 to A8

Enter address signal to these terminals.

When the IF1 is L, address bus A1 to A8 are inverted inside.

When to control at 8-byte area, process as follows:

IF1 terminal status

A (8:3) process

Remarks

Pull up (set to H)

I/F mode 1, 2

GND (set to L)

I/F mode 3, 4

4-4-10. D0 to D7

Connect lower 8 bits of the data bus.

4-4-11. D8 to D15

Connect upper 8 bits of the data bus.

When used as I/F mode 4 (IF1 = H, IF0 = H), pull up or pull down with 5 to 10 K-ohms resistor.

(Use of one resistor for 8 lines is also available.)

4-4-12. SPD0, SPD1

Specify communication speed with these terminals.

SPD1

SPD0

Communication speed

2.5 Mbps

5 Mbps

10 Mbps

20 Mbps

All of the devices on the communication line shall be set to the same speed.

Either 40 MHz or 80 MHz is connected to the clock signal, as far as you do not mistake setting of the "CKSL," you

can get communication speed of 20 Mbps.

DA70131-1/3E

I-12

4-4-13. SO

Serial output signal for communication. (Positive logic, tristate output)

Connect this line to a data input of a RS485 device.

4-4-14. SOEH, _____

SOEL

Output enable signal for communication.

Difference between SOEH and _____

SOEL is that only logic is different.

When sending signals, SOEH will become H and _____

SOEL will become L.

Connect either of needed signal to the data enabled input of a RS485 device.

4-4-15. SIA, SIB

Serial input signals for communication. (Positive logic)

Basically these two are identical in functions.

Each of them can construct independent signal line as follows.

Commonly using the serial output signal "SO" from the center device, provide RS485 and pulse transformer

individually for each line, the signal line load can be decreased.

When connecting to many local devices on one line, or when a signal line is long, signal quality will be deteriorated

remarkably. In order to prevent this problem, separate to two lines.

Even divided into two lines, use easiness from a CPU is identical.

One line can connect to max. 64 devices. Even when two lines are used, the max. number of devices is 64. If you

use only one line, the unused terminal should be fixed to GND.

When “clock control synthesized function to control motor” is used in G9103A, you cannot separate to two lines.

4-4-16. _______

MCRY

This is a monitor output to confirm communication.

When a signal is transferred on the signal line, this terminal outputs L signal. If there is no signal on the signal line,

this terminal outputs H signal.

4-4-17. _______

MERR

This is a monitor output to check communication quality.

When the center device receives an error frame such as a CRC error, or when it cannot receive a response frame

within 20 s, the signal becomes L only for 128 cycles (3.2 s) of the CLK.

By measuring the condition using the counter, you can check communication quality.

Center

device

Line

Transceiver

Transformer

Local

device

Local

device

Local

device

Transformer

SIA

SIB

Local

device

Local

device

Local

device

Line

Transceiver

DA70131-1/3E

I-13

4-4-18. _______

MERR

This is a monitor terminal to confirm communication control status.

When the center device receives an error response frame, this terminal outputs L level signal only for 0.2 seconds.

The error response frame is as follows:

A local device normally receives signals from the center device if there is no CRC error on the local device.

However, it may possible that the received data do not match with the local device status (such as receiving output

data on the input port). (It may possible because of the mistakes from the CPU.)

In this case, the local device sends back the data to the center device in order to notify the center device that the

received data is useless.

This is error response frame.

Other case is that a local device sends data longer than 128 bytes to a PCL device (G9103A 128 bytes FIFO), and

the PCL device returns receipt process error (format error).

4-4-19. MSYN

This is a monitor output of cyclic communication cycle.

Each time a cyclic communication cycle ends, this signal level changes between L and H.

DA70131-1/3E

I-14

4-5. Address map

Address map (1) I/F mode 4 (Please be aware of Notes 1 and 2 while accessing)

A0 to A8

Writing

Reading

0 0000 0000

000h

Command bits 0 to 7 Note 1

Status bits 0 to 7

0 0000 0001

001h

Command bits 8 to 15 Note 1

Status bits 8 to 15

0 0000 0010

002h

Invalid

Interrupt status bits 0 to 7

0 0000 0011

003h

Invalid

Interrupt status bits 8 to 15

0 0000 0100

004h

Input/output buffer bits 0 to 7

0 0000 0101

005h

Input/output buffer bits 8 to 15

0 0000 0110

006h

Data transfer FIFO bits 0 to 7 Note 1

Data receiving FIFO bits 0 to 7 Note 2

0 0000 0111

007h

Data transfer FIFO bit 8 to 15 Note 1

Data receiving FIFO bits 8 to 15 Note 2

0 0000 1000

0 0111 0111

008h

077h

Not defined (112 bytes)

(Any data written here will be ignored.) Not defined (112 bytes)

(Always read as 00h.)

0 0111 1000

078h

Device information (Device No. 0)

Device information (Device No.0)

0 0111 1001

079h

Device information (Device No. 1)

Device information (Device No.1)

| | | |

0 1011 0110

0B6h

Device information (Device No. 62)

Device information (Device No.62)

0 1011 0111

0B7h

Device information (Device No. 63)

Device information (Device No.63)

0 1011 1000

0B8h