PDQLogic QTrace User manual

INTRODUCTION QTRACE -USER MANUAL
Revision 1.01
August 2018
QTRACE -USER MANUAL

Contents
1. INTRODUCTION ............................................................................................................................................ 5
1.1 TRACE OVERVIEW............................................................................................................................................. 5
1.2 QTRACE SYSTEM CONNECTIONS .......................................................................................................................... 5
1.3 SUPPORTED IDES............................................................................................................................................. 6
1.4 SUPPORTED TARGET DEVICES .............................................................................................................................. 6
1.5 SYSTEM REQUIREMENTS ....................................................................................................................................7
1.6 QTRACE HARDWARE SPECIFICATION.....................................................................................................................7
1.7 TARGET CONNECTION........................................................................................................................................ 8
1.8 RECOMMENDATIONS FOR PCB LAYOUT OF TRACE SIGNALS ......................................................................................8
1.9 FRONT PANEL STATUS LED.................................................................................................................................9
1.10 PRECAUTIONS.................................................................................................................................................. 9
2. QTRACE ANALYSER OVERVIEW....................................................................................................................10
2.1 INSTALLATION................................................................................................................................................10
2.2 QTRACE ANALYSER LAYOUT .............................................................................................................................10
2.2.1 Drop-down menu and toolbar .............................................................................................................. 11
2.2.2 Status bar.............................................................................................................................................. 12
2.2.2.1 Taskbar icon..................................................................................................................................................12
2.2.3 Trace views ........................................................................................................................................... 12
3. SOURCE VIEWER..........................................................................................................................................13
3.1 FUNCTION TREE-VIEW .....................................................................................................................................13
3.2 SOURCE FILE VIEW.......................................................................................................................................... 13
3.2.1 Code coverage....................................................................................................................................... 14
3.2.2 Code coverage pause and clear ............................................................................................................ 16
3.2.3 Single stepping and execution count latency........................................................................................ 16
3.2.4 Loop timing ........................................................................................................................................... 16
3.2.5 Execution heat map .............................................................................................................................. 16
3.2.6 Navigating to function implementations .............................................................................................. 17
3.2.7 Find text ................................................................................................................................................ 17
3.2.8 Find function from clipboard................................................................................................................. 18
3.2.9 Source view bookmarks ........................................................................................................................ 18
3.3 ITM DEBUGGING ...........................................................................................................................................19
3.4 GENERAL SETTINGS ........................................................................................................................................21
4. TRACE CAPTURE ..........................................................................................................................................22
4.1 TRACE CAPTURE TRIGGER ................................................................................................................................ 22
4.1.1 Trace Point ............................................................................................................................................ 23
4.2 TRACE CAPTURE VIEW ..................................................................................................................................... 23
4.2.1 CPU instruction list view ....................................................................................................................... 24
4.2.2 Simple source view................................................................................................................................ 24
4.2.3 Function timeline .................................................................................................................................. 25
4.2.3.1 Timeline controls ..........................................................................................................................................25
4.2.3.2 Function pinning ...........................................................................................................................................26
4.2.3.3 Timeline function search...............................................................................................................................26
4.2.3.4 Measuring timeline intervals ........................................................................................................................26
4.2.4 Find trace record ................................................................................................................................... 27
4.2.5 Go to source.......................................................................................................................................... 28
4.2.6 Trace record bookmarks ....................................................................................................................... 28
4.2.7 Instruction list-view context menu........................................................................................................ 28
4.3 EXCEPTION TRACE CAPTURE.............................................................................................................................. 29
4.3.1 Problems setting exception handler trigger.......................................................................................... 30
5. PROFILING...................................................................................................................................................31
5.1 CPU TIMING ................................................................................................................................................. 33
6. TRACE CONFIGURATION..............................................................................................................................34

6.1 TRACE CONFIGURATION DIALOG ........................................................................................................................34
6.1.1 Manufacturer........................................................................................................................................ 35
6.1.2 Part/Family ........................................................................................................................................... 35
6.1.3 ROM start address ................................................................................................................................ 35
6.1.4 ROM size ............................................................................................................................................... 36
6.1.5 Trace clock divider ................................................................................................................................ 36
6.1.6 C++ project ............................................................................................................................................ 36
6.1.7 Save paths relative to configuration file ............................................................................................... 36
6.1.8 Vector table address ............................................................................................................................. 36
6.1.9 ELF file................................................................................................................................................... 36
6.1.10 Source paths ..................................................................................................................................... 37
6.1.11 Missing source files........................................................................................................................... 37
6.1.12 Additional code ranges..................................................................................................................... 39
6.1.13 Trace configuration source ............................................................................................................... 40
6.1.14 Initialisation RAM area..................................................................................................................... 40
6.1.15 Debugger script ................................................................................................................................ 40
6.1.16 Trace port voltage ............................................................................................................................ 40
6.2 FINALISING TRACE CONFIGURATION.................................................................................................................... 40
7. TRACE START SEQUENCE .............................................................................................................................42
8. SELF TEST MODE..........................................................................................................................................44
9. RECOMMENDATIONS ..................................................................................................................................45
9.1 GENERAL...................................................................................................................................................... 45
9.2 PROGRAMMING TIPS ...................................................................................................................................... 45
10. PC SPECIFICATION ...................................................................................................................................46
11. TROUBLESHOOTING ................................................................................................................................47
12. TRACING WITH COMMON IDES...............................................................................................................49
12.1 LOCATION OF DEBUGGER SCRIPTS ...................................................................................................................... 49
12.2 EXAMPLE PROJECTS........................................................................................................................................ 49
12.3 SEGGER J-LINK INSTRUCTION SIMULATION........................................................................................................... 50
12.4 ATOLLIC TRUESTUDIO ...................................................................................................................................51
12.5 IAR EMBEDDED WORKBENCH ..........................................................................................................................56
12.6 KEIL MDK .................................................................................................................................................... 57
12.7 SEGGER EMBEDDED STUDIO /ROWLEY CROSSWORKS FOR ARM ............................................................................58
12.8 ST SYSTEM WORKBENCH.................................................................................................................................59
12.9 VISUALGDB.................................................................................................................................................. 61
APPENDIX A MANUAL DRIVER INSTALLATION....................................................................................................63
APPENDIX B STM32-EVAL DEMONSTRATOR ......................................................................................................65
APPENDIX C NOSLEEP UTILITY............................................................................................................................66

Document History
Revision
Date
Changes
1.00
12/07/18
First release
1.01
06/08/18
Finalising trace configuration section added

Introduction QTRACE -USER MANUAL
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1. Introduction
QTrace is a low cost real-time instruction trace system for ARM Cortex M3/M4 processors. It gives
exceptional insight and detailed views of how a target application is running and aids locating hard-to-
find bugs. The system consists of a hardware trace probe and a Windows based trace analyser. It allows
completely unobtrusive full speed tracing and does not require any instrumentation code to be added
to the target application.
With QTrace you don’t need to be a high‐end user with a big budget or wait until
you encounter a really nasty bug before deciding to purchase a trace system.
1.1 Trace overview
Historically, trace systems have been very expensive and have required large connectors to interface to
the users' target board. Trace hardware probes typically contained large amounts of RAM to capture
trace data when a user defined event was triggered. The resulting data was then uploaded to the host
PC for laborious offline analysis.
With the introduction of the ARM Cortex M3/M4 processor cores comes a small footprint trace
interface. Many microcontroller devices based on this core contain a hardware block called an
Embedded Trace Macrocell (ETM) which enables instruction tracing of an application in real-time. The
interface to the ETM block is typically a clock and 4 data lines which are usually presented as multi-
purpose microcontroller GPIO lines that can be programmed to operate as a trace port. These high
speed trace signals are combined with the standard JTAG or SWD debug signals and connect to a 20 way
0.05" pitch header, see Figure 3. An external trace probe is required to decode the trace data frames
streamed by the trace port and transmit their payload data to a host PC.
By implementing a high speed communication link between the trace hardware probe and PC, it is
possible to stream the trace data directly to the PC without the need to capture and then review offline.
This allows a continuous view of what the target application is doing and makes trace far more useful
and easier to visualise than a large collection of static trace records.
To handle high trace data rates resulting from this configuration, the specification of the host PC is
important. It needs to decode the trace data and present a summary of the target processor execution
in real-time with minimal latency and without losing data. PC specification is outlined in section 10 on
page 46.
1.2 QTrace system connections
The block diagram in Figure 1 shows how QTrace connects to a development system and Figure 2 shows
a picture of an example hardware set-up. The QTrace probe is a little different to conventional trace
units in that it doesn't integrate a JTAG1interface. Instead it uses a splitter cable to tap-off the trace
signals from the 20 way target trace connector. The target JTAG signals connect separately to the users'
JTAG adapter.
A USB 3.0 connection from on the development PC is used to power the QTrace probe and to stream
trace data from it. A standalone Windows application, the QTrace Analyser, configures the probe then
decodes and displays its streamed trace data.
Having a separate analyser application operating independently of the user supplied IDE2means that
investment in existing development tools is not lost. Refer to section 2 for further details of the QTrace
Analyser.
1References to JTAG also include SWD
2IDE refers to an integrated development environment and its debugger

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Figure 1 QTrace block diagram
The QTrace system does not control the target JTAG interface and so does not configure target trace
hardware directly. Instead, a debug script is run from the IDE to configure the target trace pins and
registers. This is done after the target FLASH has been programmed but before the application is run.
1.3 Supported IDEs
A number of debugger scripts are supplied with the QTrace Analyser to support most common IDEs, as
shown in Table 1 below.
IDE
Version Tested
See Section
Atollic TrueSTUDIO
V9.0.0
12.4
IAR Embedded Workbench
V8.20
12.5
Keil MDK
V5.20
12.6
Segger Embedded Studio
V3.34
12.7
ST System Workbench
V2.4
12.8
VisualGDB
V5.3r5
12.9
Table 1 Supported IDEs
1.4 Supported target devices
The QTrace probe will interface to any ARM Cortex-M3/M4 based processor with an ETM trace port.
Currently the QTrace Analyser supports STM32 F1/F2/F3/F4/L4 devices from ST Microelectronics that
have the ETM trace option. More manufacturers and devices will be added, see www.pdqlogic.com for
further details.

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Figure 2 Example QTrace hardware connection
1.5 System requirements
A PC running 64-bit Windows 7, 8.1 or 10 with the preferred hardware specification:
Intel i5/i7 dual or quad core CPU running at 2GHz min.
8GB+ RAM
A spare USB 3.0 port
Screen resolution of 1366 x 768 or better (ideally a 2nd screen)
A user supplied IDE and JTAG adapter
Target hardware containing an ARM Cortex M3/M4 based processor and a 20 way ETM trace
connector with 4-bit data and clock (1.8V - 3.3V levels), see Figure 3.
1.6 QTrace hardware specification
The following gives an overview of the QTrace hardware specifications
Parameter
Min
Max
Units
Power supply
(USB 3.0 powered)
Voltage
4.0
6.0
Volts
Current
-
300
mA
Input voltage3range 1
(1.8V nom)
Vin Low
-0.2
0.38
Volts
Vin High
0.8
3.6
Volts
Input voltage3range 2
(3.3V nom)
Vin Low
-0.2
0.8
Volts
Vin High
2.0
3.6
Volts
Target clock frequency (FTarget)
(Trace clock = FTarget /2)
4
180
MHz
Trace data to clock set-up time
0.0
-
ns
Trace data to clock hold-up time
0.2
-
ns
EMC compliance
EN55024, EN55032
Table 2 QTrace hardware specification
3Input voltage range is specified in the QTrace Analyser configuration dialog
10 to 20 way
converter PCB
Splitter
Ribbon
Cable
QTrace
Probe
JTAG Unit
(not supplied)
Development Board
(not supplied)

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1.7 Target connection
Below are the pin assignments for the ARM Cortex-M 20 pin trace connector. It has a 0.05" pitch and
provides access to the 4-bit ETM interface and JTAG / SWD signals.
Figure 3 Pin assignments of the ARM Cortex-M 20 pin trace connector
1.8 Recommendations for PCB layout of Trace Signals
A good PCB layout for the trace signals is crucial for reliable operation. Below are some
recommendations for PCB layout of the trace signals:
Place the trace connector close to the processor pins
Add 0402 series termination resistors e.g. 22R next to the processor trace pins
Use low capacitance ESD diodes on the trace signals and place them close to the trace
connector
Keep tracks the same length
Do not insert vias
Route all tracks over an unbroken ground plane which is on the first inner layer (the FR4
laminate thickness between the top and ground plane layers should typically be 5 mil)
Figure 4 shows an example of trace signal routing on the STM32-EVAL demonstrator PCB (see Appendix
BSTM32-Eval Demonstrator. The trace signals are highlighted in red and the component outlines of
the 0402 series resistors and ESD diodes are highlighted in yellow.
Figure 4 Example trace schematic and PCB signal routing

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1.9 Front panel status LED
The bi-colour front panel LED conveys the current status of the QTrace probe. Below is a summary of
the possible states:
Colour
QTrace State
Red
Trace decoder hardware is unconfigured
Red flashing
No trace clock detected or unable to synchronise with trace data
Green
Streaming trace data
Green flashing
Trace data has stalled e.g. break point hit
Table 3 Front panel LED states
1.10 Precautions
There are several issues to be aware of when using the QTrace probe:
1) Do not connect a powered target processor to an unpowered QTrace probe i.e. when it isn’t
connected to a PC via a USB 3.0 lead. Doing so will cause internal ESD diodes to continuously
conduct which may damage them. It may also damage the trace pins on the target processor.
2) The QTrace probe should not be connected to a USB 3.0 lead greater than 2 metres long. The
lead should have high frequency ferrites at both ends as per the supplied lead.
3) Do not force the USB lead connector into the QTrace probe. If it does not mate easily then the
USB lead connector may be damaged and the lead should be replaced.

QTrace Analyser Overview QTRACE -USER MANUAL
© 2018 PDQLogic Ltd. QTrace User Manual Rev 1.01 Page 10
2. QTrace Analyser Overview
The QTrace Analyser is a standalone application that runs on 64-bit Microsoft Windows 7, 8.1 and 10. It
interfaces to the QTrace probe via a USB3 connection and configures it for the chosen target device. The
analyser then decodes and displays streamed trace data, independently of the IDE.
2.1 Installation
The QTrace Analyser application requires the Microsoft .NET framework v4.0 which should be installed
before running the installer (Windows Update routinely installs the latest .NET framework).
The QTrace Analyser should be installed before connecting the QTrace probe to the PC. To launch the
installer, run TraceAnalyserSetup_vx.x.x.x.exe. This will install the QTrace Analyser application, scripts,
documentation and a USB3 driver. Note that the installer will silently request Administrator privileges to
install the driver and the request may fail. If it does, the driver will not be installed and this will have to
be done manually, see Appendix A Manual Driver Installation.
The QTrace probe actually requires two drivers and Windows may try to find an updated driver for one
or both. If it does, click ‘Skip’:
When installation has successfully completed, the QTrace Analyser will run automatically by default. It
can also be run from the Windows Start menu (Start  Programs  PDQLogic  QTrace Analyser).
2.2 QTrace Analyser layout
The application consists of three main areas, a collection of drop-down menus with toolbar shortcuts, a
trace view area with selector tabs and a status bar.
Figure 5 QTrace Analyser layout
Drop-down menus & toolbar
Trace view select
Selected trace view
Status bar
1
2
3