Toshiba CN27E90 Installation guide

COLOR TELEVISION
CN27E90, CX32E70
CN32E90, CN35E15
CF35E50, CX35E60
CX35E70, CX35E81
CN35E90, CN35E95
TECHNICAL TRAINING MANUAL
N5SS (TG-1, C) CHASSIS
NTDCTV05
PRINTED IN JAPAN Aug. 1995 So

2
Contents
SECTION I
OUTLINE......................................................................6
1. OUTLINE OF N5SS CHASSIS (CN32E90, CN35E90) .................................................................... 7
2. PC BOARD CONFIGURATION........................................................................................................ 7
3. MAJOR SPECIFICATIONS (NEW FUNCTIONS IN ADDITION TO THOSE OF N5SS)........ 7
4. MODIFICATIONS ON CHASSIS..................................................................................................... 7
5. CONSTRUCTION OF CHASSIS...................................................................................................... 8
6. LOCATION OF CONTROLS............................................................................................................ 9
7. CN32D90 BLOCK DIAGRAM ......................................................................................................... 13
8. [US, CANADA] SPECIFICATION FOR MODEL's 1995 ............................................................ 14
SECTION II
TUNER, IF/MTS/S.PRO MODULE.........................16
1. CIRCUIT BLOCK ............................................................................................................................. 17
2. TUNER ................................................................................................................................................ 18
3. IF/MTS/S.PRO MODULE................................................................................................................. 19
4. PIP TUNER......................................................................................................................................... 23
SECTION III
CHANNEL SELECTION CIRCUIT........................24
1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM.................................................... 25
2. OPERATION OF CHANNEL SELECTION CIRCUIT ................................................................ 25
3. MICROCOMPUTER......................................................................................................................... 26
4. MICROCOMPUTER TERMINAL FUNCTION ........................................................................... 27
5. EEPROM (QA02) ............................................................................................................................... 29
6. ON SCREEN FUNCTION................................................................................................................. 29
7. SYSTEM BLOCK DIAGRAM .........................................................................................................30
8. LOCAL KEY DETECTION METHOD .......................................................................................... 31
9. REMOTE CONTROL CODE ASSIGNMENT............................................................................... 32
10. ENTERING TO SERVICE MODE................................................................................................ 35
11. TEST SIGNAL SELECTION ......................................................................................................... 35
12. SERVICE ADJUSTMENT .............................................................................................................. 35
13. FAILURE DIAGNOSIS PROCEDURE......................................................................................... 36
14. TROUBLE SHOOTING CHART .................................................................................................. 38
SECTION IV
AUDIO OUTPUT CIRCUIT .....................................41
1. OUTLINE............................................................................................................................................ 42
2. AUDIO OUT IC.................................................................................................................................. 43

3
SECTION V
A/V SWITCHING CIRCUIT ....................................44
1. OUTLINE............................................................................................................................................ 45
2. IN / OUT TERMINALS..................................................................................................................... 45
3. CIRCUIT OPERATION.................................................................................................................... 45
SECTION VI
VIDEO PROCESSING CIRCUIT............................47
1. OUTLINE............................................................................................................................................ 48
2. SIGNAL FLOW.................................................................................................................................. 48
3. CIRCUIT OPERATION.................................................................................................................... 48
SECTION VII
V/C/D/IC......................................................................52
1. OUTLINE............................................................................................................................................ 53
2. LARGE SCALE EMPLOYMENT OF BUS CONTROL OF PARAMETER FOR PICTURE
CONTROLS...................................................................................................................................... 53
3. EMPLOYMENT OF CONTAINING EACH VIDEO BAND FILTER INSIDE.......................... 53
4. EMPLOYMENT OF CONTAINING EACH FILTER (FOR S/H) INSIDE................................. 53
5. LOW COST OF IC ............................................................................................................................ 53
SECTION VIII
PIP MODULE.............................................................55
SECTION IX
SYNC SEPARATION, H-AFC,
H-OSCILLATOR CIRCUITS ..............................58
1. SYNC SEPARATION CIRCUIT ......................................................................................................59
2. H AFC (Automatic Frequency Control) CIRCUIT......................................................................... 60
3. H OSCILLATOR CIRCUIT ............................................................................................................. 61
SECTION X
VERTICAL OUTPUT CIRCUIT .............................63
1. OUTLINE............................................................................................................................................ 64
2. V OUTPUT CIRCUIT ....................................................................................................................... 65

4
SECTION XI
HORIZONTAL DEFLECTION CIRCUIT..............69
1. OUTLINE............................................................................................................................................ 70
2. HORIZONTAL DRIVE CIRCUIT................................................................................................... 70
3. BASIC OPERATION OF HORIZONTAL DRIVE ........................................................................ 71
4. HORIZONTAL OUTPUT CIRCUIT............................................................................................... 74
5. HIGH VOLTAGE GENERATION CIRCUIT................................................................................. 79
6. X-RAY PROTECTION CIRCUIT ................................................................................................... 82
7. OVER CURRENT PROTECTION CIRCUIT................................................................................ 83
8. KINK CORRECTION CIRCUIT..................................................................................................... 84
SECTION XII
DEFLECTION DISTORTION CORRECTION
CIRCUIT (Side DPC Circuit)..............................85
1. DEFLECTION DISTORTION CORRECTION IC (TA8859P) .................................................... 86
2. SIDE DPC............................................................................................................................................ 87
3. DIODE MODULATOR CIRCUIT ................................................................................................... 88
4. ACTUAL CIRCUIT........................................................................................................................... 89
SECTION XIII
CLOSED CAPTION/EDS CIRCUIT .......................92
1. OUTLINE............................................................................................................................................ 93
2. DATA TRANSMISSION FORMAT ................................................................................................ 93
3. DISPLAY FORMAT........................................................................................................................... 94
4. CIRCUIT OPERATION.................................................................................................................... 95
SECTION XIV
POWER CIRCUIT.....................................................98
1. OUTLINE............................................................................................................................................ 99
2. RECTIFYING CIRCUIT AND STANDBY POWER SUPPLY................................................... 100
3. MAIN SUPPLY CIRCUIT............................................................................................................... 100
4. OUTLINE OF CURRENT RESONANT TYPE SUPPLY ........................................................... 101
5. FUNDAMENTAL THEORY........................................................................................................... 101
6. ACTUAL CIRCUIT......................................................................................................................... 102
7. OTHER POWER CIRCUIT ........................................................................................................... 105
8. PROTECTOR MODULE (Z801).................................................................................................... 106

5
SECTION XV
DSP CIRCUIT ..........................................................109
1. ORIGINS OF DOLBY SURROUND ............................................................................................. 110
2. THE DOLBY MP MATRIX............................................................................................................ 110
3. THE DOLBY SURROUND DECODER.........................................................................................111
4. DSP CIRCUIT ...................................................................................................................................111
5. DSP (Digital Surround Processor) IC............................................................................................. 114
6. SURROUND CIRCUIT ................................................................................................................... 116
7. INPUT BALANCE CIRCUIT......................................................................................................... 116
8. MATRIX CIRCUIT ......................................................................................................................... 117
9. FILTER CIRCUIT (ANTI-ALIAS FILTER)................................................................................. 117
10. DSP CIRCUIT (DELAY) ............................................................................................................... 118
11. 7 kHz LOW PASS FILTER ........................................................................................................... 119
12. DOLBY NR CIRCUIT................................................................................................................... 120
13. DSP FRONT ADDITION CIRCUIT............................................................................................ 121
14. BUS CONVERTER ........................................................................................................................ 122
15. NEUTRAL BIAS ............................................................................................................................ 122
16. AUDIO OUTPUT AMPLIFIER (For Rear SP) .......................................................................... 123
17. TROUBLESHOOTING CHART ................................................................................................. 124
SECTION XVI
FAILURE DIAGNOSIS PROCEDURES...............125
1. H STARTING CIRCUIT FAILURE DIAGNOSIS PROCEDURES........................................... 126
2. DEFLECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES......................................... 127
3. LEFT-RIGHT PIN-CUSHION DISTORTION CORRECTION CIRCUIT.............................. 128
4. X-RAY PROTECTION CIRCUIT FAILURE DIAGNOSIS PROCEDURES........................... 129
5. PROTECTION CIRCUIT DIAGNOSIS PROCEDURE ............................................................. 130
6. VIDEO CIRCUIT DIAGNOSIS PROCEDURES......................................................................... 131

6
SECTION I
OUTLINE

7
1. OUTLINE OF N5SS CHASSIS
(CN32E90, CN35E90)
The N5SS chassis is a complete bus control type
chassis where the deflection circuit is controlled by a newly
developed I2C-bus line control system.
2. PC BOARD CONFIGURATION
(1) Signal unit
(2) Power/def unit
(3) A/V, CRT-D, SP-TERM
(4) CCD, comb (CN32E90)
Digital comb (CN35E90)
(5) D.S.P unit
(6) C.C, EDS/R.G.B SW
3. MAJOR SPECIFICATIONS (NEW
FUNCTIONS IN ADDITION TO THOSE
OF N5SS)
(1) EOS (Extended-Data-Service)
(2) Center-Ch-Audio-Input provided
4. MODIFICATIONS ON CHASSIS
(1) Serviceabilityimprovedwithdirect,frontaccesssystem
employed.
(2) One touch cabinet securing (CN32E90) to the chassis.
(3) Improved serviceability with the bus control system
employed for the defection circuits.
(4) Improved serviceability with the white balance bus
control system employed.
(5) Digitalcomb/CCD miniaturized into a socketable size.

8
Fig. 1-1
5. CONSTRUCTION OF CHASSIS
REAR AMP circuit
CONVERTER trans
POWER/DEF circuit
H.OUT
H.OUT trans
DPC circuit
V. OUT
RF SW
A/V circuit
CRT circuit
PIP circuit
CCD circuit
DPC circuit
EDS, RGB SW
circuit
AUDIO OUT
IF/MTS/A-PRO
module
SIGNAL circuit

9
6. LOCATION OF CONTROLS
6-1. TV Set
For specific use of each control, consult the corresponding page numbers in brackets.
Fig. 1-2
POWER
Front View
Press to open
the door
Behind the door
VIDEO/AUDIO IN
jacks <VIDEO 3>
DEMO button
MENU button
CHANNEL buttons
VOLUME
-/+buttons
buttons
ANT/VIDEO button
ADV button
POWER indicato
r
POWER button
Remote sensor

10
Fig. 1-3
Rear view
ANTenna terminals
EXTernal SPEAKER
t
erminals
MAIN SPEAKER
switch
REAR SPEAKER
terminals
S-VIDEO IN jack <VIDEO 1>
VARiable AUDIO OUT
jacks
VIDEO AUDIO OUT
jacks
PIP AUDIO OUT
jacks
VIDEO/AUDIO IN jacks
<VIDEO 2>
VIDEO/AUDIO IN jacks
<VIDEO 1>

11
6-2 Location of Controls (Remote Control)
Only the buttons that are used to operate the TV set are described here.
For details on the use of each control, refer to pages in brackets.
Fig. 1-4
SET UP button
OPTION button
EXIT button
CHANNEL buttons
Aim at the remote sensor on the TV
Learn/Transmit indicator
EDS button
TV/CABLE/VCR/AUX switch
Set to "TV" to control the TV.
TV/VIDEO
Channel Number buttons
PIP function buttons
AUDio button
PICture button
RESET button
ANT 1/2 button
C.CAPT button
CYS/SBS button
Learning buttons
You can use these eight
buttons only as Learning
function buttons.
They are not affected by
Mode selection (TV/CABLE/
VCR/AUX).
To operate buttons inside the cover,
slide the cover down and toward you.
TIMER button
RECALL button
POWER button
MUTE button
VOLUME buttons
RTN buttons
-\+ buttons
FAV -/+ buttons
DSP/SUR button
DSP F/R button
LEAR/USE switch

12
6-3 Monitor Panel
This TV set is equipped with S-VIDEO INPUT jacks,
VIDEO/AUDIO INPUT jacks, VIDEO/AUDIO OUTPUT
jacks, VARIABLE AUDIO OUTPUT jacks, PIP AUDIO
OUTPUT jacks and EXTERNAL SPEAKER terminals for
connecting your desired video/audio equipment.
, , VIDEO 1/VIDEO 2/VIDEO 3 IN Jacks —
provide for direct connection of video devices
(VCR, video disc player, camcorder, etc.) with
video/audio outputs.
,S-VIDEOINJacks—providefordirectS-video
connection from an VCR or a video disc
player. The TV's VIDEO 1/3 audio jacks can
also be used to connect the VCR's audio cables.
VIDEO/AUDIO OUT Jacks --- provide fixed-
level audio and video outputs from whatever is
displayed on the screen.
VARIABLE AUDIO OUT Jacks --- feed
volume-controlled stereo audio out from
whatever is displayed on the screen, allows
connectionofaudioamplifierandletsyouadjust
sound level with TV's remote.
PIP AUDIO OUT Jacks — provide fixed-level
audiooutputsfrom whatever is displayed onthe
PIP window screen.
EXTERNAL SPEAKER Terminals — provide
for direct connection of external speakers.
MAIN SPEAKER Switch — lets you turn off
TV'sbuilt-inspeakers so that sound will instead
come through speakers connected to
EXTERNAL SPEAKER terminals.
REAR SPEAKER Terminals — provide for
direct connection of the supplied Surround
Speakers.
TV Front
TV Rear
10 11 1 2 86
74
935
Fig. 1-5

13
7. CN32D90 BLOCK DIAGRAM

14
8. [US, CANADA] SPECIFICATION FOR MODEL's 1995
CHASSIS C C C C C
MODEL Nbr CN27E90 CX32E70 CN32E90 CE35E15 CF35E50
DERIV
SPECIFICATION HITACHI TDD TDD *TDD *TDD
1 Picture Tube *FST-D/T NF-D/T NF-D/T *FST-D/T FST-D/T
2 Channel Capacity 181ch 181ch 181ch 181ch 181ch
3 C. Caption ●●●●●
4 MTS with dbx ●●●●●
5 Bass, Tre, Balance ●●●●●
6 Sub-Audio-Program ●●●●●
7 Remote band unit *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Unive (36k) *Unive (36k)
8 Picture-in-Picture ●(2TN) ●(2TN) ●(2TN) *●(1TN) ●(1TN)
9 LED Indicators (RED) ●(Power) ●(Power) ●(Power) *●(Power) ●(Power)
10 Local Keys 8key 8key 8key 8key 8key
11 Dolby Surround — — ●——
12 Dig-Sound Processor — — ●(DSP4ch) — —
13 Front Surround ●●—●●
14 Cyclone ABX ●—●——
15 Sub-Bass-System — ●———
16 Audio Output *10Wx2 & 13W 10Wx2 10Wx2 & 10Wx2 10Wx2
13W & 5Wx2
17 Speaker Size & Nbr *80x120x2 70x130x2 80x120x2 70x130x2 70x30x2
& 100R (Hon) 100R & REAR
18 Comb Filter *●(GLS) ●(CCD) ●(CCD) ●(CCD) ●(GLS)
19 Dy-Quadruple Focus — — — — —
20 Scan Velocity Modu ●●●●●
21 Vert Contour Corre ●●●●●
22 Black Level Expand ●●●●●
23 Flesh Tone Correct *●●●●●
24 Dynamic Noise Reduc *●●●●●
25 Picture Preference ●●●●●
26 Horiz Resolution 650 700 700 800 800
27 Parental-Ch Lock ●●●●●
28 Channel Label (32ch) ●●●●●
29 3-Language Display ●●●●●
30 Clock/Off-Timer *●/●●/●●/●●/●●/●
31 Favorite Channel *●*●*●*●*●
32 Extended-Data-Servi *●*●*●*●*●
33 Star-Sight-decoder — — — — —
34 S-Video In-Term ●(1+1) ●(1+1) ●(1+1) ●(1) ●(1)
35 Audio, Video-In/Out 1+2/— 1+2/1 1+2/1 *3/1 3/1
36 Front AV Jack *●●●——
37 Variable Audio Out ●●●●●
38 2-RF Input ●●●——
39 Ext Speaker Term ●●●●●
40 PIP Audio Out Jack — *— *●——
41 Center-Ch-Aud-Input — *●*— — —
42 Speaker-Box -- — ●SS-SR94 — —
43 Others — — — — —
*Cabinet NEW CX32D70 CN32D90 *CE35D10 CF35D50
PARTS SUPPLY (ISO) — — — — —
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CHASSIS C C C C C
MODEL Nbr CX35E60 CX35E70 CX35E81 CN35E90 CN35E95
CONSOLE CINEMA
SPECIFICATION TDD TDD TDD TDD TDD
1 Picture Tube FST-D/T NF-D/T NF-D/T NF-D/T NF-D/T
2 Channel Capacity 181ch 181ch 181ch 181ch 181ch
3 C. Caption ●●●●●
4 MTS with dbx ●●●●●
5 Bass, Tre, Balance ●●●●●
6 Sub-Audio-Program ●●●●*●
7 Remote band unit *A-Univ (42k) *A-Univ (42k) *A-Univ (42k) *Intelig+EZ *Intelig+EZ
8 Picture-in-Picture ●(2TN) ●(2TN) ●(2TN) ●(2TN) ●(2TN)
9 LED Indicators (RED) ●(Power) ●(Power) ●(Power) ●(Power) ●(Power)
10 Local Keys 8key 8key 8key *8key *8key
11 Dolby Surround — — — ●●
12 Dig-Sound Processor — — — ●(DSP4ch) ●(DSP4ch)
13 Front Surround ●●●——
14 Cyclone ABX — — — ●●
15 Sub-Bass-System ●●●——
16 Audio Output 10Wx2 10Wx2 10Wx2 10Wx2 10Wx2
& 13W, 5Wx2 & 13W, 5Wx2
17 Speaker Size & Nbr 70x130x2 70x130x2 70x130x2 80x120x2 & 80x120x2 &
*100R, REAR *120R, REAR
18 Comb Filter ●(DIG) ●(DIG) ●(DIG) ●(DIG) ●(DIG)
19 Dy-Quadruple Focus ●●●●●
20 Scan Velocity Modu ●●●●●
21 Vert Contour Corre ●●●●●
22 Black Level Expand ●●●●●
23 Flesh Tone Correct ●●●●●
24 Dynamic Noise Reduc ●●●●●
25 Picture Preference ●●●●●
26 Horiz Resolution 800 800 800 800 800
27 Parental-Ch Lock ●●●●●
28 Channel Label (32ch) ●●●●●
29 3-Language Display ●●●●●
30 Clock/Off-Timer ●/●●/●●/●●/●●/●
31 Favorite Channel *●*●*●*●*●
32 Extended-Data-Servi *●*●*●*●*●
33 Star-Sight-decoder — — — — —
34 S-Video In-Term ●(1+1) ●(1+1) ●(1+1) ●(1+1) ●(1+1)
35 Audio, Video-In/Out 1+2/1 1+2/1 1+2/1 1+2/1 1+2/1
36 Front AV Jack ●●●●●
37 Variable Audio Out ●●●●●
38 2-RF Input ●●●●●
39 Ext Speaker Term ●●●●●
40 PIP Audio Out Jack — *— *— *●*●
41 Center-Ch-Aud-Input — *●*●*— *—
42 Speaker-Box — — — ●SS-SR94 ●SS-SR94
43 Others — *VCR-Storate — *VCR-Stora
*Cabinet C35D60 CX35D70 NEW (DAX) CN35D90 NEW (BLK)
PARTS SUPPLY (ISO) — — — — —
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16
SECTION II
TUNER, IF/MTS/S.PRO MODULE

17
1. CIRCUIT BLOCK
Fig. 2-1 Block diagram
1-1. Outline
(1) RF signals sent from an antenna are converted into
intermediatefrequencybandsignals(video:45.75MHz,
audio:41.25MHz)inthetuner.(Hereafter,thesesignals
are called IF signals.)
(2) The IF signals are band-limited in passing through a
SAW filter.
(3) The IF signals band-limited are detected in the VIF
circuit to develop video and AFT signals.
(4) The band-limited IF signals are detected in the SIF
circuit and the detected output is demodulated by the
audiomultiplexer,developingRandLchanneloutputs.
These outputs are fed to the A/V switch circuit.
(5) A sound processor (S.PRO.) is provided.
1-2. Major Features
(1) TheVIF/SIFcircuitisfabricatedintoasmallmoduleby
using chip parts considerably.
(2) Asthe tuner,EL466Lthatwhich contains anintegrated
PLL circuit is employed.
(3) Wide band double SAW filter F1802R used.
(4) FS(frequencysynthesizer)typechannelselectionsystem
employed.
(5) VIF/SIF circuit uses PLL sync detection system to
improve performances shown below:
• Telop buzz in video over modulation
• DP, DG characteristics (video high-fidelity
reproduction)
• Cross color characteristic (coloring phenomenon at
color less high frequency signal objects)
(6) HIC SBX1637A-22 is used in the audio multiplexer
circuittominimizethesizewithincreasedperformance.
(7) As a sound control processor, TA1217N is used. I2C-
bus data control the DAC inside the IC to perform
switching of the audio multiplexer modes.
EL466L
Tuner
RF AGC
IF/MTS/S.PRO Module MVUS34S
SIF
output
Sound
Multiplex
Circuit
SAW
Filter VIF/SIF
Circuit S.PRO Circuit
AFT output
TP12
Video output
To A/V switch circuit
TV
R-OUT TV L-OUT
C-IN
R-IN L-IN
R-OUT L-OUT
(L+R)
-OUT
C-OU
T

18
2. TUNER
2-1. Outline
(1) Type name: EL466L
(2) Applicable 181CH
(3) I2C-bus version
(4) PLL-integrated
Fig. 2-2 Tuner terminal layout
Terminal No. Name
1 32V
25V
3 S-CLOCK
4 S-DATA
5 ADDRESS
6 IF OUT
7 BM (9V)
8 RF AGC
9VT
2-2. Operation of the Tuner
2-2-1. Receiver Channels
VHF 2~13CH
UHF 14~69CH 181CH in total
CATV A-6~, J~W, AA~BBB, 65~92, 100~127CH
2-2-2. Terminals (Tuner section)
Name Function
IF OUT IF outputs (P=45.75 MHz, C=42.17 MHz,
S=41.25 MHz)
BM Tuner power supply (9V)
RF AGC Gain control terminal to obtain constant
IF output
VT Control voltage to select channels
2-2-3. Tuner VT Voltage (unit: V)
(1) VHF (2) UHF
CH VT voltage (TYP)
2 1.4
6 6.4
A-2 12.8
B 20.0
C 1.4
I 3.5
10 5.6
J 7.6
N 9.7
R 11.8
W 14.2
FF 17.9
LL 24.2
CH VT voltage (TYP)
MM 1.1
QQ 2.2
WW 4.0
14 5.8
20 7.8
26 9.2
32 10.8
38 12.5
44 13.9
50 15.0
56 17.2
62 19.4
69 23.6
* VT voltage not indicated for a channel falls between
thosevaluesforchannelsjustupperandlowerthechannel.
PLL Selection EL466L
Tuner Section
1 2 3 4 5 6 7 8 9

19
3. IF/MTS/S.PRO MODULE
The IF/MTS/S.PRO module (MVUS34S) limits bandwidth
ofIFsignalsanddetectsvideoandaudiosignals.Themodule
consists of IF amplifiers, SAW (surface acoustic wave)
filter, and PIF IC. The SAW filter has a wideband response
toimprovepicturequalityandaudiobuzzcharacteristicand,
develops separate outputs of video and audio signals. The
PIFICemploys a PLL complete syncdetection+ audio split
carrier system.
3-1. IF/MTS/S.PRO Module (MVUS34S)
3-1-1. Module Terminal Layout
3-1-2 Video PIF Circuit
APIF detector switching carrier isoscillating at a frequency
adjusted to 45.75 MHz with L051 (VCO CW coil) under no
RF signal input. When an RF signal enters, an IF video
carrierisfedtoAPCsectionfromIF AMP inside the IC, and
the detector switching carrier is adjusted by the APC, VCO,
etc. in the PLL circuit so that its frequency and phase are
matched to those of the IF video carrier to perform precise
sync detection. Thus processed video output is developed at
pin 21.
PLL lock speed is automatically controlled by adding the
video signal at pin 21 to pin 1. That is, since the video signal
is not output at operations of power on, CH switching, etc.,
theAPCfilterbetweenpin16andGNDconsistsofC022and
C053,andR018,andthefiltereffectdecreases,thusincreasing
PLL lock speed.
Next,whenavideooutexists,theinternalresistanceisshort-
circuited and the APC filter consists of C022 and C053,
internal resistance, and R018. As a result, the filter effect
increases and the PLL lock speed decreases. Consequently,
undernormalsignalreception,phaseofthedetectorswitching
carrier is locked in a stable condition if an IF video carrier is
lostforashorttimeduetoovermodulation,etc.Bycombining
such a PLL complete sync detection system and a wideband
SAW filter shown in Fig. 2-4, a wideband (4.2 MHz) video
detectionoutputwith less beat interferencewillbeobtained.
3-1-3. Audio PIF Circuit
The IF signal fed through Q003 (Fig. 2-4) enters an audio
section of the SAW filter (Z001) which has an IF bandwidth
for dedicated audio signals, and only the audio signal of
41.25 MHz is fed to pin 7. The signal is sync-detected with
the detection carrier completely synchronized with the IF
video carrier and pin 14 develops a 4.5 MHz SIF signal. By
using the PLL split carrier system just stated, audio signals
withlessbuzzbythevideosignalwillbereproduced.The4.5
MHz SIF enters pin 15 through a 4.5 MHz filter, Z003 and
pin 9 develops a FM-detected audio signal.
Pin No. Name Pin No. Name
1 GND 15 DAC-OUT2
2 IF-IN 16 R-IN
3 NC 17 C-IN
4 +9V 18 L-IN
5 RF AGC 19 GND
6 AFC 20 SCL
7 VIDEO OUT 21 SDA
8 ADR SW 22 W-OUT
9 MPX OUT 23 C-OUT
10 --- 24 L-OUT
11 --- 25 GND
12 TV R-OUT 26 R-OUT
13 DAC-OUT1 27 +9V
14 TV L-OUT
Fig. 2-3 IF/MTS/S.PRO module terminal layout
27 12 91

20
Fig. 2-4 IF/MTS/S. PRO circuit diagram
SIF BANDWIDTH
S
Q002
Q003
IF AMP
GAIN – 14dB
Z001
SAW
FILTER
F1802R
S C P
41.25M 45.75M
VIDEO IF BANDWIDTH
GND IF-IN N.C +B(9V) RF AGC AFC VIDEO OUT ADR SW
M
Z003 4.5MHz SIF SIGNAL
FM DET. COIL
L053
15 11 12
9
7
5
4
2
1
14.
22
13 16 20
21
23
18
17.
SIF LIMIT FM DET.
SIF DET APC
VCD
IF
AMP
AGC
VIDEO
DET.
L051
VCO
CW COIL
R151 TO SOUN
D
MPX IC
L502
AFT COIL
R021 TP12
Q004
Z002
R022
RF AGC
R051
1 2 3 4 5 6 7 8 9
LOCK
CONTROL
-15dB
-6dB
R018
C022
C053
C106