VersaLogic SPX-2 User manual

Reference
Manual
DOC. REV. 4/7/2008
SPX-2
Sixteen-line Digital I/O Serial
Peripheral Expansion (SPX™)
Board

SPX Reference Manual ii
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Contents Copyright © 2013
All Rights Reserved
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties of
merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.
PC/104 and the PC/104 logo are trademarks of the PC/104 Consortium.
MSPX2

SPX Reference Manual iii
Product Release Notes
Rev. 2
Production release.
Rev. 1
Pre-production only. No customer releases.
Support Page
The SPX support page, at http://www.versalogic.com/private/spx2support.asp, contains additional
information and resources for this product including:
Reference Manual (PDF format)
Data sheets and manufacturers’ links for chips used in this product
Utility routines and benchmark software
This is a private page for SPX-2 users that can be accessed only be entering this address directly. It cannot
be reached from the VersaLogic homepage.

SPX Reference Manual iv
Table of Contents
Introduction .....................................................................................................................1
Description..........................................................................................................................1
About SPI...............................................................................................................1
Technical Specifications.....................................................................................................2
RoHS-Compliance..............................................................................................................3
About RoHS...........................................................................................................3
Warnings.............................................................................................................................3
Electrostatic Discharge ..........................................................................................3
Technical Support...............................................................................................................4
Repair Service........................................................................................................4
Physical Details...............................................................................................................5
SPX-2 Board Layout...........................................................................................................5
Hardware Assembly...............................................................................................6
Connector Functions and Interface Cables .........................................................................7
Jumper Summary ................................................................................................................7
J1 Connector Pinout............................................................................................................7
Digital I/O .........................................................................................................................8
Description..........................................................................................................................8
External Connections.............................................................................................8
Digital I/O Port Configuration...............................................................................9
Interrupt Generation...............................................................................................9
Writing to a Digital I/O Port..................................................................................9
Base Board SPI Registers............................................................................................11
SPI Data Registers...............................................................................................13

SPX Reference Manual 1
Introduction
Description
The VersaLogic SPX-2 is a 16-channel digital I/O expansion module designed to be used with
any SPX™ enabled base board. Its features include:
Microchip MCP23S17 16-bit I/O
Expander
Compatible with any SPX
enabled base board
VersaLogic SPX boards are a line of I/O expansion boards using the industry standard Serial
Peripheral Interface (SPI) bus. These are small 1.2” x 3.775” that can mount in either “user
connector” areas of a PC/104-Plus stack using the normal PC/104 stand-offs. They can also
mount up to two feet away from the base board using custom cabling.
SPX boards are electrically connected to a base board via a 14-pin 2mm cable. Up to four boards
can be daisy-chained together. Four is the maximum number of SPI chips that can be driven by
the 14-pin interface. The SPI bus requires each chip to have a discrete chip-select signal, and the
14-pin interface supplies four chip-select signals. The maximum clock rate is 8 MHz.
Power for SPX boards is supplied through the interface cable. I/O connections on SPX boards are
provided through screw terminal/wire connections.
All SPX boards are RoHS compliant and industrial temperature rated.
ABOUT SPI
The SPI bus specifies four logic signals: SCLK – Serial clock (output from master); MOSI –
Master output, slave input (output from master); MISO – Master input, slave output (output from
slave); and SS – Slave select (output from master).
The SPI implementation on VersaLogic CPU boards adds additional features, such as hardware
interrupt input to the master. The master initiates all SPI transactions. A slave device responds
when its slave select is asserted and it receives clock pulses from the master.
Slave selects are controlled in one of two modes: manual or automatic. In automatic mode, the
slave select is asserted by the SPI controller when the most significant data byte is written. This
initiates a transaction to the specified slave device. In manual mode, the slave select is controlled
by the user and any number of data frames can be sent. The user must command the slave select
high to complete the transaction.
The SPI clock rate can be software configured to operate at speeds between 1 MHz and 8 MHz.
All four common SPI modes are supported through the use of clock polarity and clock phase
controls.
1

Introduction
SPX Reference Manual 2
Technical Specifications
Specifications are typical at 25°C with 5.0V supply unless otherwise noted.
Board Size: 1.2" x 3.775", SPX compliant
Storage Temperature: -40° C to 85° C
Free Air Operating Temperature:
-40° C to +85° C
Power Requirements:
+5.0V ± 5% @ 9.0 mA (45 mW) typ.,
155 mA (773 mW) max.
(Interface cable provides 500 mA total, to be
shared by SPX modules)
Digital I/O:
16-channel, ±24 mA outputs
3.3V LVCMOS (not 5V tolerant)
Compatibility:
SPX – Full compliance
(Any 3.3V signaling SPI interface, 8 MHz
maximum clock)
Weight: 0.044 lbs (0.020 kg)
Compliance:
RoHS – Full compliance
Specifications are subject to change without notice.

Introduction
SPX Reference Manual 3
RoHS-Compliance
The SPX-2 is RoHS-compliant.
ABOUT ROHS
In 2003, the European Union issued Directive 2002/95/EC regarding the Restriction of the use of
certain Hazardous Substances (RoHS) in electrical and electronic equipment.
The RoHS directive requires producers of electrical and electronic equipment to reduce to
acceptable levels the presence of six environmentally sensitive substances: lead, mercury,
cadmium, hexavalent chromium, and the presence of polybrominated biphenyls (PBB) and
polybrominated diphenyl ethers (PBDE) flame retardants, in certain electrical and electronic
products sold in the European Union (EU) beginning July 1, 2006.
VersaLogic Corporation is committed to supporting customers with high-quality products and
services meeting the European Union’s RoHS directive.
Warnings
ELECTROSTATIC DISCHARGE
Electrostatic discharge (ESD) can damage boards, disk drives and other components. The circuit
board must only be handled at an ESD workstation. If an approved station is not available, some
measure of protection can be provided by wearing a grounded antistatic wrist strap. Keep all
plastic away from the board, and do not slide the board over any surface.
After removing the board from its protective wrapper, place the board on a grounded, static-free
surface, component side up. Use an antistatic foam pad if available.
The board should also be protected inside a closed metallic anti-static envelope during shipment
or storage.

Introduction
SPX Reference Manual 4
Technical Support
If you are unable to solve a problem with this manual please visit the SPX Product Support web
page listed below. If you have further questions, contact VersaLogic technical support at (541)
485-8575. VersaLogic technical support engineers are also available via e-mail at
[email protected].
REPAIR SERVICE
If your product requires service, you must obtain a Returned Material Authorization (RMA)
number by calling [phone].
Please provide the following information:
Your name, the name of your company and your phone number
The name of a technician or engineer that can be contact if any questions arise.
Quantity of items being returned
The model and serial number (barcode) of each item
A detailed description of the problem
Steps you have taken to resolve or recreate the problem
The return shipping address
Warranty Repair All parts and labor charges are covered, including return shipping
charges for UPS Ground delivery to United States addresses.
Non-warranty Repair All non-warranty repairs are subject to diagnosis and labor charges,
parts charges and return shipping fees. Please specify the shipping
method you prefer and provide a purchase order number for invoicing
the repair.
Note Please mark the RMA number clearly on the outside of the box before
returning. Failure to do so can delay the processing of your return.
SPX Support Website
http://www.versalogic.com/private/spx2support.asp

SPX Reference Manual 5
Physical Details
SPX-2 Board Layout
The figure below shows the dimensions of the SPX-2 board, as well as the location of connectors,
jumpers, and mounting holes.
Figure 1. SPX-2 Board Layout
(Not to scale. All dimensions in inches.)
2
1 5
1 51
1.2”
3.775”
+ +
+
+
3.375”
J1
SPX to Base
Board
J2
DIO J3 DIO
V1
Slave Select
1 0.39”
51
15
J5
DIO
J4
DIO

Physical Details
SPX Reference Manual 6
HARDWARE ASSEMBLY
The SPX-2 mounts on two hardware standoffs using the corner mounting holes. These standoffs
are secured to the board, typically across the PC/104 and PC/104-Plus stack locations, using pan
head screws.
Standoffs and screws are available as part number VL-HDW-101.
Figure 2. SPX Board Mounting
Two SPX boards mounted
across the PC/104 and
PC/104-Plus stack locations

Physical Details
SPX Reference Manual 7
Connector Functions and Interface Cables
The following table shows the function of each connector, as well as mating connectors and
cables.
Table 1: Connector Functions and Interface Cables
Connector Function Mating Connector Transition Cable Cable Description
J1 SPX to Base
Board FCI 89361-714LF or equivalent CBR-1401 CBR-1402 2 SPX Module Cable 4 SPX Module Cable
J2 Digital I/O Bare wires to 5-pin
screw terminal – –
J3 Digital I/O Bare wires to 5-pin
screw terminal – –
J4 Digital I/O Bare wires to 5-pin
screw terminal – –
J5 Digital I/O Bare wires to 5-pin
screw terminal – –
Jumper Summary Table 2: Jumper Summary
Jumper
Block Description As Shipped
V1[1-2] Slave Select 0 In
V1[3-4] Slave Select 1 Out
V1[5-6] Slave Select 2 Out
V1[7-8] Slave Select 3 Out
J1 Connector Pinout Table 3: J1 Connector Pinout
Pin Signal Name Description
1 V5_0 +5.0V
2 SCLK Serial Clock
3 GND Ground
4 MISO Master In Slave Out
5 GND Ground
6 MOSI Master Out Slave In
7 GND Ground
8 SS0# Slave Select 0
9 SS1# Slave Select 1
10 SS2# Slave Select 2
11 SS3# Slave Select 3
12 GND Ground
13 SINT# SPI Interrupt
14 V5_0 +5.0V

SPX Reference Manual 8
Digital I/O
Description
The SPX-2 provides a 16-channel digital I/O interface. The digital lines are grouped as two 8-bit
bi-directional ports. Data direction and output driver type are configurable by software.
Input data can be inverted through register settings. Any I/O pin(s) can generate an interrupt on
change of state. As outputs, the I/O pins drive at 3.3 volt CMOS levels. The SPX-2 I/O inputs are
not 5 volt tolerant. Inputs have external 10k pull-ups to 3.3 volts.
The digital I/O expander communicates with the host computer through the SPX interface.
EXTERNAL CONNECTIONS
Digital I/O channels 0-15 are accessed via connectors J2 through J5 of the SPX-2 as shown in the
following table.
Table 4: Digital I/O Connectors
J2
Pin Signal Name Description
1 GPA0 Digital I/O 0
2 GPA1 Digital I/O 1
3 GPA2 Digital I/O 2
4 GPA3 Digital I/O 3
5 Ground Ground
J3
1 GPA4 Digital I/O 4
2 GPA5 Digital I/O 5
3 GPA6 Digital I/O 6
4 GPA7 Digital I/O 7
5 Ground Ground
J4
1 GPB0 Digital I/O 8
2 GPB1 Digital I/O 9
3 GPB2 Digital I/O 10
4 GPB3 Digital I/O 11
5 Ground Ground
J5
1 GPB4 Digital I/O 12
2 GPB5 Digital I/O 13
3 GPB6 Digital I/O 14
4 GPB7 Digital I/O 15
5 Ground Ground
3

Digital I/O
SPX Reference Manual 9
For more detailed information on the digital I/O expander, refer to the Microchip MCP23S17 I/O
Expander data sheet.
DIGITAL I/O PORT CONFIGURATION
The 16 I/O pins are grouped into two 8-bit sets (GPIOA and GPIOB) within the MCP23S17. See
the Base Board SPI Registers appendix at the end of this document and the Microchip
MCP23S17 data sheet for configuration details. Each pair of I/O ports is configured by a set of
paged I/O registers accessible through SPI. These registers control settings such as signal
direction, input polarity, and interrupt source. The 16 port pins on the SPX-2 use the slave select
configured by the jumper setting at jumper block V1.
INTERRUPT GENERATION
The SPX-2 digital I/O can be configured to issue hardware interrupts on the transition (high to
low or low to high) of any SPX-2 I/O pin. IRQ assignment is made in base board SPI control
register SPISTATUS. Note that this IRQ is shared among all SPI devices on-board and externally
connected to the base board. The IRQ is also shared with the PC/104 bus and must be enabled in
CMOS for ISA IRQx. SPX-2 I/O chip interrupt configuration is achieved through I/O chip
register settings. Please refer to the Microchip MCP23S17 datasheet for more information.
The base board’s (EBX-11 and EBX-22) on-board digital I/O chips must be configured for open-
drain and mirrored interrupts in order for any SPI device to use hardware interrupts. See the base
board’s reference manual for instructions. Note that the SPX-2 interrupts should be configured as
mirrored, but not open-drain.
WRITING TO A DIGITAL I/O PORT
The SPX-2 can take advantage of the EBX-11 Rev 6 and above as well as the EBX-22 Rev 3 and
above data streaming capability. See the MCP23S17 datasheet for information on Sequential
Mode. The following code example initiates a write of 55h to SPX-2 I/O port bits GPA7-GPA0
using the standard 24-bit SPI frame with auto slave select. The SPX-2 is configured for SS0#.
;Write 40h to configure MCP23S17 register IOCON
MOV DX, 1D8h
MOV AL, 21h ;SPICONTROL: SPI Mode 00, 24bit, auto SS0#
OUT DX, AL
MOV DX, 1D9h
MOV AL, 30h ;SPISTATUS: 8MHz, no IRQ, left-shift
OUT DX, AL
MOV DX, 1DBh
MOV AL, 40h ;SPIDATA1: mirror interrupts
OUT DX, AL
MOV DX, 1DCh
MOV AL, 0Ah ;SPIDATA2: MCP23S17 IOCON register address 0Ah
OUT DX, AL
MOV DX, 1DDh
MOV AL, 40h ;SPIDATA3: MCP23S17 write command
OUT DX, AL
CALL BUSY ;Poll busy flag to wait for SPI transaction
;Configure MCP23S17 register IODIRA for outputs
MOV DX, 1DBh
MOV AL, 00h ;SPIDATA1: 00h for outputs
OUT DX, AL
MOV DX, 1DCh

Digital I/O
SPX Reference Manual 10
MOV AL, 00h ;SPIDATA2: MCP23S17 register address 00h
OUT DX, AL
MOV DX, 1DDh
MOV AL, 40h ;SPIDATA3: MCP23S17 write command
OUT DX, AL
CALL BUSY ;Poll busy flag to wait for SPI transaction
;Write 55h to MCP23S17 register GPIOA
MOV DX, 1DBh
MOV AL, 55h ;SPIDATA1: data to write
OUT DX, AL
MOV DX, 1DCh
MOV AL, 14h ;SPIDATA2: MCP23S17 register address 14h
OUT DX, AL
MOV DX, 1DDh
MOV AL, 40h ;SPIDATA3: MCP23S17 write command
OUT DX, AL
CALL BUSY ;Poll busy flag to wait for SPI transaction
BUSY: MOV DX, 1D9h
IN AL, DX ;Get SPISTATUS
AND AL, 01h ;Isolate the BUSY flag
JNZ BUSY ;Loop if SPI transaction not complete

SPX Reference Manual 11
Base Board SPI Registers
The following tables describe the SPI control and data registers of the EBX-11 Rev. 6.00
and later. This is the standard set of SPI registers for VersaLogic CPU boards with an
SPX interface. See the reference manual for details and updates.
SPICONTROL (READ/WRITE) 1D8h
D7 D6 D5 D4 D3 D2 D1 D0
CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0
Table 5: SPI Control Register 1 Bit Assignments
Bit Mnemonic Description
D7 CPOL
SPI Clock Polarity – Sets the SCLK idle state.
0 = SCLK idles low
1 = SCLK idles high
D6 CPHA SPI Clock Phase – Sets the SCLK edge on which valid data will be read.
0 = Data read on rising edge
1 = Data read on falling edge
D5-D4 SPILEN SPI Frame Length – Sets the SPI frame length. This selection works in
manual and auto slave select modes.
SPILEN1 SPILEN0 Frame Length
0 0 8-bit
0 1 16-bit
1 0 24-bit
1 1 32-bit
D3 MAN_SS SPI Manual Slave Select Mode – This bit determines whether the slave select
lines are controlled through the user software or are automatically controlled by
a write operation to SPIDATA3 (1DDh). If MAN_SS = 0, then the slave select
operates automatically; if MAN_SS = 1, then the slave select line is controlled
manually through SPICONTROL bits SS2, SS1, and SS0.
0 = Automatic, default
1 = Manual
D2-D0 SS
SPI Slave Select – These bits select which slave select will be asserted. The
SSx# pin on the base board will be directly controlled by these bits when
MAN_SS = 1.
SS2 SS1 SS0 Slave Select
0 0 0 None, port disabled
0 0 1 SPX Slave Select 0, J17 pin-8
0 1 0 SPX Slave Select 1, J17 pin-9
0 1 1 SPX Slave Select 2, J17 pin-10
1 0 0 SPX Slave Select 3, J17 pin-11
1 0 1 On-Board A/D Converter Slave Select
1 1 0 On-Board Digital I/O Ch 0-Ch 15 Slave Select
1 1 1 On-Board Digital I/O Ch 16-Ch 31 Slave Select
A

Base Board SPI Registers
SPX Reference Manual 12
SPISTATUS (READ/WRITE) 1D9h
D7 D6 D5 D4 D3 D2 D1 D0
IRQSEL1 IRQSEL0 SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY
Table 6: SPI Control Register 2 Bit assignments
Bit Mnemonic Description
D7-D6 IRQSEL IRQ Select – These bits select which IRQ will be asserted when a hardware
interrupt from a connected SPI device occurs. The HW_IRQ_EN bit must be
set to enable SPI IRQ functionality.
IRQSEL1 IRQSEL0 IRQ
0 0 IRQ3
0 1 IRQ4
1 0 IRQ5
1 1 IRQ10
Note: The on-board digital I/O chips must be configured for open-drain and
mirrored interrupts in order for any SPI device to use hardware interrupts.
D5-D4 SPICLK SPI SCLK Frequency – These bits set the SPI clock frequency.
SPICLK1 SPICLK0 Frequency
0 0 1.042 MHz
0 1 2.083 MHz
1 0 4.167 MHz
1 1 8.333 MHz
D3 HW_IRQ_EN Hardware IRQ Enable – Enables or disables the use of the selected IRQ
(IRQSEL) by an SPI device.
0 = SPI IRQ disabled, default
1 = SPI IRQ enabled
Note: The selected IRQ is shared with PC/104 ISA bus devices. CMOS
settings must be configured for the desired ISA IRQ.
D2 LSBIT_1ST SPI Shift Direction – Controls the SPI shift direction of the SPIDATA registers.
The direction can be shifted toward the least significant bit or the most
significant bit.
0 = SPIDATA data is left-shifted (MSbit first), default
1 = SPIDATA data is right-shifted (LSbit first)
D1 HW_INT SPI Device Interrupt State – This bit is a status flag that indicates when the
hardware SPX signal SINT# is asserted.
0 = Hardware interrupt on SINT# is deasserted
1 = Interrupt is present on SINT#
This bit is read-only and is cleared when the SPI device’s interrupt is cleared.
D0 BUSY
SPI Busy Flag – This bit is a status flag that indicates when an SPI
transaction is underway.
0 = SPI bus idle
1 = SCLK is clocking data in and out of the SPIDATA registers
This bit is read-only.

Base Board SPI Registers
SPX Reference Manual 13
SPI DATA REGISTERS
SPIDATA0 (READ/WRITE) 1DAh
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA1 (READ/WRITE) 1DBh
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA2 (READ/WRITE) 1DCh
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA3 (READ/WRITE) 1DDh
D7 D6 D5 D4 D3 D2 D1 D0
MSbit LSbit
SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this
register will initiate the SPI clock and, if the MAN_SS bit = 0, will also assert a slave select to
begin an SPI bus transaction. Increasing frame sizes from 8-bit use the lowest address for the least
significant byte of the SPI data word; for example, the LSB of a 24-bit frame would be
SPIDATA1. Data is sent according to the LSBIT_1ST setting. When LSBIT_1ST = 0, the MSbit
of SPIDATA3 is sent first, and received data will be shifted into the LSbit of the selected frame
size set in the SPILEN field. When LSBIT_1ST = 1, the LSbit of the selected frame size is sent
first, and the received data will be shifted into the MSbit of SPIDATA3.