Xycom XVME 200 User manual

XVME-200/290 Manual
December, 1987
Chapter 1
INTRODUCTION
1.1 OVERVIEW
The XVME-200 and XVME-290 are Digital I/O VMEbus compatible boards (also
referred to as DIO Modules). The XVME-200
is a single-high (3U), single-wide
module, and the XVME-90 is a double-high (6U), single-wide form factored modules.
The DIO Module provides a VME system with 32 digital (TTL) I/O channels, full
VMEbus interrupt capability, and port handshake control features. The DIO Module
utilizes two 68230 Parallel Interface/Timer Integrated Circuit devices (also referred
to as PI/T devices) to provide and control its parallel interface functions (with 16
I/O channels per PI/T device).
In addition, the 68230 devices also provide two 240
bit, software-configurable timers (1 timer per PI/T device), which can be used to
generate periodic interrupts, a single interrupt after a specified time period, or a
square wave. The specific features of the DIO Module are listed below:
Direct compatibility with OPT0 22 -- 24 point subsystems, of either
single or quad density, with no transition interface required
(XVME-290/2).
-- Fully buffered TTL outputs, and hysteresis on TTL Inputs.
Software-configurable port direction
either input or output TTL level data). (i.e., ports may be configured to
Complete VMEbus interrupt capability (I( 1)-I(7) interrupts - STAT).
-- Programmable IACK vector (with vector alteration based on the source of
the interrupt.
Port handshake signals are available to coordinate port data transfers.
TWO 24=bit, software-configurable, timers.
The XVME-200 provides 32 digital I/O channels plus port handshake and timer
control signals through the VMEbus P2 connector. The XVME-290/2 places all
signals on OPT0 22 compatible connectors (JKI and JK2) located in the P2 area.
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XVME-200/290 Manual
December, 1987
1.2 MANUAL STRUCTURE
This manual consists of three chapters which divide the various aspects of module
specification and operation into three distinct areas. The three chapters develop
these aspects in the following progression:
Chapter One
- A general description of the XVME-200/290 Digital I/O Module,
including complete functional and environmental specifications, VMEbus com-
pliance information, and a block diagram.
Chapter Two - DIO Module installation information covering module specific
system requirements, jumpers, and connector pinouts.
Chapter Three - Details covering functional addressing, interrupt enabling, and
programming considerations/requirements.
The Appendices are designed to provide additional information in terms of the
backplane signal/pin descriptions, a block diagram and assembly drawing, and module
schematics.
NOTE
In order to fully document the complex vers-
atility of the XVME-200/290 and the 68230 PI/T
device, a manual kit is being shipped with the
XVME-200/290 DIO Module (the manual kit is
referenced as XYCOM Part #74200-001). This
kit consists of two parts: a *Motorola MC68230
Manual (c) (referenced as XYCOM Part
#74200-003), and an XVME-200/290 Manual
(referenced as XYCOM Part #74200-002.
It is recommended that the user read
(completely) the 68230 Manual prior to reading
further in the XVME-200/290 Manual. After
becoming familiar with the 68230 and how it is
programmed, the user should then read the
remainder of the XVME-200/290 Manual to
become acquainted with module base addressing,
register access offsets, interrupt control,
handshake control, and operational
mode/programming constraints.
* MC68230 Parallel Interface/Timer Manual, (c)Motorola Inc., 1983
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XVME-200/290 Manual
December, 1987
The DIO Module uses two 68230 Parallel Interface/Timer devices to provide a total
of 32 parallel I/O lines (16 lines per chip) arranged as four I/O ports (two 8 line
ports per chip), as well as 2 programmable timers (1 timer per chip). Several
different operating modes can be programmed for the parallel ports and timers, to
provide a high degree of versatility and flexibility.
Each 68230 chip has two (8 line) I/O ports labeled as Port Al and Port Bl for PI/T
#l, and Port A2 and Port B2 for PI/T #2. The third Port on each PI/T chip (Port
C/Alternate Function) is configured as a group of dedicated control lines for
interrupt handling, timer operation, and data port direction.
Each of the four I/O ports is independently buffered by its own 8-bit data
transceiver. The data transceivers are all bidirectional, with their direction being
independently controlled by PC0 and PC1 of the Port D/Alternate Function lines on
each PI/T. The 8 data lines within each of the four PI/T I/O ports Al, A2, Bl,
and B2 must always be programmed for the same direction (i.e., because transceiver
data direction is programmed individually for each port and cannot be done on a
line-by-line basis). In order to avoid signal direction contention between a PI/T
Port and its data transceiver, the direction of the ports and transceivers must be
programmed in the proper order (documented in Chapter 2).
The DIO Module design allows each of the PI/T ports Al, Bl, A2, or B2 to be
individually programmed in either Port Mode 0 or Port Mode 1 (refer to the 68230
Manual for a description of Port Modes). In addition, any of the submodes within
Port Modes 0 and 1 may be utilized. There are 4 buffered handshake lines for each
PI/T chip which (depending on the operation mode selected and the position of
jumpers Jl and J3) can be used to provide interlocked handshake, pulsed handshake,
interrupt input (independent of data transfer), or general purpose single-line I/O.
Each PI/T chip also contains its own 24-bit timer capable of signaling event
occurrence by generating a periodic interrupt, an interrupt after timeout, or a
square wave output. The timer interrupt capability is enabled by using three of the
Port C/Alternate Function pins programmed to carry the Timer Interrupt functions
(i.e., Timer Interrupt enable, Timer input, and Timer output).
The module address decode logic allows the user to select (via 6 jumpers) any one
of 64 of the 1K boundaries in the Short I/O Address Space to be used as the
module base address. The PI/T Internal Registers are accessible at specific
addresses offset from the selected module base address. Any of the 7 VMEbus
interrupt levels may be selected (via 3 jumpers) to facilitate interrupt generation,
and handling from any one of 4 interrupt sources on the module (i.e., PI/T #l port
interrupts, PI/T #2 port interrupts, PI/T #l timer interrupts, and PI/T #2 timer
interrupts). Each of the two PI/T chips is capable of producing 5 different IACK
vectors (one for the timer and four for the ports) for a total of ten different IACK
vectors per module.
On the XVME-200/290 the configuration of the
I/O signals interface to JKl or JK2 (XVME-200,
I/O signals connect to (XVME-290/l), and the
direction of H2, which must be distinct.
PI/Ts differ only in whether their
1XVME-290/2) or which P2 pins the
jumper number which controls the
.
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XVME-200/290 Manual *
December, 1987
1.4 MODULE SPECIFICATIONS
The following is a list of the operational and environmental specifications for the
XVME-200/290 DIO Module.
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XVME-200/290 Manual
December, 1987
Table l-l. Digital I/O Module Specifications
Characteristic Specification
Number of Channels
Parallel Interface Device
Input Characteristics
Output Characteristics
Power Requirements
Board Dimensions
32
68230 (2 per module)
Vil = 0.8V max., Iil = -750 uA max.
Vih = 2.0v min., lil= -325 uA max.
V ol = 0.4V max., Iol = 12 mA
V ol = 0.5V max., Iol = 24 mA
V oh = 2.4V min., Ioh = -3 mA
V oh = 2.0v min., Ioh = -15 mA
+5V, 1.3 A typ., 1.5 A max.
Single-height size (150 x 116.7 mm)(XVME-200)
Double-height size (160 x 233.4 mm)(XVME-290)
Temperature
Operating
Non-Operating
Humidity
Altitude
Operating
Non-Operating
Vibration
Operating
Non-Operating
Shock
Operating
Non-Operating
O” to 32' C (32O to 149OF)
-4OO to 85OC (-40° to 158OF)
5 to 95% RH non-condensing
(Extremely low humidity may require
protection against static discharge.)
Sea-level to 10,000 ft. (3048m)
Sea-level to 50,000 ft. (1524Om)
5 to 2000 Hz
0.015" peak-to-peak displacement
2.5 g peak acceleration
5 to 2000 Hz
0.030” peak-to-peak displacement
5.0 g peak acceleration
30 g peak acceleration
11 msec duration
50 g peak acceleration
11 msec duration
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XVME-200/290 Manual
December, 1987
VMEbus Compliance Complies with VMEbus Standard Rev. C.l
A 16:D8(0) DTB Slave
I(1) to I(7) interrupter (STAT) with
programmable interrupt vector
Size - Single (XVME-200
Size - Double (XVME-290)
Base address jumper-selectable on 1K
boundaries within the VMEbus short I/O
address space
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XVME-200/290 Manual
December, 1987
Chapter 2
INSTALLATION
2.1 INTRODUCTION
This chapter explains how to configure the XVME-200/290 DIO Module prior to
installation in a VMEbus backplane. Included in this chapter is information on
module base address selection jumpers, module interrupt level selection jumpers, the
handshake line H2 direction jumpers, connector pinouts, and a brief outline of the
physical installation procedure.
2.2 SYSTEM REQUIREMENTS
The XVME-200/290 DIO Modules are VMEbus compatible modules. To operate, they
must be properly installed in a VMEbus backplane.
The minimum system requirements for the operation of an XVME-200/290 DIO
Modules are one of the following:
A host processor module properly installed on the same backplane as the
XVME-200/290; and a controller subsystem module which employs a Data
Transfer Bus Arbiter, a System Clock driver, a System Reset driver, and a
Bus timeout module. (The XYCOM XVME-010 System Resource Module
provides a controller subsystem with the components listed.)
-- OR --
A host processor module which incorporates an on-board controller sub-
system (such as XYCOM’s XVME-600 or XVME-601).
Prior to installing the XVME-200/290 DIO Modules, it will be necessary to configure
several jumper options. These options are:
1) Module base address within the short I/O address space.
2) Address Modifier codes to which the DIO Module will respond.
3) Interrupt level.
4) Direction of handshake line H2 on the 68230 PI/T chip.
2.3 XVME-200/290 DIO MODULE JUMPER/CONNECTOR LOCATIONS
The jumpers and connectors relevant to the installation of the XVME-200 DIO
Module are shown in Figure 2-1, and the jumpers and connectors relevant to the
installation of the XVME-290/2 DIO Module are shown in Figure 2-2, and Figure 2-3
shows the XVME-290/l.
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XVME-200/290 Manual
December, 1987
2.4 XVME-200/290 DIO MODULE JUMPER LIST
Table 2-1. DIO Module Jumper List
Jumper Use
Jl and J3 Determine the direction of handshake line H2 for both of the
PI/T chips (refer to Section 2.4.5 of this manual).
J2 Determines whether the module will respond to supervisory or
non-privileged short I/O VMEbus cycles (refer to Section 2.4.2
of this manual).
JAl0-JAI5 Select module base address on any one of the 64 1K boundaries
within the short I/O address space (refer to Section 2.4.1 of
this manual).
JA1-JA3 Select the VMEbus interrupt level for the module (refer to
Section 2.4.3 of this manual).
2.4.1 Base Address Jumpers
The DIO Module can be configured to be addressed at any one of the 64 IK
boundaries within the VME Short I/O Address space by using jumpers JAI0 through
JA15 (see Figure 2-1 (XVME-200), or Figure 2-2 (XVME-290) for the location of the
jumpers on the board) as shown below:
Table 2-2. Base Address Jumper Options
JA15 JA14 JA13 JA12 JAI1 JAI0 Base Address of
Module
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OOOOH
0400H
0800H
OCOOH
1OOOH
1400H
1800H
1COOH
2000H
2400H
2800H
2COOH
3000H
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XVME-200/290 Manual
December, 1987
Table 2-2. Base Address Jumper Options (Cont’d)
JA15 JA14 JA13 JA12 JAll JAlO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
2-6
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
Base Address of
Module
3400H
3800H
3COOH
4000H
4400H
4800H
4COOH
5000H
5400H
5800H
5COOH
6OOOH
6400H
6800H
6COOH
7000H
7400H
7800H
7COOH
8OOOH
8400H
8800H
8COOH
9000H
9400H
9800H
9COOH
AOOOH
A400H
A800H
ACOOH
BOOOH
B400H
B800H
BCOOH
COOOH
C4OOH
C8OOH
CCOOH
DOOOH
D400H
D800H
DCOOH
EOOOH
E400H

XVME-200/290 Manual
December, 1987
Table 2-2. Base Address Jumper Options (Cont’d)
JA15 JA14 JAI3 JA12 JAI1 JAI0 Base Address of Module
OUT OUT OUT
IN OUT IN E800H
OUT OUT OUT IN OUT OUT
EC00H
OUT
OUT OUT OUT IN IN F000H
OUT OUT OUT OUT IN OUT
F400H
OUT OUT OUT OUT OUT
IN F8OOH
OUT OUT
OUT OUT OUT OUT FC00H
2.4.2 Address Modifier Jumper
The DIO Module has one jumper that determines which Address Modifier Codes it
will respond to. This jumper is labeled as J2 (see Figure 2-1 for the jumper
location). Jumper J2 determines whether the module will respond to supervisory or
to non-privileged short I/O VMEbus cycles. When jumper J2 is in, the module will
respond to supervisory short I/O bus cycles only. When jumper J2 is out, the
module will respond to both non-privileged and supervisory short I/O bus cycles.
Table 2-3 shows the relationship between jumper J2 and the Address Modifiers.
Table 2-3. Addressing Options
Jumper J2 Address Modifier that the DIO Module will respond to
In
out (2DH) Supervisory Only (2DH) Supervisory or (29H) Non-privileged
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XVME-200/290 Manual
December, 1987
2.4.3 Interrupt Level Selection Jumpers
The DIO Module can either be configured to generate VMEbus interrupts at levels
1-7 or the module interrupt capability can be completely disabled. Table 2-4 shows
how jumpers JAI-JA3 are used to determine the interrupt level status for the DIO
Module.
Table 2-4. Interrupt Level Jumper Positions
JA3
In
In
In
In
Out
Out
Out
Out
JA2
In
In
Out
Out
In
In
Out
Out
JAl
In
Out
IN
Out
In
Out
In
Out
Interrupt Level Selected
None, VMEbus Interrupter disabled
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
The modules are shipped from the factory with jumpers JAI, JA2, and JA3 installed.
NOTE
When the module is never required to generate interrupts,
JAl, JA2, and JA3 should all be installed to ensure that a
programming bug will not generate a VMEbus interrupt.
2.4.4 BGIN*/BGOUT*-IACKIN*/IACKOUT* Daisy Chain
The Data Bus Arbitration signals BGIN*/BGOUT* are not used by the DIO Module
and are hardwired together on the module to allow the Bus Arbitration Daisy Chain
to pass through the backplane slot occupied by the DIO Module. In each slot of
the VMEbus backplane there are set of jumpers which short the “IN” lines to the
“OUT” lines. Since the BGIN*/BGOUT* signals are already hardwired on the DIO
Module, it is not necessary to insert the corresponding jumper on the slot occupied
by the DIO Module. However, the IACKIN*/IACKOUT* signals are used by the DIO
Module and thus, the backplane jumper for these signals must not be installed in
the backplane slot occupied by the DIO Module.
2.4.5 Handshake Line H2 Direction Jumpers
The 68230 PI/T chips on the DIO Module can be programmed to operate in Modes 0
and 1 (refer to the 68230 Manual for mode explanation). Data transfers in these
modes can be controlled via the four handshake pins on each chip. These
handshake pins are designed to be used in any of several different programmable
protocols (a thorough understanding of Modes 0 and 1, and their associated
submodes presented in the 68230 Manual is necessary in order to fully understand
the variety of protocols).
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