Aeroflex GR-UT699 User manual

GR-UT699
Development Board
User Manual
AEROFLEX GAI LER AB
Rev. 0.6, 2013-03-28

2 GR-UT699 Development Board
User Manual
nformation furnished by Aeroflex Gaisler AB is believed to be accurate and reliable.
However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements
of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Aeroflex
Gaisler AB.
Aeroflex Gaisler AB tel [phone]
Kungsgatan 12 fax [phone]
411 19 Göteborg [email protected]
Sweden www.aeroflex.com/gaisler
Copyright © 2013 Aeroflex Gaisler
All information is provided as is. There is no warranty that it is correct or suitable for any purpose,
neither implicit nor explicit.
© Aeroflex Gaisler AB March 2013, Rev. 0.6

3 GR-UT699 Development Board
User Manual
TABLE OF CONTENT
1 INTRODUCTION...........................................................................................................7
1.1 Overview......................................................................................................................7
1.2 References...................................................................................................................9
1.3 Handling....................................................................................................................... 9
1.4 Abbreviations.............................................................................................................10
2 ELECTRICAL DE IGN...............................................................................................11
2.1 Block Diagram............................................................................................................11
2.2 UT699 AS C............................................................................................................... 11
2.3 Memory...................................................................................................................... 12
2.3.1 SRAM.........................................................................................................................13
2.3.2 FLASH.......................................................................................................................13
2.3.3 EEPROM....................................................................................................................13
2.3.4 MEMORY EXPANS ON CONNECTOR.....................................................................13
2.4 CAN nterface............................................................................................................14
2.4.1 Configuration of Bus Termination...............................................................................14
2.4.2 Configuration of Slew Rate.........................................................................................15
2.5 Spacewire (LVDS) nterfaces.....................................................................................15
2.5.1 SPW interface circuit..................................................................................................15
2.5.2 SPWCLK....................................................................................................................16
2.6 Serial nterface...........................................................................................................17
2.7 Debug Support Unit (DSU) Serial nterface................................................................17
2.8 Oscillators and Clock nputs.......................................................................................19
2.8.1 System Clock.............................................................................................................19
2.8.2 SPW_CLK..................................................................................................................19
2.8.3 Ethernet Clock............................................................................................................19
2.8.4 PC Clock...................................................................................................................20
2.9 Power Supply and Voltage Regulation......................................................................20
2.10 Ethernet nterface......................................................................................................20
2.11 PC nterface..............................................................................................................21
2.11.1 Host/System Slot Configuration.................................................................................22
2.11.2 Peripheral Slot Configuration.....................................................................................23
2.12 Other nterfaces and Circuits.....................................................................................24
2.12.1 GP O..........................................................................................................................24
2.12.2 Reset Circuit and Button............................................................................................24
2.12.3 Watchdog...................................................................................................................25
2.12.4 JTAG interface...........................................................................................................25
2.12.5 Mezzanine/Memory Expansion...................................................................................25
3 ETTING UP AND U ING THE BOARD...................................................................27
4 INTERFACE AND CONFIGURATION.....................................................................32
4.1 List of Front/Back Panel Connectors..........................................................................32
4.2 List of Oscillators, Switches and LED's......................................................................42
4.3 List of Jumpers...........................................................................................................43
© Aeroflex Gaisler AB March 2013, Rev. 0.6

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LI T OF TABLE
Table 3-1: Default Status of Jumpers/Switches..............................................................................27
Table 4-1: List of Connectors.........................................................................................................32
Table 4-2: J1 UART-1 - Serial nterface (RS232) connections .....................................................34
Table 4-3: J2 RJ45-ETHERNET Connector...................................................................................34
Table 4-4: J3 AS C– JTAG Connector ..........................................................................................34
Table 4-5: J4A (upper connector) CANBUS-1 interface connections............................................35
Table 4-6: J4B (lower connector) CANBUS-0 interface connections..............................................35
Table 4-7: J5 SPW-0 interface connections .................................................................................35
Table 4-8: J6 SPW-1 interface connections .................................................................................36
Table 4-9: J7 SPW-2 interface connections .................................................................................36
Table 4-10: J8 SPW-3 interface connections................................................................................36
Table 4-11: Expansion connector J9 Pin-out (see section 2.12.5 for pin order).............................38
Table 4-12: J10 P O Header Pin out..............................................................................................38
Table 4-13: Expansion connector J11 Pin-out (see section 2.12.5 for pin order)..........................39
Table 4-14: J12 DSU-Serial over USB MiniAB...............................................................................40
Table 4-15: J13 POWER – External Power Connector..................................................................40
Table 4-16: J14 POWER – External Power Connector..................................................................40
Table 4-17: SOD MM socket J15 Pin-out.......................................................................................42
Table 4-18: List and definition of Oscillators..................................................................................42
Table 4-19: List and definition of PCB mounted LED's...................................................................42
Table 4-20: List and definition of Switches.....................................................................................42
Table 4-21: D P Switch S3 'P O[7..0]' definition.............................................................................42
Table 4-22: D P Switch S4 'P O[15..8]' definition............................................................................43
Table 4-23: List and definition of PCB Jumpers.............................................................................43
© Aeroflex Gaisler AB March 2013, Rev. 0.6

5 GR-UT699 Development Board
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LI T OF FIGURE
Figure 1-1: GR-UT699 Development Board.....................................................................................8
Figure 2-1: Block Diagram of GR-UT699 board.............................................................................11
Figure 2-2: UT699 AS C................................................................................................................. 12
Figure 2-3: On-Board Memory Configuration.................................................................................13
Figure 2-4: Block Diagram of the CAN interface............................................................................14
Figure 2-5: Transceiver and Termination Configuration (one of 2 interfaces shown).....................15
Figure 2-6: Transceiver and Termination of the SPW interfaces (2 of 4 interfaces shown)............16
Figure 2-7: Serial interface............................................................................................................. 17
Figure 2-8: Debug Support Unit connections.................................................................................17
Figure 2-9: Clock Distribution Scheme...........................................................................................19
Figure 2-10: Power Regulation Configuration.................................................................................20
Figure 2-11: Block diagram of Ethernet nterface...........................................................................21
Figure 2-12: Block diagram for PC System Slot connections........................................................22
Figure 2-13: Block diagram of PC Peripheral connections............................................................23
Figure 2-14: P O interface.............................................................................................................. 24
Figure 2-15: Watchdog configuration.............................................................................................25
Figure 2-16: Mezzanine Connector Pin Number Ordering..............................................................26
Figure 3-1: GRMON Output Screenshot #1...................................................................................29
Figure 3-2: GRMON Output Screenshot #2...................................................................................31
Figure 4-1: Front Panel View (pin 1 of connectors marked)...........................................................33
Figure 4-2: PCB Top View..............................................................................................................44
Figure 4-3: GR-UT699 Assembly Photo.........................................................................................45
REVI ION HI TORY
Revision Date Page Description
0.1 DRAFT 2008-05-01 All New document/draft
0.2 2008-09-16 §2.5.2
§2.12.1
18
41
Added note about SPWCLK oscillator
Added notes about PC _ NT[A B C D] signals
Modified Figure 2-9
Updated Figure 4-2.
0.3 2008-10-27 All Formatting changes
0.4 2009-01-07 7,28,29,
41,42
Updated Figure 1-1, Figure 3-1, Figure 3-2, Figure 4-2, Figure 4-3
0.5 2012-12-10 §1.2
§2.3.4
§2.12.15
Added a link to reference document about Mezzanine Connectors
Added description of Mezzanine connectors and pin numbering
0.6 2013-03-28 §2.11.1,
§2.11.2
§3
Corrected references to JP8 / JP10 in PC jumper configurations
Added paragraph explaining grmon command for using Digilent HS-1 JTAG
cable.
© Aeroflex Gaisler AB March 2013, Rev. 0.6

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ntentionally Blank
© Aeroflex Gaisler AB March 2013, Rev. 0.6

7 GR-UT699 Development Board
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1 INTRODUCTION
1.1 Overview
This document describes the GR-UT699 Development Board.
The purpose of this equipment is to provide developers with a convenient hardware platform
for the evaluation and development of software for the Aeroflex UT699RH RadHard 32-bit
Fa lt-Tolerant LEON 3FT/SPARCTM V8 Processor AS C device. The UT699 is a Leon3FT
based custom AS C for Aerospace applications.
The GR-UT699 Unit comprises a custom designed PCB with a 6U Compact PC front panel,
making the board suitable either for stand-alone bench top development, or for installation in
a 6U High Compact PC rack. All the principle interfaces and functions are accessible on
front panel connectors.
The interface connectors on the Front Panel of the unit provide:
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 1-1: GR-UT699 Development Board

8 GR-UT699 Development Board
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•One Serial UART interface (RS232)
•Ethernet
•JTAG - DSU
•Two CAN bus interfaces
•Four Spacewire interfaces
•Serial DSU UART (Mini-AB USB connector)
•16 pins General Purpose /O Port
•Push Buttons for RESET and BREAK
•LED indicators
To enable convenient connection to the interfaces, the connector types and pin-outs are
compatible with the standard connector types for these types of interfaces.
Additionally the board is equipped with a 32 bit Master/target PC interface via standard
Compact PC Connector interface on the back edge of the PCB.
The PCB contains the following main items as detailed in section 2 of this document:
•UT699RH AS C
•Memory
•SRAM 80 Mbit (1 banks x 2Mword x 40 bit, typ. 10ns)
(optional second bank is not fitted as standard)
•SDRAM SOD MM socket (up to 64Mword x 40 bit with 512Mbyte module)
•FLASH 128Mbit (4M x 32 bit, typ. 90ns)
•EEPROM D L32 socket (1 bank x 1Mbit, organised x8 bit wide)
•additional memory via memory expansion connector
•nterfaces
•two CAN interfaces
•four Spacewire LVDS electrical interfaces
•one serial UART (RS232) interface
•10/100MBit Ethernet PHY
•DSU - Serial (over USB Converter) interface
•DSU - JTAG (over JTAG connector) interface
•GP O (16 signals) general purpose input/output port
•Power, Reset, Clock and Auxiliary circuits
1.2 References
RD-1 GR-UT699_schematic.pdf, Schematic
RD-2 GR-UT699_assy_drawing.pdf, Assembly Drawing
RD-3 UT699RH Datasheet
RD-4 GR-MEZZ Technical Note, Technical Note about Mezzanine connectors
© Aeroflex Gaisler AB March 2013, Rev. 0.6

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1.3 Handling
ATTENTION : OB ERVE PRECAUTION FOR
HANDLING ELECTRO TATIC EN ITIVE DEVICE
This unit contains sensitive electronic components which can be damaged by Electrostatic
Discharges (ESD). When handling or installing the unit observe appropriate precautions and
ESD safe practices.
When not in use, store the unit in an electrostatic protective container or bag.
When configuring the jumpers on the board, or connecting/disconnecting cables, ensure that
the unit is in an unpowered state.
1.4 Abbreviations
D L Dual n-Line
ESD Electro-Static Discharge
FP Front Panel
FT Fault-Tolerant
GP O General Purpose nput / Output
/O nput/Output
P ntellectual Property
LVDS Low Voltage Digital Signalling
M Media ndependent nterface
MUX Multiplexer
PCB Printed Circuit Board
SPW Spacewire
© Aeroflex Gaisler AB March 2013, Rev. 0.6

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2 ELECTRICAL DE IGN
2.1 Block Diagram
The GR-UT699 board provides the electrical functions and interfaces as represented in the
block diagram, Figure 2-1.
Figure 2-1: Block Diagram of GR-UT699 board
The Main PCB is of standard Double Eurocard format (233.35 x 160mm) and, in principle,
could be used 'stand-alone' on the bench-top simply using an external +5V power supply.
The board is fitted with a Compact PC front panel, and is compatible with mounting in a 6U
Compact PC rack.
2.2 UT699 A IC
The UT699RH ASC is packaged in a 352-pin Ceramic Quad Flatpack, and is soldered in to
the PCB.
Details of the interfaces, operation and programming of the UT699 AS C is given in the
UT699 Datasheet, RD-3.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
UT699RH
A IC
SPW ETHER-
NET PHY
CANBUS
SER AL
DSU
UART
RS232
MEMORY
EXPANS ON
POWER
&
AUX
FLASH
EEPROM
SDRAM
SRAM
GP O /F
POWER
16 x GP O USB-
SER AL
2 x CAN 4 x SPW 10/100 Mb
ETHERNET
1 x RS232
UART
D P
SW TCHES
COMPACT PC
NTERFACE

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2.3 Memory
The memory configuration installed on the board is shown in the figure below comprising of:
•80Mbit of SRAM memory, organised as 1 banks x 2Mword x 40 bits wide
(a second SRAM bank can be installed on the PCB, but is not fitted as standard)
•128Mbit of Flash PROM, organised as 1 bank x 4 Mword x 32 bits wide)
•D L 32 pin socket to allow 1Mbit of EEPROM organised as 1 bank x 128kByte x 8
bits wide) to be installed
Additionally, in order to allow users to install alternative memory configurations or devices, all
the signals of the memory interface are connected to memory expansion connectors. The
expansion connectors allow mezzanine boards to be added similar to those developed for
the existing GR-CPCI development boards.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-2: UT699 AS C
Figure 2-3: On-Board Memory Configuration
SRAM
SRAM
UT699RH
A IC
UT699RH
A IC
SRAM
SRAM
SRAM
32
ADDR
BANK0
DATA
FLASH
FLASH
8
EEPROM
EEPROM SRAM
(32+8)
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM BANK1
MEMORY EXPANS ON CONNECTOR
CONTROL
ROMSN0 RAMSN0
RAMSN1

12 GR-UT699 Development Board
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2.3.1 RAM
The GR-UT699 board is laid out with two SRAM memory banks but only has one bank
mounted as standard. Each bank is made up of five CY7C1069AV33. These devices are
16Mbit (2Mbyte x 8 bit devices with 10 or 12 ns access times.
The five devices provide (32 + 8) bit wide SRAM memory paths allowing EDAC operation.
These memory banks are mapped as RAMBANK0 and RAMBANK1.
n case the user wishes to disable the on board memory, this can be done by removing the
jumpers JP5 on the PCB.
2.3.2 FLA H
The GR-UT699 board has mounted as standard one FLASH memory bank, made up of two
ntel JS28F640J3 FLASH devices. These devices are 64Mbit (8Mbyte x 16 bit devices),
typically with 90ns access times. The data bus width to the Flash memory is 32 bits wide.
Note that, the PROM width and PROM EDAC conditions are set by the state of the
GP O[2..0] pins at power up of the Processor. Therefore the GP O[2..0] D P switches on the
PCB must be appropriately set for the correct operation of the PROM memory at start up of
the processor. For information on the GP O[2..0] settings refer to the Memory Configuration
documentation in the Leon3 User Manual, or RD-3.
2.3.3 EEPROM
The GR-UT699 board additionally has a D P32 socket suitable for mounting an EEPROM
device. The data bus width to the EEPROM device is 8 bits wide.
This socket is suitable for mounting an EEPROM device of the type AT28LV010, or
compatible, in D P32 package. The AT28LV010 is an ATMEL EEPROM, of 1Mbit capacity
organised as 128kByte x 8 bits.
Jumpers are provided to enable the user to select either the FLASH PROM device or the
EEPROM to operate as the ROMBANK0 device which appears at the initial memory location
of 0x00000000.
2.3.4 MEMORY EXPAN ION CONNECTOR
Access to the memory signals is provided by the connectors J9 and J11. This enables uses
to conceive their own mezzanine boards and functions. Please see section.2.12.5
2.4 CAN Interface
The board provides the electrical interfaces for two CAN bus interfaces, as represented in
the block diagram, Figure 2-4.
The CAN bus transceiver C's on this board are SN65HVD230 devices from Texas
nstruments which operate from a single +3.3V power supply.
The connector interfaces are male DSUB-9 connectors adhering to the standard pin-out for
this type of interface (ref. Table 4-6 And Table 4-5).
© Aeroflex Gaisler AB March 2013, Rev. 0.6

13 GR-UT699 Development Board
User Manual
2.4.1 Configuration of Bus Termination
The CAN interfaces on the board can be configured for either end node or stub-node
operation by means of the jumpers JP3 and JP4 for interface 1 and 2 respectively, as shown
in Figure 2-5.
For normal end-node termination with a nominal 120 Ohm insert jumpers in position 1-3.
However, if a split termination is desired (if required for improved EMC performance), insert
the jumpers in positions 1-2 and 3-4.
For stub nodes, if termination is not required, do not install any jumpers.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-4: Block Diagram of the CAN interface
CAN
TRANSCE VER
CAN
TRANSCE VER
CAN_H
CAN_L
TXD
RXD
CAN
interface 1
CAN
TRANSCE VER
CAN
TRANSCE VER
CAN_H
CAN_L
TXD
RXD
CAN
interface 2
CONTROLLER LOG C N AS C

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2.4.2 Configuration of lew Rate
The SN65HVD230 transceiver device used on the board has the facility to set the device into
STANDBY mode, by connecting an active high external signal to pin 8 of the device (refer to
the device data sheet). However, on this board this is tied to permanently 'low' to enable the
CAN bus Transceivers.
A further feature provided by the SN65HVD230 device is the capability to adjust the
transceiver slew rate. This can be done by modifying the values of resistors connected to pin
8 of the transceivers.
The default value of 0 ohms is compatible with 1Mbps operation.
From the data sheet the following resistor values give the following slew rates:
10kOhm => 15V/us
100kOhm => 2V/us
2.5 pacewire (LVD ) Interfaces
The UT699 AS C provides four Spacewire interfaces which are routed to the front panel of
the board.
2.5.1 PW interface circuit
Each Spacewire interface consists of 4 LVDS differential pairs (2 input pairs and 2 output
pairs), as shown in the figure below. As the Spacewire interface to the UT699 AS C is
LVTTL (3.3V logic), LVDS driver and receiver circuits are required on the PCB to interface
between the AS C and the external interface.
The PCB traces for the LVDS signals on the GR-UT699 board are laid out with 100-Ohm
differential impedance design rules and matched trace lengths.
100 Ohm Termination resistors for the LVDS receiver signals are mounted on the board
close to the receiver.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-5: Transceiver and Termination Configuration (one of 2 interfaces shown)

15 GR-UT699 Development Board
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The pin out and connector types for these Spacewire interfaces conform to the Spacewire
standard, as shown in Figure 2-6.
The inner shield pin (pin3 of the connector) is connected to DGND via a Zero-ohm resistor.
2.5.2 PWCLK
Configuration options on the board (jumpers, crystal socket and SMA coaxial connector)
allow this Spacewire clock to be provided from the following sources:
•Dedicated SPWCLK oscillator (if appropriate Oscillator X3 is mounted in socket and
jumper J17 is not installed)
•Main processor oscillator X1(if jumper J17 is installed)
•External clock input via SMA connector J16. (X3 and J17 not installed)
The default configuration is that the clock is supplied by the SPWCLK oscillator X3, and
jumper J17 is not installed. Do not install jumper J17 if an oscillator is installed in X3 socket
as this will unintentionally connect the outputs of oscillator X1 and Oscillator X3 together.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-6: Transceiver and Termination of the SPW interfaces (2 of 4 interfaces shown)

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2.6 erial Interface
The UT699RH AS C, provides a single Serial port, with TXD/RXD pins, and the GR-UT699
board provides an RS232 driver/receiver chip and routes these signals to a front panel
connector.
The front panel connector type for the UART interface is Female D-Sub 9 pin type with a
standard pin-out for serial links.
2.7 Debug upport Unit (D U) erial Interface
The GR-UT699 unit provides a interface for Debug and control of the processor by means of
a host terminal via the DSU serial link to the UT699 AS C, as represented in Figure 2-8.
The board provides two possibilities for connecting to the processor's DSU interface:
1. USB MiniAB connector with USB to Serial interface chip
2. JTAG DSU interface
The baud rate of the serial link is specified by the host computer, and the DSU interface in
the UT699 AS C auto-detects and adjusts its baud rate to suit.
The DSUENable signal input to the processor is connected to a jumper on the PCB. n
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-8: Debug Support Unit connections
Figure 2-7: Serial interface
UT699RH
A IC
DSUTX←
DSURX→
DSUBRE→
DSUACT←
DSUEN→
DSU /F
HOST
TERM NAL/COMPUTER
USB-SER AL
JTAG
USB to SER AL
CONVERTER
UT699RH
A IC
RS232
NTERFACE
SUB-D 9 pin
Female
RS232
DR VER/
RECE VERS
TXD
RXD

17 GR-UT699 Development Board
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normal use the DSU feature will always be enabled to allow processor control and program
debugging via the DSU link.
An LED is provided on the PCB to indicate the conditions of the DSUACT signal from the
UT699 processor. Additionally connections are provided to an LED indicator on the front
panel of the Unit.
A miniature push button switch is provided on the Main PCB for the DSUBREAK control, and
connections are provided to an additional push-button switch on the front panel of the unit.
© Aeroflex Gaisler AB March 2013, Rev. 0.6

18 GR-UT699 Development Board
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2.8 Oscillators and Clock Inputs
The oscillator and clock scheme for the UT699 AS C is shown in Figure 2-9.
2.8.1 ystem Clock
The main oscillator for the UT699 AS C is a 75 MHz Crystal oscillator. This oscillator will be
a 4 pin D L8 style oscillator, installed in a socket on the board. A zero-delay buffer circuit
(CY2305) is used to distribute the SYSCLK.
2.8.2 PW_CLK
The SPWCLK can be derived from either the SYSCLK, a separate socketed on-board crystal
oscillator, or can be injected on a coaxial connector on the board.
2.8.3 Ethernet Clock
A dedicated 25MHz SMD oscillator is provided for the Ethernet Controller and PHY circuit
(see section 2.10).
2.8.4 PCI Clock
A dedicated 33.3MHz SMD oscillator and zero delay buffer are provided for the PC clock.
For information on the configuration, please see section 2.11.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-9: Clock Distribution Scheme
SPW CLK
SMD
ZERO
DELAY
BUFFER
ZERO
DELAY
BUFFER
UT699RH
AS C
PC _CLK
TBD MHz
TBD MHz ZERO
DELAY
BUFFER
ZERO
DELAY
BUFFER
D L8 SOCKET
TBD MHz
TBD MHz
COAX CONNECTOR
D L8 SOCKET
COAX CONNECTOR
MEMORY EXPANS ON
CONNECTOR
MEMORY EXPANS ON
CONNECTOR
SDCLK
SYS CLK
33.3 MHz
33.3 MHz
SDRAM
MODULE
SDRAM
MODULE
SMD
Ethernet
PHY
Ethernet
PHY
ETH_TXCLK
ETH_RXCLK
25 MHz
25 MHz
SDRAM
MODULE
PC Backplane

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2.9 Power upply and Voltage Regulation
The board operates from a single +5V DC power supply input. On board regulators generate
the following voltages:
•+3.3V for the UT699 /O voltage, memory chip and other peripherals
•+2.5V for UT699 Vcore voltage
All voltages +5V, +3.3V, ±12V are provided via the memory expansion connector interface
making feasible that user defined mezzanine boards can use these voltages.
f the Board is installed in a Compact PC rack, the board can be configured by means of
jumpers such that the +5V, +3.3V, +12V and -12V are provided from the Compact PC
backplane instead of the internal regulators.
2.10 Ethernet Interface
The UT699RH AS C device incorporates a Ethernet controller with support for M interface,
and the GR-UT699 Development Board has an ntel LXT971 10/100Mbit/s Ethernet PHY
transceiver and RJ45 connector are on board.
For more information on the registers and functionality of the Ethernet MAC+PHY device
please refer to the data sheet for the WJLXT971A device.
A 25MHz oscillator dedicated for this device is provided on the board.
The interrupt output of the Ethernet MD O interface is connected to the PIO[4] input to the
UT699 AS C. This can be disabled by removing jumper JP2 if necessary.
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-10: Power Regulation Configuration
REGULATOR
+3.3V
Vcore
(+2.5V for UT699RH core)
EXTERNAL POWER
SUPPLY, REGULATED
+5V, >1A
J13 POWER
2.1mm JACK
CPC CONNECTOR
+5V PC
REGULATOR
+3.3V PC
1
1
2
3
2
3
JP12
JP13
+V O PC
n.c.
±12V PC
MEZZ. CONN.
+3V3asic
(+3.3V for UT699RH)
JP14
JP15

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2.11 PCI Interface
The UT699RH AS C incorporates a 33MHz/32 bit interface with 8 channel PC Arbiter and is
capable of being configured to be installed in either the SYSTEM slot (HOST) or in
PER PHERAL slots (GUEST).
The GR-UT699 board can be configured to operate either as a peripheral slot card or system
slot card as described in the following sections.
Note that the GR-UT699 board has been designed to operate in a 3.3V signalling
environment, and the Compact PC connector is appropriately keyed (yellow key).
© Aeroflex Gaisler AB March 2013, Rev. 0.6
Figure 2-11: Block diagram of Ethernet nterface
UT699RH
ETH_RXCLK 25MHz
ETHERNET
PHY
ETH_TXCLK
RJ45
ETH_RXD[3..0]4
ETH_TXD[3..0]4
ETH_CLK
ETH_RXERR
ETH_RXDV
ETH_TXER
ETH_TXEN
ETH_CRS
ETH_COL
ETH_MD O
ETH_MDC
ETH_MD NT