Arcom APCI-SER4 User manual

APCI-SER4
2192-09100-000-000J592 APCI-SER4
Page 1
Introduction
The APCI-SER4 is a 32-bit PCI local bus board which provides 4 channels of RS232/422/485 serial
communications. It utilises two 85230 Enhanced serial communication controllers. Each channel can
be independently configured for asynchronous or synchronous protocols, baud rate and signalling
standards. The board supports communication speeds of up to 115kbaud (asynchronous) and
1.8Mbaud (synchronously).
All serial channel signals are routed to a 50 way D-type connector.
Features
 4 Serial Communications Channels
 Powerful and versatile 85230 Enhanced Serial Communications controllers
 RS232, RS485 and RS422 signal levels supported
 Transmit and Receive FIFOs
 Interrupt facility
 Board Access LED (RED)
 User LED (GREEN)
 Industry Standard I/O via 50 way D-type
 PCI 2.1 Compatible Bus Interface
 Plug and Play software compatible
 CE Compliant design
 Operating temperature range 0 to +70C
 Power Consumption 250mA@+5V, 70mA@+12, 60mA@-12V
 MTBF: 350,014 hours (using generic figures from MIL-HDBK-217F at ground benign)
Getting Started
 Power down your PC system.
 Install the board in a spare PCI Slot (See Installation for CE compliance).
 Power up system with MSDOS.
 Run APCI.EXE (supplied on the utility disk), this will search for the board and check I/O access. If
this fails, check board is correctly located.
Warning
This board contains CCMMOOSSdevices which may be damaged by static electricity. Please ensure anti-
static precautions are taken at all times when handling this board. If for any reason this board is
returned to Arcom Control Systems, please ensure it is adequately packed to prevent damage during
shipment.

Page 2
Operation
PCI Bus Interface
The PCI bus is a high speed alternative to ISA bus, it has been designed to overcome some of the
limitations of ISA bus, and provide faster throughput for I/O intensive peripheral devices. PCI bus
also supports Plug and Play configuration which allows the system software to allocate resources
during initialisation helping to overcome resource conflicts, which might exist in a system.
The APCI-SER4 uses a single chip PCI bus slave controller which is designed and manufactured by
PLX Technology. This device has been designed to fully support the PCI 2.1 specification and
provides plug and play software capabilities. During power-up initialisation the PCI BIOS will detect
the card and assign a unique I/O address location and interrupt line. This ensures that there are no
resource conflicts on the PCI bus. Multiple cards are supported through this mechanism without the
need for address decode links.
The PLX device contains a standard type 00H configuration space header. The table below shows the
registers within this header which are required for configuration of the APCI-SER4.
Configuration Space Header
These registers can be accessed using PCI BIOS functions. Please contact Arcoms customer support
team (Tel: [phone]) for a copy of the PCI BIOS Specification if required.
Enhanced Serial Communication Controllers
The APCI-SER4 contains two 85230 Enhanced Serial Communication Controllers (ESCC), each device
provides two full-duplex communication channels. The serial interface lines from these devices are
buffered on board by RS232 and RS485/422 devices.
The ESCC is a versatile and powerful device and requires careful initialisation. For this reason it is
recommended that the ESCC manufacturers manual is used. This may be obtained by contacting
Arcoms customer support team (Tel:[phone]). It should be noted that these devices are NOT
compatible with the PC 8250-type UART.
The order in which registers are initialised is important and a register may need to be accessed more
than once during initialisation. Unreliable operation may be experienced if short cuts are taken. For
examples of basic ESCC initialisation, please refer to the programs on the utility disk.
Each ESCC occupies four I/O locations in the APCI-SER4 indexed I/O map; two consecutive locations
per channel. The lower address of each pair is used to select the appropriate register within the
device, and to read/write data to the register. The higher address provides direct connection to the
receive and transmit data latches.
The internal ESCC registers are accessed using an indexed addressing scheme like the APCI-SER4.
The appropriate index must be written each time a register is accessed. Therefore each read/write
operation to a register must be preceded with a write to the index register. After a read/write
operation the index is reset to 0.
2192-09100-000-000 J592 APCI-SER4
Offset
00-01H
02-03H
18-1BH
2C-2DH
2E-2FH
3CH
Register Name
Vendor ID
Device ID
Base Address Register
Subsystem Vendor ID
Subsystem ID
Interrupt Line
Description
ID of PCI device manufacturer
ID of PCI device
ID of board manufacturer
ID of Board
Interrupt line assigned to device
I/O base address assigned to card
Value
10B5H (PLX Technology)
9050H
0000xxxx
13ABH (ARCOM)
0592H (APCI-SER4)
0x

Page 3
2192-09100-000-000J592 APCI-SER4
Initialising ESCC Control Registers
The following procedure is required to access the ESCC registers.
1. Write the control register index (for the appropriate channel) to the APCI-SER4 base address.
2. Write the ESCC register index to the APCI-SER4 base+1 address.
3. Write the new data to the APCI-SER4 base+1 address.
4. Repeat steps 2 and 3 for each of the ESCC registers.
Transmitting and Receiving Data
The following tables show the steps required to transmit and receive deta in polled mode from
Channel 2.
Transmit Data
Receive Data
Baud Rates
Each serial channel has a 16-bit baud rate counter which is used for both transmit and receive data
operations. In asynchronous mode, the ESCC can use a x16, x32 or x64 clock.
The following table shows some typical baud rates and their time constants, when the x16 mode is
selected:
The baud rate counter is set by writing the low byte of the time constant to ESCC register 12
(decimal) and the upper byte to register 13 (decimal). As the board rates shown in the table above
all have time constants of less than 256, their upper bytes are all zero.
Interrupts
The APCI-SER4 has one interrupt signal which is routed to an IRQ line during the PCI BIOS
initialisation. This interrupt line is expanded on board to provide two interrupt sources. These
interrupts are connected to the output signals from the ESCC devices.
An interrupt source register has been provided at index 10H. The interrupt service routine must read
this register to determine which device generated the interrupt request. If bit 0 in this register is set
(logic 1) Channel 1 or 2 has requested the interrupt, if bit 7 is set Channel 3 or 4 has requested the
interrupt all other bits will be zero.
Action
Write 02H to the Base address
Read from Base+1 address
Write 03H to the base address
Write data to be transmitted to
Base+1 address
Logically AND the value with 04H
Explanation
Sets the APCI-SER4 to read register 0 on Channel 2.
Reads Status
Sets APCI-SER4 to write to data register on Channel 2.
Data is written to the transmit buffer
If bit is set the TX buffer is empty and another byte can
be sent. If bit is zero continue to read status.
Action
Write 02H to the Base address
Read from Base+1 address
Write 03H to the base address
Read from Base+1 address
Logically AND the value with 01H
Explanation
Sets the APCI-SER4 to read register 0 on Channel 2.
Reads Status
Sets APCI-SER4 to read from the data register on Channel 2.
Data in receive buffer is read
If bit is set there is a byte in the receive register. If bit is zero
continue to read status.
Baud
9600
19200
38400
115200
Time Constant
22
10
4
0

I/O Map
The APCI-SER4 uses an indexed addressing scheme to access the on-board devices and special
function registers. Two consecutive I/O locations are required to implement this scheme, the base
address is used to set the index value and the base+1 address is used to access the device.
The I/O base address is set by the PCI BIOS during initialisation (refer to the PCI BUS section of this
manual for details). A PCI BIOS function call may be used to determine the base address once the
system has been initialised. Multiple boards may be used in a system as each will be given a unique
I/O address.
Index Registers
Special Function Registers
Page 4
2192-09100-000-000 J592 APCI-SER4
Index
00
00
01
02
02
03
04
04
05
06
06
07
08-0F
10
Register Name
S1
C1
D1
S1
C1
D1
S1
C1
D1
S1
C1
D1
N/A
INT
Read/Write
Read
Write
Read/Write
Read
Write
Read/Write
Read
Write
Read/Write
Read
Write
Read/Write
N/A
Read
Comments
Channel 1 Status
Channel 1 Control
Channel 1 Data
Channel 2 Status
Channel 2 Control
Channel 2 Data
Channel 3 Status
Channel 3 Control
Channel 3 Data
Channel 4 Status
Channel 4 Control
Channel 4 Data
Not Used
Interrupt Line Status
Index
80
81
Register Name
User LED
Board Ident
Read/Write
Write
Read
Comments
01H Switches LED ON
00H Switches LED OFF
Always returns 10H for
APCI-SER4

Links
Throughout this section a + indicates the default link position.
Default Link Positions
There are three functions defined by the links on the APCI-SER4: whether the serial lines are RS232
or RS485/422 (and how some of them are connected); synchronous clock sourcing; and receiver
enabling/disabling.
The first digit of the link number refers to the channel i.e LK13 refers to channel 1. The links define
whether some of the lines connecting to the ESCC for that channel are at RS232 or RS485/422
levels, and in some cases which lines go to the 50-way connector.
Some of the serial lines are not affected by these links. This is either because they have a connection
on the 50-way connector, which is not shared with a different function or level, or because the device
can operate at either level.
RS232/485 and RS422 - Serial Signal Connections
Page 5
2192-09100-000-000J592 APCI-SER4
Link
LK10
Channel
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
Ribbon Cable
Pin No.
9
8
4
7
19
18
14
17
29
28
24
27
39
38
34
37
A+ Position
RS232
DTR
CTS
TX
RTS
DTR
CTS
TX
RTS
DTR
CTS
TX
RTS
DTR
CTS
TX
RTS
B Position
RS485/422
DCD
DTR+
TX+
DTR
DCD
DTR+
TX+
DTR
DCD
DTR+
TX+
DTR
DCD
DTR+
TX+
DTR
LK11
LK12
LK13
LK20
LK21
LK22
LK23
LK30
LK31
LK32
LK33
LK40
LK41
LK42
LK43

2192-09100-000-000
Page 6
J592 APCI-SER4
Synchronous Clock selection, RS232 and RS485/422 enabling/disabling
There are four groups of nine pins: each group contains three two-position links. They are LK14A-C,
LK24A-C, LK34A-C and LK44A-C. The first digit of the link number refers to the channel; the letter
refers to the function.
The A links control receiver enables. If a link is inserted in position A on one of these links, the
receive buffer is enabled when RTS is active. If the link is in position B, the receive buffer is
permanently enabled.
The B links change the function of ribbon cable wires 3, 13, 23 and 33. Position A connects to the
RS485 transmitted data signal, position B connects to the 85230 TRXC clock inputs via RS232
buffers.
The C links change the function of ribbon cable wires 5, 15, 25 and 35. Position A connects to the
RS485 receive data signal, position B connects to the 85230 RTXC clock inputs via RS232 buffers.
LK14A
LK14A
A
B+
RX buffer enabled when RTS active
RX buffer is permanently enabled
LK14B
LK14B
A
B+
Pin 3 of D-Type connects RS485 TX data
Pin 3 of D-Type connects to 85230 TRXC clock input via RS232 buffer
LK14C
LK14C
A
B+
Pin 5 of D-Type connects to RS485 RX data
Pin 5 of D-Type connects to 85230 RTXC clock input via RS232 buffer
LK24A
LK24A
A
B+
RX buffer enabled when RTS active
RX buffer is permanently enabled
LK24B
LK24B
A
B+
Pin 13 of D-Type connects RS485 TX data
Pin 13 of D-Type connects to 85230 TRXC clock input via RS232 buffer
LK24C
LK24C
A
B+
Pin 15 of D-Type connects to RS485 RX data
Pin 15 of D-Type connects to 85230 RTXC clock input via RS232 buffer
LK34A
LK34A
A
B+
RX buffer enabled when RTS active
RX buffer is permanently enabled
LK34B
LK34B
A
B+
Pin 23 of D-Type connects RS485 TX data
Pin 23 of D-Type connects to 85230 TRXC clock input via RS232 buffer
LK34C
LK34C
A
B+
Pin 25 of D-Type connects to RS485 RX data
Pin 25 of D-Type connects to 85230 RTXC clock input via RS232 buffer
LK44A
LK44A
A
B+
RX buffer enabled when RTS active
RX buffer is permanently enabled
LK44B
LK44B
A
B+
Pin 33 of D-Type connects RS485 TX data
Pin 33 of D-Type connects to 85230 TRXC clock input via RS232 buffer
LK44C
LK44C
A
B+
Pin 35 of D-Type connects to RS485 RX data
Pin 35 of D-Type connects to 85230 RTXC clock input via RS232 buffer

Page 7
2192-09100-000-000J592 APCI-SER4
User Configuration Record Sheet
Link
LK10
LK11
LK12
LK13
LK20
LK21
LK22
LK23
LK30
LK31
LK32
LK33
LK40
LK41
LK42
LK43
LK14A
LK14B
LK14C
LK24A
LK24B
LK24C
LK34A
LK34B
LK34C
LK44A
LK44B
LK44C
Default
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
User

2192-09100-000-000
Page 8
J592 APCI-SER4
D-50 I/O Connector (PL1) Pin Assignments
The pin assignments are listed with the pin number of the D-50 connector and also the pin number
when a 50-way IDC ribbon cable is connected to the D-50. The pin assignments conform to the
Arcom signal conditioning system (SCS) and may be connected to an external signal conditioning
board.
Ribbon Cable
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
D-Type
Pin No.
1
34
18
2
35
19
3
36
20
4
37
21
5
38
22
6
39
23
7
40
24
8
41
25
9
42
26
10
43
27
11
44
28
12
45
29
13
46
30
14
47
31
RS232 Signal
Name
0V
0V
N/C
TX1
N/C
RX1
RTS1
CTS1
DTR1
DCD1
0V
SEE LK14
N/C
TX2
N/C
RX2
RTS2
CTS2
DTR2
DCD2
0V
SEE LK24
N/C
TX3
N/C
RX3
RTS3
CTS3
DTR3
DCD3
0V
SEE LK34
N/C
TX4
N/C
RX4
RTS4
CTS4
DTR4
DCD4
0V
SEE LK44
RS485/RS422
Signal Name
Ribbon Cable
Pin No.
D-Type
Pin No.
RS232 Signal
Name
RS485/RS422
Signal Name
0V
0V
TXB1
TXA1
RXB1
RXA1
DTRB1
DTRA1
43
44
45
46
47
48
49
50
15
48
32
16
49
33
17
50
N/C
N/C
N/C
N/C
-12v
+12V
+5V
+5V
N/C
N/C
N/C
N/C
-12v
+12V
+5V
+5V
DCDB1
DCDA1
0V
SEE LK14
TXB2
TXA2
RXB2
RXA2
DTRB2
DTRA2
DCDB2
DCDA2
0V
SEE LK24
TXB3
TXA3
RXB3
RXA3
DTRB3
DTRA3
DCDB3
DCDA3
0V
SEE LK34
TXB4
TXA4
RXB4
RXA4
DTRB4
DTRA4
DCDB4
DCDA4
0V
SEE LK44

Page 9
2192-09100-000-000J592 APCI-SER4
Installation for CE Compliance
To maintain compliance with the requirements of the EMC directive (89/336/EEC), this product must
be correctly installed. The PC system in which the board is housed must be CE compliant as declared
by the manufacturer. The type of external I/O cable required can be chosen according to the notes
below:
1. Remove the cover of the PC observing any additional instructions of the PC manufacturer.
2. Locate the board in a spare PCI slot and press gently but firmly into place.
3. Ensure that the metal bracket attached to the board is fully seated.
4. fit the bracket clamping screw and firmly tighten this on the bracket.
Note:- Good contact of the bracket to the chassis is essential.
5. Replace the cover of the PC observing any additional instructions of the PC manufacturer.
Cable
Cable length 1 Metre or less : Ribbon cable satisfactory.
Cable 1 Metre to 3 Meters : Commercial screened cable.
>3 Meters or noisy environment : Use fully screened cable with metal backshells
e.g. Arcom CAB50CE
The following standards have been applied to this product:
BS EN50081-1 : 1992 Generic Emissions Standard, Residential, Commercial, Light Industry
BS EN50082-1 : 1992 Generic Immunity Standard, Residential, Commercial, Light Industry
BSEN55022 : 1995 ITE Emissions, Class B, Limits and Methods.

2192-09100-000-000
Page 10
J592 APCI-SER4
Product Information
Full information about other Arcom products is available via the FFaaxx--oonn--DDeemmaanndd
SSyysstteemm, (Telephone
Numbers are listed below), or by contacting our WWeebbSSiitteein the UK at: wwwwww..aarrccoomm..ccoo..uukk, or in the US
at: wwwwww..aarrccoommccoonnttrroollss..ccoomm
UUsseeffuull CCoonnttaacctt IInnffoorrmmaattiioonn
CCuussttoommeerr SSuuppppoorrtt SSaalleess
Tel: [phone] Tel: [phone]
Fax: [phone] Fax: [phone]
E-mail: [email protected].uk E-mail [email protected].uk or for the US
E-mail [email protected]
UUnniitteedd KKiinnggddoomm
Arcom Control Systems Ltd
Clifton Road
Cambridge CB1 4WH, UK
Tel: [phone]
Fax: [phone]
FoD: 01223 240 600
UUnniitteedd SSttaatteess
Arcom Control Systems Inc
13510 South Oak Street
Kansas City MO 64145 USA
Tel: [phone]
Fax: [phone]
FoD: 800 747 1097
FFrraannccee
Arcom Control Systems
Centre daffaires SCALDY
23 rue Colbert
7885 SAINT QUENTIN
Cedex, FRANCE
Tel: [phone]
Fax: [phone]
FoD: 0800 90 23 80
GGeerrmmaannyy
Kostenlose Infoline:
Tel: [phone]
Fax: [phone]
FoD: 0130 860 449
IIttaallyy
NumeroVerde:
FoD: 1678 73600
BBeellggiiuumm
Groen Nummer:
Tel: [phone]
Fax: [phone]
NNeetthheerrllaannddss
Gratis 06 Nummer:
Tel: [phone]
Fax: [phone]
The choice of boards or systems is the responsibility of the buyer, and the use to which they are put cannot be the liability of
Arcom Control Systems Ltd. However, Arcoms sales team is always available to assist you in making your decision.
Arcom Control Systems Ltd operate a company-wide quality management system which has
been certified by the British Standards Institution (BSI) as compliant with ISO9001:1994
Revision History
Manual
Issue A V1 Iss 1 980313 First released in this format.
PCB Comments
© 1997 Arcom Control Systems Ltd
Arcom Control Systems is a subsidiary of Fairey Group Plc.
Specifications are subject to change without notice and do not form part of any contract.
All trademarks recognised.