CommTech FASTCOM SuperFASTCOM Quick user guide

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Find the Commtech SuperFastcom-RS-422 / 485 at our website: Click HERE

F™ A ASTCOM
D
A
P
T
E
R
S
SuperFASTCOM
Four Channel Hi
g
h-Speed Synchronous Serial Adapter
for PCI Bus
Hardware Reference Manual
Manufactured by:
9011 E 37th St N
Wichita KS 67226-2006

9011 E. 37TH STREET N.
WICHITA, KANSAS 67226-2006
[phone]
FAX [phone]
http://www.commtech-fastcom.com/
COPYRIGHT (C) 2001, 2002, 2003, 2004, 2005
All rights reserved, including those to reproduce this document or parts thereof in
any form without permission in writing from Commtech, Inc.
FASTCOM is a trademark of Commtech, Inc.
Microsoft is a registered trademark of Microsoft Corporation.
WINDOWS is a trademark of Microsoft Corporation.

REVISION NOTES
REVISION PAGE NUMBER CHANGES MADE
2.1 12 Revised Windows 2000 test procedure
2.2 20 Changed warranty to 2 years
2.3 5 Added SuperFASTCOM Cable to packing
list
2.4 11 Added link to installation manual
2.5 19 Updated contact information
2.6 10 Removed RS-530 references
2.7 1
13
Changed board revision level on CE
certificate
Removed unnecessary register setup
information and repaginated
2.8 1 Added SuperFastcom family information
2.9 18 Changed warranty period to lifetime
2.10 12-13 Added more programs to list
2.11 19-21 Added “Errata” section
Modified features to agree with errata
2.12 21 Appended to “Errata” section
2.13 11 Add hardware installation notes 2a & 2b
2.14 14 Add register descriptions

CONTENTS
“CE” CERTIFICATE..............................................................................................................1
INTRODUCTION
Description / Block Diagram ............................................................................................3
Specifications / Features.................................................................................................4
Board Layout...................................................................................................................5
Communications Overview..............................................................................................6
Comparison to ESCC Family...........................................................................................8
CABLE
Cable Configuration.........................................................................................................9
DB25 Connector Description.........................................................................................10
INSTALLATION
Hardware Installation.....................................................................................................11
Software Installation......................................................................................................11
TESTING THE INSTALLATION
Windows 2000 Test Procedure......................................................................................11
SOFTWARE UTILITIES......................................................................................................12
PROGRAMMING................................................................................................................14
MEMORY MANAGEMENT.................................................................................................16
RS-422/485.........................................................................................................................17
Termination Resistance.................................................................................................18
PROGRAMMABLE CLOCK GENERATORS......................................................................19
ERRATTA...........................................................................................................................20
TECHNICAL SUPPORT.....................................................................................................23
APPENDIX A
Infineon 20534 Technical Data Sheet............................................................................24

1
EUROPEAN UNION DECLARATION OF CONFORMITY
Information Technology Equipment
The Company COMMTECH, INC. declares under its own and full responsibility that the product
" SuperFastcom - Revision 2.0 "
on which is attached this Certificate is compliant to the "89/336/EEC" Directive, amended by 92/31/EEC and
93/88/EEC.
[ ] The product identified above complies with the requirements of the above EU Directive by meeting the
following standards:
• EN 50081-1 (1992) EMC Generic Emission Standard - Part 1, Residential, Commercial and Light Industry
- EN 55022 (1995), CISPR 22 (1993) Limits and Methods of Measurement of Radio Disturbance
Characteristics of Information Technology Equipment, 30 MHz - 1 GHz, Class B Limits
• EN 50082-1 (1992) EMC Generic Immunity Standard - Part 1, Residential, Commercial and Light Industry
- IEC 801-2 (1984), Method of Evaluating Susceptibility to Electrostatic Discharge, Level 4
- IEC 801-3 (1984), Radiated Electromagnetic field Requirements, Level 3
- IEC 801-4 (1988), Electrical Fast Transient/Burst Requirements, Level 2
Products listed on this declaration are exempt from the requirements of the 73/23/EEC directive due to the input
voltage specification as stated in Article 1 of the directive.
The technical documentation required to demonstrate that this product meets the requirements of the EMC Directive
has been compiled by the signatory below and is available for inspection by the relevant enforcement authorities.
In WICHITA, KS on December 31st of 1995
9011 E. 37th Street North
Wichita, KS 67226-2006
[phone]
Fax [phone]
Mr. Glen R. Alvis
Chief Engineer

2

3
INTRODUCTION
The new SuperFASTCOM PCI adapter is a very high-speed, four channel, synchronous serial
communications adapter designed for Windows- and LINUX-based industrial/commercial
systems. Its outstanding features include data rates up to 40 Mbits/s and the ability to buffer
up to 4 Gigabytes of data (Windows 2000) in system memory.
The SuperFASTCOM supports standard synchronous protocols (HDLC, SDLC) and their
variations, as well as standard asynchronous data formats at data rates up to 40 Mbits/s. The
on-board clock generator provides a high-speed clock source for your system and
eliminating the need for an external clock. The board also features high-speed RS-422/RS-
485 drivers/receivers with on-board line termination.
Programming is simplified with the inclusion of drivers, example programs and comprehensive
documentation supplied on the Fastcom CD. The SuperFASTCOM provides high speed and
high reliability while greatly reducing development time and system complexity.
The SuperFASTCOM family includes:
Form Factor Line Type Ports
PCI RS422/485 OR RS232 4
PC/104+ RS422/485 1 or 2
CompactPCI RS422/485 4
CompactPCI Rear IO RS422/485 4
The following diagram illustrates the basic structure of the SuperFASTCOM:
Bus Control
Logic
Communication
Processor
Memory
Controller
Clock
Generator
#2
Drivers/
Receivers
Termination Resistance
Status
LEDs
1
2
3
4
Channels
PCI Bus
Clock
Generator
#1
Programmable High Speed Clock Source

4
SPECIFICATIONS:
COMMUNICATION CONTROLLER: INFINEON 20534
OS SUPPORT: Windows XP, 2000, NT4; Linux
DATA RATE: All baud rates up to 40 Mbps
DATA BUFFERING: Up to 4 Gbytes (Windows)
Up to 52 Mbytes per channel (LINUX)
DRIVERS/RECEIVERS: High Speed RS-422/RS-485
SIGNALS: TxD, RxD, RTS, CTS, DCD, TT, RT, ST
CONNECTOR CONFIGURATION: DB-78 to four DB-25 connectors
BUS INTERFACE: 32-bit PCI Ver. 2.1
POWER REQUIREMENTS: 450mA @ +5 (typical)
ENVIRONMENT:
Operating Temperature Range: 0 to 70 C
Humidity: 0 to 90% (non-condensing)
MEAN TIME BETWEEN FAILURES: 24.61 Yrs
CERTIFICATION: FCC compliant, CE marked
FEATURES:
Four independent channels
Status LEDs for system development/debugging
Two programmable on-board clock generators
“Switchless” design for durability and reliability
Hardware documentation and software included on CD
Made in Wichita, KS U.S.A.

5
SuperFASTCOM
BOARD LAYOUT
Commtech, Inc.
Wichta, KS
DB78
CONNECTOR
TRANSMIT/
RECEIVE
STATUS
LEDs
PACKING LIST:
SuperFASTCOM Card
SuperFASTCOM Cable
FASTCOM CD
If an omission has been made, please call technical support for a replacement.

6
COMMUNICATIONS OVERVIEW
 HDLC/SDLC Protocol Modes
- Automatic flag detection and transmission
- Shared opening and closing flag
- Generation of interframe-time fill ’1’s or flags
- Detection of receive line status
- Zero bit insertion and deletion
- CRC generation and checking (CRC-CCITT or CRC-32)
- Transparent CRC option per channel and/or per frame
- Programmable Preamble (8 bit) with selectable repetition rate
- Error detection (abort, long frame, CRC error, short frames)
 Bit Synchronous PPP Mode
- Bit-oriented transmission of HDLC frame (flag, data, CRC, flag)
- Zero bit insertion/deletion
- 15 consecutive ’1’ bits aborts sequence
 Octet Synchronous PPP Mode
- Octet-oriented transmission of HDLC frame (flag, data, CRC, flag)
- Programmable character map of 32 hard-wired characters (00 H -1F H)
- Four programmable characters for additional mapping
- Insertion/deletion of control-escape character (7D H) for mapped characters
 Asynchronous (ASYNC) Protocol Mode
- Selectable character length (5 to 8 bits)
- Even, odd, forced or no parity generation/checking
- 1 or 2 stop bits
- Break detection/generation
- In-band flow control by XON/XOFF
- Immediate character insertion
- Termination character detection for end of block identification
- Time out detection
- Error detection (parity error, framing error)
 BISYNC Protocol Mode
- Programmable 6/8-bit SYN pattern (MONOSYNC)
- Programmable 12/16-bit SYN pattern (BISYNC)
- Selectable character length (5 to 8 bits)
- Even, odd, forced or no parity generation/checking
- Generation of interframe-time fill ’1’s or SYN characters
- CRC generation (CRC-16 or CRC-CCITT)
- Transparent CRC option per channel and/or per frame
- Programmable Preamble (8 bit) with selectable repetition rate
- Termination character detection for end of block identification
- Error detection (parity error, framing error)
 Extended Transparent Mode
- Fully bit transparent (no framing, no bit manipulation)
- Octet-aligned transmission and reception
 Protocol and Mode Independent
- Data bit inversion

7
- Data overflow and under run detection
- Timer
Protocol Support
 Address Recognition Modes
- Mode 0 - No address recognition
- Mode 1 - 8-bit (high byte) address recognition
- Non-Auto Mode - 8-bit (low byte) or 16-bit (high and low byte) address recognition
General
 On-chip Rx and Tx data buffer (the buffer size is 128 32-bit words each)
 Programmable buffer size in transmit direction per channel; buffer allocation in receive
direction on request.
 Programmable watermark for receive channels to control transfer of receive data to
host memory.
 Two programmable watermarks for each transmit channel, i.e. one controlling data
loading from host memory and one controlling transfer of transmit data to the
corresponding Serial Communication Controller (SCC).
 Internal test loop capability.

8
SuperFASTCOM / ESCC FAMILY COMPARISON
Enhancements to the ESCC Serial Core
The SuperFASTCOM adapter contains the core logic of the ESCC2 V3.2A as the heart of the
device. Some enhancements are incorporated in the SuperFASTCOM. These are:
 16-Kbyte packet length byte counter
 Enhanced address filtering (16-bit maskable)
 Enhanced time slot assigner
 Support of high data rates (45 Mbit/s for DS3 or 52 Mbit/s for OC1). Protocol support is
limited to HDLC Sub-modes without address recognition.
Simplifications of the ESCC Serial Core
The following features of the ESCC core have been removed:
 SDLC Loop mode
 Extended transparent mode 0 (this mode provided octet buffered data reception without
usage of FIFOs; the SuperFASTCOM supports octet buffered reception via appropriate
threshold configurations for the SCC receive FIFOs)

9
CONFIGURATION FOR SuperFASTCOM CABLE ASSEMBLY
The cable provided with your SuperFastcom adapter splits each channel from the DB78 to into
four DB 25 male connectors.
DB78 PIN NUMBER
SIGNAL DB25 # CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4
GND 1 58 38 9 48
GND 7 68 29 10 49
SD- 2 70 13 22 62
SD+ 14 50 32 2 46
RD- 3 73 36 6 65
RD+ 16 53 17 26 42
RTS- 4 71 33 3 63
RTS+ 19 51 14 23 45
CTS- 5 74 18 27 66
CTS+ 13 54 37 7 41
DCD- 10 76 31 8 40
DCD+ 8 57 12 28 60
TT- 11 69 30 1 61
TT+ 24 52 11 21 47
RT- 9 72 16 25 64
RT+ 17 56 35 5 43
ST- 12 75 34 4 67
ST+ 15 55 15 24 44
PRGCLK- 23 77 N/A N/A N/A
PRGCLK+ 20 78 N/A N/A N/A

10
SuperFASTCOM DB25
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
GND
RT-
RD+
CTS-
ST+
DCD-
SD+
RTS-
20
21
22
23
24
25
RT+
RD-
CTS+
ST-
DCD+
SD-
RTS+
TT-
9
TT+
GND
PROGCLK+ (CH1)
PROGCLK- (CH1)
CABLE CONNECTOR DESCRIPTION
PIN DESCRIPTIONS
PIN# DESCRIPTION 422 TYPE CONNECTED TO
1 SHIELD/GROUND GND
7 SIGNAL/GROUND GND
2 TRANSMIT DATA A SD-
14 TRANSMIT DATA B SD+
3 RECEIVE DATA A RD-
16 RECEIVE DATA B RD+
4 REQUEST TO SEND A RTS-
19 REQUEST TO SEND B RTS+
5 CLEAR TO SEND A CTS-
13 CLEAR TO SEND B CTS+
CLOCK SIGNALS
PIN# DESCRIPTION 422 TYPE CONNECTED TO
8 DATA CARRIER DETECT A DCD+
10 DATA CARRIER DETECT B DCD-
24 TRANSMIT CLOCK OUT A TT+
11 TRANSMIT CLOCK OUT B TT-
17 RECEIVE CLOCK IN A RT+
9 RECEIVE CLOCK IN B RT-
15 TRANSMIT CLOCK IN A ST+
12 TRANSMIT CLOCK IN B ST-
Special Signals On Cable 1 Only
Pin 20 PROGCLK + Programmable clock output
Pin 23 PROGCLK-

11
INSTALLATION
Important: Observe Electrostatic Discharge (ESD) precautions when handling the
SuperFASTCOM board.
1. Unpack the SuperFASTCOM adapter. Keep the box and static bag for warranty repair
returns.
2. Select an open PCI slot in your PC.
a. The SuperFastcom requires that the selected PCI slot be capable of bus mastering.
The card will not function correctly if installed into a non-bus mastering slot.
b. If possible, install the SuperFastcom into one of the Primary PCI slots. If you are
installing into a Secondary PCI slot (i.e., on the other side of a PCI bridge), make sure
that your motherboard’s PCI bridge is properly installed in your operating system
before proceeding with the installation. If you do not have more than three PCI slots,
then none of the slots are secondary.
3. After removing the blank bracket from your PC, install the SuperFASTCOM in the PC by
pressing it firmly into the slot. Install the bracket screw to hold it firmly in place.
4. Re-install the cover on your PC.
5. Install the SuperFASTCOM cable.
Software Installation
Select the link above to open the Installation Manual. Under SuperFastcom, select your
operating system and follow the instructions. When you are finished, select SuperFastcom
from the list at the end of the SuperFastcom section to return to this manual.
TESTING THE INSTALLATION
To fully test the installation of your SuperFastcom, you will
need to build a "loop back plug". Materials needed are a
DB25 female receptacle (solder cup style) and a few short
pieces of 20 or 24 AWG stranded wire. Jumper the pins
together on the DB25 as illustrated:
WINDOWS 2000 TEST PROCEDURE
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
GND
RT-
RD+
7
16
DCD-
SD+
9
20
21
22
23
24
25
RT+
RD-
2
3SD-
14 TT-
1. Place the loop back plug onto the Port 1 connector.
9TT+
10
11
24
17
SIGNALS

12
2. Open a console/DOS window.
3. Change directories to where you installed/copied the software.
4. Execute: setclock 0 4000000
5. Execute: sfcset 0 hdlcset
6. Execute: loopback 0 h
The green and red LEDs for port 1 should be blinking/on. Wait a few moments, press a key,
and the errors/number of bytes sent through the loop will be displayed. The numbers will vary
depending on how long you allow the test to run
The rest of the ports can be checked by executing:
sfcset 1 hdlcset
loopback 1 h
sfcset 2 hdlcset
loopback 2 h
sfcset 3 hdlcset
loopback 3 h
SOFTWARE UTILITIES
These programs and their source can be found on the Fastcom CD or downloaded from
our website at http://www.commtech-fastcom.com/. They are meant to be used as
educational tools and programming references when designing your own software.
• sfcset.exe Use to change register settings in conjunction with the hdlcset file
• hdlcset, asyncset, bisyncset
Generic settings files to be used with sfcset.exe
• getclock.exe returns programmable clock #1 rate (osc)
• getclock2.exe returns programmable clock #2 rate (progclk +/-)
• setclock.exe sets the programmable clock #1 (osc)
• setclock2.exe sets the programmable clock #2 (prograclk +/-)
• loopback.exe user program to effect a loopback on a SuperFastcom channel
• sfcmfc.exe
o Install your loopback plug onto the SuperFastcom.
o Run “sfcmfc.exe”.
o Select “connect” from the menu.
o A dialog will open. Select the port to use (0,1,2,3).
o Click on “OK”.
o An info box will open; click “OK”.

13
o Type a message: “Hello, world”.
o What you type should show up under “Transmit” in the window.
o Select “Send” from the menu.
o The message will appear in red under “Received”.
o To open a different port, either select “File->New” or “Disconnect” from the menu.
• readlb.exe user program to read a SuperFastcom special register
• writelb.exe user program to read a SuperFastcom special register
• readreg.exe user program to read a 20534 register
• writereg.exe user program to write to a 20534 register
• send.exe user program that opens a file and sends it through port 0
• flushrx.exe user program to flush the SuperFASTCOM receiver/buffers
• flushtx.exe user program to flush the SuperFASTCOM transmitter/buffers
• getbufs.exe user program to get buffering/descriptor parameters for a port
• setbufs.exe user program to set buffering/descriptor parameters for a port
• getclock.exe user program to get the current clock generator settings
• getclock2.exe user program to get the current program clock generator settings
• read_file_hdlc.exe user program to read hdlc frames from a port and stuff them to a
file
• sendfile.exe user program to send a file out a SuperFastcom port
• setchecktimeout.exe
user mode function to set the timeout timer in the driver
that checks for frames to be returned or sent
• setfs6131clock.exe user program that sets the fs6131 clock generator which is only
valid if you have an extended temperature card with fs6131’s on it
• setrfi.exe user program to mask/unmask the frame end interrupt indication for
receive descriptors
• setrirq.exe user program to set the interrupt rate for receive descriptors
• settirq.exe user program to set the interrupt rate for transmit descriptors
• settfi.exe user program to mask/unmask the frame end interrupt indication for
transmit descriptors
• simuln200.exe user program to generate 26 byte hdlc frames simulating an LN200
• st_tt.exe user program to switch the onboard txclk multiplexer between the
TT output and the ST input
• status.exe user program to read status from a SuperFastcom port