AsashiKASEI AKM AK7722 User manual

[AK7722]
MS1328-E-00 - 1 - 2011/09
GENERAL DESCRIPTION
The AK7722 is a digital signal processor with an integrated 4ch 24bit DAC, a stereo ADC with input selector
and a 2ch input ADC. The integrated 4ch DAC, the 2ch ADC with input selector and the other 2ch ADC
feature high performance achieving 108dB, 96dB and 95dB, respectively. The integrated SRC has three
input selector enabling the DSP to operate in master mode with digital inputs. The audio DSP has
1536step/fs (at 48kHz sampling) parallel arithmetic operation performance and the 5k-word delay RAM
allows surround processing and time alignment adjusting. As the AK7722 is a RAM based DSP, it is
programmable for various user requirements. It is housed in an 80pin LQFP package.
FEATURES
[DSP Block]
- Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point)
- Processing Speed: 13.6 ns (1536step/fs; fs = 48kHz)
- Multiplication: 20 x 24 →44-bit Double precision arithmetic available
- Divider 20 / 20 →20bit
- ALU: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic
and logic operation
- Program RAM: 3072 x 36bit
- Coefficient RAM: 2048 x 24bit (F24 floating point)
- Data RAM: 2048 x 24-bit (F24 floating point)
- Offset Register: 64 x 13bit
- Delay RAM1: 3072 x 24-bit
- Delay RAM2: 2048 x 24-bit
- Sampling rate: fs= 7.35k ~ 48kHz
- Master Clock: 1536fs
(generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL)
- Master/Slave Operation
[ADC1 Block]
- Stereo with 6 Inputs Selector
- DR, S/N: 96dB (fs = 48kHz, when differential input)
- S/(N+D): 90dB (fs = 48kHz)
- Differential & Single-ended Inputs
- Digital HPF (fc=1Hz)
- 6 Analog Inputs Selector (2 differential, 4 single-ended)
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[ADC2 Block]
- DR, S/N: 95dB (fs = 48kHz)
- Single-ended Inputs
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[SRC Block]
- 3 Pair of Stereo →1 Stereo Pair Selector
- 2ch x 1 system
- Supporting frequency: Fin = 7.35kHz ~ 96kHz →Fout = 7.35kHz ~ 48kHz
(FSO/FSI = 0.167~ 6.0)
24bit 4ch ADC + 24bit 4ch DAC with Audio DSP
AK7722

[AK7722]
MS1328-E-00 - 2 - 2011/09
[Guidance SRC Block] (GSRC)
- 1 Channel (24bit) Up-converter for Voice Guidance
- Supporting frequency: Fin = 7.35kHz ~ 12kHz →Fout = 44.1kHz or 48kHz
[DAC Block]
- 4ch (2 Stereos)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~48kHz)
- DR, S/N: 108dB (Differential Output)
- S/(N+D): 90dB
- Digital Volume Control (12dB ~ -115dB, 0.5dB Step, Mute)
[Digital Interface Input/Output]
- Digital Signal Input Port (4ch):
24bit MSB justified, 24/20/16bit LSB justified and I2S Format
- Digital Signal Output Port (6ch):
24bit MSB justified, 24/16bit LSB justified and I2S Format
[Micro Computer Interface]
- I2C or 4-wired Interface
[General]
- Integrated PLL
- Integrated Regulator 3.3V →1.8V
- Power Supply: 3.3V ± 0.3V
- Operating Temperature Range: -40˚C ~ 85˚C
- 80pin LQFP

[AK7722]
MS1328-E-00 - 3 - 2011/09
■Block Diagram
pull down
Hi-z
CLKO
2
3
DVDD
VSS2
CLKOE
Open Drain
SCLK / SCL
SI / CAD0
RQN / CAD1
SDOUT1 / GP0
SDA
I2CSEL
MICIF
SDIN1
J
X
0
DIN3
DIN1
DIN4
DOUT3
DOUT4
DSP
OUT3E
SDOUT3 / IRPT
ADC1
XTO
XTI
CLKGEN & CONT
LFLT
IRESETN
TESTI1
BICKI
LRCKI
2
AIN3L,AIN3R
AIN1LP,AIN1LN
AIN1RP,AIN1RN
4
SDOUTAD1
DAC2
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
DAC1
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
DOUT1
SDINDA2
SDINDA1
REF
VCOM
AVDRV
DOUT2
SO
RDY
SELDO4[1:0]
SELDO5[1:0]
2
ASEL[2:0]
DOUT5
IRPT
0
1
2
3
0
1
2
3
DVOL
DVOL
DVOL
AVDD 3
VSS3
3
2
AIN4L,AIN4R
2
AIN5L,AIN5R
4
A
IN2LP,AIN2LN
2
AIN6L,AIN6R
ADC2DVOL
2
SDOUTAD2
DIN5
JX0
OUT2E
SDOUT2
RDY
SRC
SRCBICKI
SRCLRCKI
UNLOCK
SRCI
SRCO
SRIN3,SRBICK3
SRLRCK3
3
3
3
SRIN2,SRBICK2
SRLRCK2
SRIN1,SRBICK1
SRLRCK1
2
1
0
DSEL
[
1:0
]
1
0
SRIN1
1
0
SRIN2
SRCLFLT
SRCLFLT
WDT
UNLOCK
AIN2RP,AIN2RN
BICKO
LRCKO
TESTI2
SDIN2 / JX1
DIN2
0
1
2
3
0
1
2
3
0
1
2
3
A2INL,A2INR
SELDO3[1:0]
OUT1E
SELDO2[1:0]
SELDO1[1:0]
SO
LDO
GP0
J
X
1
JX1E
STO
GP1
SELDI3
MUX[2:0]
SELDI4
BICKOE
LRCKOE
WDTEN
SDIN5
GBICKI
GLRCKI
GSRC
MUX2
MUX1
MUX2[2:0]
CRC
GP1
CRCE
JX2E
J
X
2
1
0
SELDI5
SRIN3
0
1
2
3
4
5
Figure 1. Block Diagram
* Figure 1 shows a simplified diagram of the AK7722, which is not the perfect same as the actual circuit diagram.

[AK7722]
MS1328-E-00 - 4 - 2011/09
CP0, CP1
CRAM
2048W x 24-Bit
DP0, DP1
DRAM
2048w x 24-Bit
MPX24 MPX20
OFREG
64w x 13-Bit
X Y
Multiply
24 x 20 →44-Bit
Micon I/F
Control
PRAM
3072w x 36-Bit
DEC
PC
Stack: 5level(max)
MUL DBUS
SHIFT
A B
A
LU
48-Bit
Overflow Margin: 4-Bit
DR0
∼3
Over Flow Data
Generator
Division 20÷20→20 Peak Detector
Serial I/F
CBUS(24-Bit)
DBUS(24-Bit)
44-Bit 24-Bit
44-Bit
48-Bit
48-Bit
DLRAM1:3072W x 24-Bit
PTMP(LIFO) 6 x 24-Bit
DLP0, DLP1
DIN1
DOUT4(DAC1)
2 x 24, 20, 16-Bit
2 x 24, 20, 16-Bit
48-Bit
DOUT1
TMP 12 x 24-Bit
2 x 24, 20, 16-Bit
2 x 24(,16)-Bit DIN5 (ADC2)
DOUT2
DOUT3
2 x 24, 20, 16-Bit
2 x 24, 20, 16-Bit
DIN4 (ADC1)
2
x 24, 20, 16-Bit DIN3 (SRC)
DIN2
2
x 24, 20, 16-Bit
2 x 24(,16)-Bit
DLRAM2:2048W x 24-Bit
DOUT5(DAC2)
2 x 24, 20, 16-Bit
Figure 2. Main DSP Block Diagram of the AK7722

[AK7722]
MS1328-E-00 5 2011/09
■Ordering Guide
AK7722VQ -40 ∼+85°C 80pinLQFP
AKD7722 Evaluation Board for AK7722
■Pin Layout
(TOP VIEW)
80
p
in LQF
P
AOUTR2N
A
VDRV
61
62
63
64
65
66
67
68
69
70
72
73
71
74
76
77
75
78
79
80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40
39
38
3
7
3
6
35
34
3
3
32
31
2
9
28
30
2
7
25
24
2
6
2
3
2
2
21
60
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SDOUT1 / GP0
SDOUOT2 STO SRLRCK2 SRBICK2 I2CSEL TESTI2 VSS4 DVDD SRCLFLT VSS5
A
VDD
AOUTR2P
AOUTL2N
AOUTL2P
A2INR
RQN / CAD1
RDY
SRBICK1
BICKI
AINR2P
TESTI1
AOUTR1N
AOUTR1P
AOUTL1N
AINR6
A2INL
SDIN1
SDIN2 / JX1
Input
Output
I/O
Power
pin
AOUTL1P
SRIN1
XTO
AINL3
AINL1P
AINR1N
AINL1N
AINL2P
SDA
VSS3
CLKO
SO
DVDD
SRLRCK3 UNLOCK SRBICK3 SRIN3
AVDD
LRCKI
SCLK / SCL
BICKO
SI / CAD0
AINR3
AINL4
AINR4
AINL6
AINL5
LFLT
AINL2N
AINR2N
AINR5
VSS6
JX0
GBICK
SDIN5
VSS2
DVDD
GP1
SRLRCK1
XTI
VCOM
LRCKO
SRIN2 SDOUT3 / IRPT
GLRCK
AVDD
VSS1
AINR1P
INITRSTN

[AK7722]
MS1328-E-00 6 2011/09
No. Name I/O Function Classification
1 AINL3 I
ADC1 Lch Single-ended Input 3 Pin. Analog Input
2 AINR2N I
ADC1 Inverted Rch Differential Input 2 Pin Analog Input
3 AINR2P I
ADC1 Non-inverted Rch Differential Input 2 Pin Analog Input
4 AINL2N I
ADC1 Inverted Lch Differential Input 2 Pin Analog Input
5 AINL2P I
ADC1 Non-inverted Lch Differential Input 2 Pin Analog Input
6 AINR1N I
ADC1 Inverted Rch Differential Input 1 Pin Analog Input
7 AINR1P I
ADC1 Non-inverted Rch Differential Input 1 Pin Analog Input
8 AINL1N I
ADC1 Inverted Lch Differential Input 1 Pin Analog Input
9 AINL1P I
ADC1 Non-inverted Lch Differential Input 1 Pin Analog Input
10 AVDD - Analog Power Supply Pin 3.0 ~ 3.6V Power Supply
11 VSS1 - Analog Ground Pin 0V Power Supply
12 LFLT
O R and C Component Connect Pin for PLL
Refer to “7. LFLT Pin External Connection”. This pin outputs “L” during
initial reset.
Analog Output
13 TESTI1 I Test 1 Pin (Internal pull-down)
This pin must be connected to VSS. Test
14 GLRCKI I Frame Clock Input Pin for Voice Guidance Digital Input
15 GBICKI I Bit Clock Input Pin for Voice Guidance Digital Input
16 SDIN5 I Serial Audio Input Pin for Voice Guidance Digital Input
17 DVDD - Digital Power Supply Pin 3.0~3.6V Power Supply
18 VSS2 - Ground Pin 0V Power Supply
19 XTI I
Crystal oscillator input pin
Connect a crystal oscillator between this pin and the XTO pin, or input an
external clock to the XTI pin.
Clock
20 XTO O
Crystal Oscillator Output Pin
When a crystal oscillator is used, connect it between XTI and XTO. When
an external clock is used, leave this pin open. During initial reset, the output
of this pin is not determinable.
Clock
21 GP1 O
Programmable Bit Output Pin
This pin outputs “L” during initial reset. Digital Output
22 JX0 I
Conditional Jump Pin0
The conditional jump pin (JX0) is valid by setting control register (JX0E) to
“1”.
Conditional Input
23 LRCKI I LR Channel Select Clock Pin 1
LR clock should be input to this pin in slave mode.
System Clock
Input
24 BICKI I Serial Bit Clock Input Pin 1
BITCLOCK (48fs or 64fs) should be input to this pin in slave mode.
System Clock
Input
25 SDIN1 I Serial Data Input 1 Pin Digital Input
SDIN2 I Serial Data Input 2 Pin Digital Input
26 JX1 I
Conditional Jump Pin1
The conditional jump pin (JX1) is valid by setting control register (JX1E) to
“1”.
Conditional Input
27 SRLRCK1 I LR Channel Select Clock Pin 1 (for SRC) System Clock
Input
28 SRBICK1 I Serial Bit Clock Input Pin 1 (for SRC) System Clock
Input
PIN FUNCTION

[AK7722]
MS1328-E-00 7 2011/09
No. Name I/O Function Classification
29 SRIN1 I Serial Data Input Pin 1 (for SRC) Digital Input
SDIN3 I Serial Data Input Pin 3
30 RDY O
Data Write Ready Output Pin for Microprocessor Interface
This pin outputs RDY, and outputs “H” during initial reset.
Microprocessor
RQN I
Microprocessor Interface Write Request Pin (I2CSEL pin = “L”)
When initial reset state and Microcomputer interface are not in use, leave
RQN pin= “H”.
Interface
31
CAD1 I
I2C Bus Address Setting Pin 1 (I2CSEL pin = “H”) I2C
SCLK I Serial Data Clock Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SCLK is not used, tie the SCLK pin = “H”.
Microprocessor
Interface
32
SCL I
I2C Bus Data Clock Pin (I2CSEL pin = “H”) I2C
SI I Serial Data Input Pin for Microprocessor Interface (I2CSEL pin = “L”)
When SI is not used, tie the SI pin = “L”.
Microprocessor
Interface
33
CAD0 I
I2C Bus Address Setting Pin 0 (I2CSEL pin = “H”) I2C
34 SO O
Serial Data Output Pin for Microprocessor Interface
Outputs “L” during initial reset.
Microprocessor
Interface
O I2CSEL pin = “L”
Leave this pin Open. SDA outputs “L”. Open
35 SDA I/O I2C Bus Data Clock Pin (I2CSEL pin = “H”)
Outputs “Hi-z” during initial reset. I2C
36 DVDD - Digital Power Supply Pin 3.0~3.6V Power Supply
37 VSS3 - Ground Pin 0V Power Supply
38 CLKO O
Clock Output Pin
This pin outputs “L” during initial reset. Clock Output
39 LRCKO O
LR Channel Select Output Pin
This pin outputs “L” during initial reset in master mode.
System Clock
Output
40 BICKO O
Serial Bit Clock Output Pin
This pin outputs “L” during initial reset in master mode.
System Clock
Output
SDOUT1 O
Serial Data Output1 Pin
This pin outputs “L” during initial reset.
Digital Output
41
GP0 O Programmable Bit Output Pin Digital Output
42 SDOUT2 O
Serial Data Output2 Pin
This pin outputs “L” during initial reset.
Digital Output
SDOUT3
O Serial Data Output3 Pin
This pin outputs “L” during initial reset.
Digital Output
43
IRPT O Interrupt Status Output Pin Digital Output
44 STO O
Status Output Pin
This pin outputs “H” during initial reset. Status
45 SRLRCK2 I LR Channel Select Clock Pin 2 (for SRC) System Clock
Input
46 SRBICK2 I Serial Bit Clock Input Pin 2 (for SRC) System Clock
Input
SRIN2 I Serial Data Input Pin 2 (for SRC)
47 SDIN4 I Serial Data Input Pin 4 Digital Input
48 SRLRCK3 I LR Channel Select Clock Pin 3 (for SRC) System Clock
Input

[AK7722]
MS1328-E-00 8 2011/09
No. Name I/O Function Classification
49 SRBICK3 I Serial Bit Clock Input Pin 3 (for SRC) System Clock
Input
SRIN3 I Serial Data Input Pin 3 (for SRC) Digital Input
50 JX2
I Conditional Jump Pin2
The conditional jump pin (JX2) is valid by setting control register (JX2E) to
“1”.
Conditional Input
51 UNLOCK O
SRC UNLOCK State Output Pin
This pin outputs “H” during initial reset. SRC Status
52 INITRSTN I
Reset Pin (for Initialization)
Use to initialize the AK7722. Set this pin to “L” when power-up the
AK7722.
System
53 I2CSEL I
I2C BUS Select Pin (Internal pull-down)
I2CSEL pin = “L”: 4-wired Interface
I2CSEL pin = “H”: I2CBus selected mode. SCL and SDA are active.
I2CSEL should be connected to “L” (VSS) or “H” (DVDD).
I2C Select
54 TESTI2 I Test Input 2 Pin (Internal pull-down)
This pin must be connected to VSS4. Test
55 AVDRV
O AVDRV Pin
Connect a 1μF capacitor between this pin and VSS4 pin. No external
circuits should be connected to this pin. This pin outputs “L” during initial
reset.
Analog Output
56 VSS4 - Ground Pin 0V Power Supply
57 DVDD - Digital Power Supply Pin 3.0~3.6V Power Supply
58 SRCLFLT O
Capacitor Connect Pin for SRCPLL
Connect a 1μF capacitor between this pin and VSS4 pin. This pin outputs
“L” during initial reset.
Analog Output
59 VSS5 - Ground Pin 0V Power Supply
60 AVDD - Analog Power Supply Pin 3.0~3.6V Power Supply
61 AOUTR2N O
DAC2 Inverted Rch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
62 AOUTR2P O
DAC2 Non-inverted Rch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
63 AOUTL2N O
DAC2 Inverted Lch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
64 AOUTL2P O
DAC2 Non-inverted Lch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
65 AOUTR1N O
DAC1 Inverted Rch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
66 AOUTR1P O
DAC1 Non-inverted Rch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
67 AOUTL1N O
DAC1 Inverted Lch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
68 AOUTL1P O
DAC1 Non-inverted Lch Differential Analog Output Pin
“Hi-Z” output during initial reset
Analog Output
69 AVDD - Analog Power Supply Pin 3.0~3.6V Power Supply
70 VCOM
O Analog Common Voltage Output pin
Connect 0.1μF and 2.2μF capacitors between this pin and the VSS6 pin. No
external circuits should be connected to this pin. This pin outputs “L”
during initial reset.
Analog Output

[AK7722]
MS1328-E-00 9 2011/09
No. Name I/O Function Classification
71 VSS6 - Ground Pin 0V Power Supply
72 A2INR I ADC2 Rch Single-ended Input Pin Analog Input
73 A2INL I ADC2 Lch Single-ended Input Pin Analog Input
74 AINR6 I ADC1 Rch Single-ended Input Pin 6 Analog Input
75 AINL6 I ADC1 Lch Single-ended Input Pin 6 Analog Input
76 AINR5 I ADC1 Rch Single-ended Input Pin 5 Analog Input
77 AINL5 I ADC1 Lch Single-ended Input Pin 5 Analog Input
78 AINR4 I ADC1 Rch Single-ended Input Pin 4 Analog Input
79 AINL4 I ADC1 Lch Single-ended Input Pin 4 Analog Input
80 AINR3 I ADC1 Rch Single-ended Input Pin 3 Analog Input
■Handling of Unused Pin
The following table illustrates recommended states for open pins:
Classification Pin Name Setting
Analog
ANL1P, AINL1N, AINR1P, AINR1N, AINL2P, AINL2N, AINR2P
AINR2N, AINL3, AINR3, AINL4, AINR4, AINL5, AINR5, AINL6, AINR6
AOUTL1P, AOUTL1N, AOUTR1P, AOUTR1N
AOUTL2P, AOUTL2N, AOUTR2P, AOUTR2N
Leave Open
XTO, GP1, RDY, SO, SDA(I2CSEL= “L”), CLKO, LRCKO, BICKO, SDOUT1
SDOUT2, SDOUT3, STO, UNLOCK Leave Open
Digital TESTI1, GLRCK, GBICK, SDIN5, XTI, JX0, LRCKI, BICKI, SDIN1, SDIN2
SRLRCK1, SRBICK1, SRIN1, RQN, SI, SRLRCK2, SRBICK2, SRIN2,
SRLRCK3
SRBICK3, SRIN3, TESTI2
Connect to VSS
The relationship between the I2CSEL pin and SDA pin
I2CSEL INITRSTN SDA
Micro controller L L L
Interface L H L
I2C-bus support H L “Hi-Z”
H H function

[AK7722]
MS1328-E-00 10 2011/09
(VSS1~VSS6=0V:
Note 1)
Parameter Symbol min max Unit
Power Supply Voltage
Analog
Digital
AVDD
DVDD
-0.3
-0.3
4.3
4.3
V
V
Input Current (except for power supply pin ) IIN – ±10 mA
Analog Input Voltage VINA -0.3 AVDD+0.3 V
Digital Input Voltage VIND -0.3 DVDD+0.3 V
Operating Ambient Temperature Ta -40 85 ºC
S
torage Temperature Tstg -65 150 ºC
Note 1. All indicated voltages are with respect to ground.
Note 2. VSS1-6 must be connected to the same ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
(VSS1~VSS6=0V:
Note 1)
Parameter Symbol min typ max Unit
Power Supply Voltage
Analog
Digital
AVDD
DVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Note 3. The power supply sequence for AVDD and DVDD is not critical but all power supplies must be On before start
operating the AK7722.
Note 4. Do not turn off the power supply of the AK7722 with the power supply of the surrounding device turned on.
DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and
SCL pins.)
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS