Bitwise QuickUSB User manual

User Guide
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QuickUSB User Guide
Version 2.11.35
April 28, 2006
Copyright © 2005, 2006 Bitwise Systems. All rights reserved. This document
contains confidential information and trade secrets of Bitwise Systems, and is
protected by United States and international copyright laws. Use, disclosure, or
reproduction is prohibited without the prior express written permission of
Bitwise Systems, except as agreed in the License Agreement. Use, duplication
or disclosure by the U.S. Government is subject to restrictions as provided in
DFARS 227.7202-1(a) and 227.7202-3(a) (1998), and FAR 12.212, as
applicable.

Table of Contents
Introduction 1
QuickUSB and the Big USB Picture 1
USB Nomenclature 1
USB System Architecture 1
I/O Subsystem Latency and Throughput 2
USB Interpacket Delay 2
Designing Hardware for QuickUSB 3
The Cypress EZ USB FX2 3
Power and Ground 3
Unused I/O Pins 4
DefaultI/O State 4
High Speed Parallel Port 4
Overview 4
GPIF Master Mode 5
GPIF Master Mode I/O Models 6
Slave FIFO I/O Models 16
FPGA Configuration 21
General-Purpose I/O Pins 21
RS-232 21
I2C 21
SPI 22
QuickUSB Pin Definitions 23
Using the QuickUSB Library 39
Overview 39
How to Communicate with a Module 39
System Considerations 40
Blocking versus Non-blocking Data Transfers 40
QuickUSB Base API 41
QuickUsbFindModules 41
QuickUsbOpen 41
QuickUsbClose 42
QuickUsbGetStringDescriptor 42
QuickUsbSetTimeout 43
QuickUsbGetDriverVersion 43
QuickUsbGetDllVersion 43
QuickUsbGetFirmwareVersion 44
QuickUsbGetLastError 44
QuickUSB Settings 45
QuickUsbReadSetting 51
QuickUsbWriteSetting 51
QuickUsbReadDefault 52
QuickUsbWriteDefault 52
FPGA Configuration 53
QuickUsbStartFpgaConfiguration 53

QuickUsbWriteFpgaData 54
QuickUsbIsFpgaConfigured 54
High-Speed Parallel Port 55
QuickUsbReadCommand 55
QuickUsbWriteCommand 56
QuickUsbReadData 57
QuickUsbWriteData 58
QuickUsbReadDataAsync 59
QuickUsbWriteDataAsync 60
QuickUsbAsyncWait 61
General-Purpose I/O 62
QuickUsbReadPortDir 62
QuickUsbWritePortDir 62
QuickUsbReadPort 63
QuickUsbWritePort 63
RS-232 64
QuickUsbSetRs232BaudRate 64
QuickUsbGetNumRS232 64
QuickUsbFlushRS232 65
QuickUsbReadRS232 65
QuickUsbWriteRS232 66
I2C-Compatible Port 67
QuickUsbReadI2c 67
QuickUsbWriteI2c 67
SPI-Compatible Port 68
QuickUsbReadSpi 68
QuickUsbWriteSpi 68
QuickUsbWriteReadSpi 69
Index 70

Introduction
Introduction
Thank you for choosing QuickUSB®. QuickUSB makes your product a well-
connected USB device quickly and with a minimum of hassle. Not only is
QuickUSB a quick way to get connected to USB, it also offers great Hi-Speed
USB 2.0 performance with a wide variety of target interface options.
We hope this guide will answer all of your questions about QuickUSB. However,
if you have a question that you cannot find an answer for in this guide, please
check the web site at www.quickusb.com and please use the QuickUSB online
support forum. Our support team will do our best get you the answer you need.
QuickUSB and the Big USB Picture
Please take some time to understand the big picture as it relates to USB
connections. USB has gained the success it has because it is a well-designed
bus specifically designed to easily, and reliably connect peripherals to a PC.
Part of that design defines the relationship between your PC and the device.
Although with QuickUSB you do not need to learn the inner workings of USB, you
do need to understand the basics of USB. We will explain the basics here and if
you want to learn more, you can browse www.usb.org and learn just about
everything that there is to know about USB. Just be careful, because you can
easily get distracted from what you really need to accomplish.
USB Nomenclature
Conveying the big picture requires defining some key words. The first is USB
and it is an acronym for Universal Serial Bus. Host means your PC. Device
means the QuickUSB module and/or the subsystem you need to connect to the
PC. A pipe is a unidirectional virtual connection between a host and the device.
Every pipe has a direction attribute of either IN or OUT to indicate the direction
of data flow with respect to the host. An endpoint is the device side connection
of a pipe. When a device is connected to a host, the host automatically senses
this and enumerates the bus to find it.
USB System Architecture
The USB is a master/slave bus. This means that the master initiates all traffic
on the bus and the slave can only respond to the master. For the USB, the
master is the host computer (your PC) and the slave is the device. This
master/slave relationship means that interrupts are not possible on the USB.
The USB supports a pseudo-interrupt scheme involving low-latency interrupt
endpoints so the host can perform low-latency device polling to emulate an
interrupt. QuickUSB does not currently support interrupt endpoints.
USB Nomenclature 1

QuickUSB and the Big USB Picture
I/O Subsystem Latency and Throughput
The period of time between the start of a transfer and the time that it actually
occurs is the transfer latency. USB transfer latency is the result of several
factors. First is the fact that the USB is a frame oriented bus and that all
packets must be scheduled to a timebase of either 1ms (full speed) or 125us
(Hi-Speed). Secondly, the operating system generally assesses a software
latency penalty when switching from user mode to kernel mode.
Throughput is a measure of data transfer speed and is generally expressed in
megabytes per second (MB/s). Transfer latency affects throughput because it
increases the amount of time a transfer takes regardless of the connection
speed.
However, as the data transfer size becomes larger, the transfer latency
becomes a smaller fraction of the total transfer time thereby diminishing its
effect. When the transfer size is small, the transfer latency will seriously
degrade throughput.
Therefore, for applications that require the highest throughput, transfer sizes of
at least 64KB are recommended.
Another way to mitigate transfer latency issues is to minimize the amount of
time that the USB subsystem waits to schedule USB packets. You can
accomplish this using asynchronous function calls. With asynchronous function
calls, the transfer is scheduled when the function is called, but the function
returns without waiting for the transfer to complete. Using this mechanism, one
can concurrently schedule enough USB transfers to assure that the USB will not
idle waiting for data to be transferred to or from your device.
The simplest and most reliable technique for this is to employ multiple transfer
buffers and rotate them on an as-needed basis.
USB Interpacket Delay
In certain circumstances, the USB target interface bandwidth is greater than the
USB bus bandwidth. This is the case with the Cypress EZ-USB FX2LP
microcontroller. In word-wide mode, the FX2LP can transfer data at up to
96MB/sec. The maximum theoretical throughput of a Hi-Speed USB 2.0 pipe is
54MB/sec. Because the FX2LP can go faster than the USB pipe, the target
interface is subject to periods of bus inactivity (‘gaps’) between data packets.
Your system design should take into consideration the strong that there will be
gaps between data packets and deal with them accordingly.
2 I/O Subsystem Latency and Throughput

Designing Hardware for QuickUSB
Designing Hardware for QuickUSB
Connecting QuickUSB to your hardware is simple. First, decide on the type of
connection you need. If you need to transfer large amounts of data very quickly,
then you should use the High Speed Parallel Port. If you only need to turn some
I/O pins on and off, you can just use the general-purpose I/O pins.
The Cypress EZ USB FX2
QuickUSB is based on the Cypress EZ-USB FX2LP microcontroller. The FX2LP is
a powerful, single-chip USB microcontroller that offers an unparalleled capability
to interface subsystems to a PC with a high-speed USB 2.0 connection.
QuickUSB unleashes the power of the FX2LP to high-level hardware and
software designers by abstracting its capabilities as library of dataflow oriented
function calls. In addition, chip-specific capabilities are supported via ‘Settings’
that allow the user to customize the behavior of the FX2LP to suit the target
application.
Power and Ground
QuickUSB supplies unregulated +5V at up to 400 mA max on the VBUS pins to
power your circuitry. For modules Rev A1 and above, an FET on the QuickUSB
module controls power. Power is off by default and then turned on once the
host configures the module. This behavior is required by the USB specification.
The QuickUSB module incorporates a current limiting circuit that will shut down
the VBUS pins on an over-current condition. In addition the entire module may
be powered down by the host or a USB hub if it draws more than the 500 mA
allotted by the USB.
If your circuit draws less than 400 mA, you may power it from the unregulated
5V provided on the VBUS pins. However, if your circuit will draw more than 50
mA, you should design your circuit with either a downstream power switch (such
as the TPS2051A) or an active high enable logic switched voltage regulator.
Connect the enable signal to SW_PG (pin 76). This signal will enable your
circuit’s voltage regulator once the VBUS switch is turned on and the output
voltage has stabilized to >= 93% of the voltage supplied by the USB. For more
information about the QuickUSB VBUS switch, consult the datasheet for the
Texas Instruments TPS2150.
If your circuit draws more than 400 mA, do not power it from VBUS. It should be
powered with an external power supply and connect the digital ground of your
circuit to GND. In this case, you might want to connect an unused I/O pin to the
external power supply through a current limiting resistor (10K) so you can read
the pin to determine the state of the external power supply.
The Cypress EZ USB FX2 3

Designing Hardware for QuickUSB
Unused I/O Pins
Some I/O pins are reserved for future use and may be activated by a new
version of the module or a new firmware release. Therefore, you must not
connect unused QuickUSB I/O pins to any signals or power supplies. DO NOT
DIRECTLY GROUND UNUSED QUICKUSB I/O PINS IN YOUR CIRCUIT. You may
use a 10k resistor to tie unused pins to a known level, but do not connect them
directly.
Default I/O State
With QuickUSB Library (including firmware) v2.11 and above, QuickUSB
supports non-volatile I/O pin default settings. The default settings are
programmed and read using the QuickUsbWriteDefault and
QuickUsbReadDefault functions respectively.
High Speed Parallel Port
The High-Speed parallel port is a truly outstanding feature of the QuickUSB
module. It is the fastest connection on the QuickUSB module and can transfer
very large blocks of data to and from your device with ease. It provides both
master and slave mode transfers with several types of transfer handshaking
models.
Overview
The high-speed parallel port (HSPP) is an 8 or 16-bit port that is used to transfer
high-speed data between the host PC and your device. The WORDWIDE setting
controls the data element width. If WORDWIDE = 1, the transfers are 16-bits
wide and if 0, 8-bits wide. For more information about WORDWIDE, see the
SETTING_WORDWIDE setting in the ‘Settings’ section of this document. If the
HSPP is in 8-bit mode, the upper 8 bits may be used as general purpose I/O.
In addition, there is a 9-bit address bus which increments each time a data
element is transferred. The address bus can be set to a fixed address to allow
multiple writes to the same address. The address bus can also be disabled and
the address bus bits reused as general purpose I/O. See the
SETTING_DATAADDRESS setting in the ‘Settings’ section of this manual for
more information
There are two modes of HSPP operation, master and slave. The HSPP mode is
automatically selected by the QuickUSB firmware, but it may be changed at any
time using the SETTING_FIFO_CONFIG setting. Typically, your hardware will be
configured for either master or slave mode and the requirements of your
application will determine which mode is best for you.
4 Unused I/O Pins

Designing Hardware for QuickUSB
GPIF Master Mode
In GPIF master mode, the QuickUSB module controls all aspects of the HSPP
and the host PC initiates all data transfers through the QuickUSB module. This
mode is implemented using the GPIF programmable DMA engine built into the
FX2. All GPIF master mode HSPP transfers are synchronous with IFCLK and are
controlled by CMD_DATA, REN, WEN and OE. CMD_DATA indicates whether the
HSPP transfer was initiated by the command or data functions. REN indicates
read a transfer and WEN indicates a write transfer. OE indicates a read
transfer prior to actually asserting the REN signal so that the peripheral can
prepare to execute a read transfer.
Command Transfers
Command transfers are low-speed transfers that use the data bus (FD) and the
address bus (GPIFADR) to read and write data to and from the target hardware.
The QuickUsbReadCommand and QuickUsbWriteCommand functions are used
to perform command transfers. They transfer data one element at a time with
the CMD_DATA line set high (‘1’). Command transfers were designed to control
registers in a peripheral connected to the HSPP, but they can be used for any
type of bi-directional low speed parallel I/O.
Data Transfers
Data transfers are high-speed block-oriented data transfers that use the data
bus (FD) and the address bus (GPIFADR) to read and write data to either a FIFO
or a memory in the target hardware. The QuickUsbReadData and
QuickUsbWriteData functions are used to perform high-speed data transfers.
They transfer data in a burst of data blocks with the CMD_DATA line set low
(‘0’). A single call from QuickUsbReadData or QuickUsbWriteData will be broken
down into a series of data blocks transferred over the HSPP.
High Speed Parallel Port 5

Designing Hardware for QuickUSB
GPIF Master Mode I/O Models
The QuickUSB module interfaces to target hardware by implementing a number
of I/O models that provide enough flexibility to interface to a wide variety target
hardware. The I/O models are selected by reprogramming the firmware of the
QuickUSB module using the QuickUSB Programmer. Each firmware load
implements a different I/O model. The timing diagrams for each I/O model are
given below.
QuickUSB Signal I/O Model
FD[15:0] (Word Wide) or FD[7:0] (Byte Wide) All
IFCLK All
CMD_DATA All
REN or nREN All
WEN or nWEN All
nEMPTY FIFO & Block
nFULL FIFO & Block
nOE FIFO & Block
Table 1 – GPIF Master Mode I/O Connections
GPIF Master Mode Timing Parameters
Internally Sourced
IFCLK Externally Sourced IFCLKParameter Description Min Max Min Max Unit
tIFCLK IFCLK Period 20.83 20.83 200 ns
tSRY RDYX to Clock Set-
up Time 8.9 2.9 ns
tRYH Clock to RDYX Hold
Time 0 3.7 ns
tSGD GPIF Data to Clock
Set-up Time 9.2 3.2 ns
tDAH GPIF Data Hold
Time 0 4.5 ns
tSGA Clock to GPIF Address
Propagation Delay 7.4 11.4 ns
tXGD Clock to GPIF Data Output Propagation
Delay 11 15 ns
tXCTL Clock to CTLX Output Propagation
Delay 6.7 10.7 ns
Table 2 – GPIF Master Mode Timing Parameters
6 High Speed Parallel Port

Designing Hardware for QuickUSB
Simple I/O Model
This I/O model performs transfers without regard to the readiness of the target
hardware. This model is suitable for hardware that is always ready and that can
transfer data as fast as the host can deliver it. This is the fastest QuickUSB I/O
model available.
The Simple I/O model is backwards compatible with all default QuickUSB
firmware files.
This I/O model is implemented in the QuickUSB firmware file
‘quickusb-simple vX.XX.qusb’ where X.XX is the firmware version number.
The Simple I/O model is designed to provide the highest possible data rate that
the hardware can provide.
AS A RESULT, THERE ARE CERTAIN INVALID TRANSFER LENGTHS THAT MAY
RESULT IN A FATAL SOFTWARE ERROR WHICH MAY CRASH YOUR COMPUTER.
The simplest valid transfer length calculation is to request data transfer lengths
in multiples of 512 bytes for Hi-Speed mode or 64 bytes for Full-Speed mode.
For applications that cannot use this simplified method, see the Notes section
below.
Command Transfers
IFCLK IFCLK
Addr0X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGA
Signifies QuickUSB Write to
the Data Bus
t
XCTL
t
XCTL
IFCLK IFCLK
Addr0X
t
DAH
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Read Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGD
t
SGA
Signifies QuickUSB Read
from the Data Bus
t
XCTL
t
XCTL
High Speed Parallel Port 7

Designing Hardware for QuickUSB
Data Transfers
IFCLK IFCLK
X
t
DAH
t
SGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
Z
Read Cycle
Addr1
XData0
Addr3 Addr4
Addr[N]
Data1 Data2 Data 3
Data[N-
1]
Z
t
SGA
nEMPTY RDY0
nFULL RDY1 X
X
t
IFC LK
t
XCTL
Data[N]
X
X
…
… X
Signifies QuickU SB Read from the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed , Wor d Wide : N = 31 High Speed , Wor d Wide : N = 255
t
XCTL
Addr0
t
XCTL
…Data4
Addr[N+1]
Addr5Addr2 X…
IFCLK IFCLK
Addr0X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
Addr1
Data1
Addr2 Addr3 Addr4 …
Addr[N-1] Addr[N]
X
Data2 Data3 Data4
Data[N-1] Data[N]
Z
t
SGA
nEMPTY RDY0
nFULL RDY1
X
t
XCTL
t
IFCLK
Addr[N+1]
X
X X
…
t
XCTL
t
XGD
t
SGA
Signifies QuickUSB Write to the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
Data[N+1]
Notes
The valid data transfer length for the Simple I/O model can be calculated with
the following pseudo code:
If (DesiredLength MOD PacketSize <= PreRead) Then
ValidLength = PreRead
Else
ValidLength = DesiredLength
Where:
DesiredLength = The desired transfer length
Valid = The valid transfer length
PreRead = 2 for Byte Wide Mode, 4 for Word Wide Mode
PacketSize = 512 for Hi-Speed, 64 for Full-Speed
8 High Speed Parallel Port

Designing Hardware for QuickUSB
FIFO Handshake I/O Model
This I/O model is designed specifically to allow QuickUSB to connect directly to
external synchronous or asynchronous FIFOs. This I/O model is ideal for
applications that combine QuickUSB with an FPGA. The
QuickUsbRead/WriteData functions read or write streaming data to FIFOs inside
the FPGA while the QuickUsbRead/WriteCommand functions control a register
array inside the FPGA to manage internal FPGA operations.
With this I/O model, you simply instantiate a FIFO in the FPGA and connect the
data and control lines to the QuickUSB module. Please note the FIFO timing
requirements given in the ‘Data Transfers’ section.
This I/O model is implemented in the QuickUSB firmware file
‘quickusb-fifohs vX.XX.qusb’ where X.XX is the firmware version number.
Command Transfers
IFCLK IFCLK
Addr[N]X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
Z
Write Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGA
Signifies QuickUSB Write
to the Data Bus
t
XCTL
t
XCTL
Data[N]
IFCLK IFCLK
Addr[N]X
t
DAH
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData[N]
Read Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGD
t
SGA
Signifies QuickUSB Read
from the Data Bus
t
XCTL
t
XCTL
High Speed Parallel Port 9

Designing Hardware for QuickUSB
Data Transfers
IFCLK IFCLK
Addr0
t
DAH
t
SGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
Z
Read Cycle
Addr[N]
Z
nEMPTY RDY0
nFULL RDY1 X
t
SRY
t
XCTL
Data 0
t
RYH
Data1Z Z Data[N]Z
X
t
XCTL
t
SRY
t
RYH
t
XCTL
t
XCTL
t
SRY
t
RYH
t
IFCLK
Signifies QuickUSB Read from the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
Addr1 Addr2 Addr[N+1]Z
t
SGA
IFCLK IFCLK
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
Write Cycle
nEMPTY RDY0
nFULL RDY1
X
t
SRY
t
XCTL
t
RYH
X
t
XCTL
Signifies QuickUSB Write to the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
t
SRY
t
RYH
t
XGD
Addr0
ZData0
Addr[N]
ZData1 Data2 Data[N]…
Addr1 Addr2 X
…X
t
SGA
10 High Speed Parallel Port

Designing Hardware for QuickUSB
Full Handshake I/O Model
The full handshake I/O model is ideal for connecting a device that has a very
slow or variable transfer time. The module checks the state of the READY signal
before each state transition and thereby guarantees that the module and target
will be properly synchronized at all times.
This I/O model is implemented in the QuickUSB firmware file
‘quickusb-fullhs vX.XX.qusb’ where X.XX is the firmware version number.
Command Transfers
IFCLK IFCLK
X
Data[N] Z
t
DAH
t
SGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
RDYTST CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZZ
X
Data[N]
t
XGD
Z
Addr[N]
Read Cycle Write Cycle
READY RDY0
t
XCTL
t
SRY
t
XCTL
Addr[N+1]
XAddr[N]
t
XCTL
t
RYH
Addr[N+1]
X
t
SGA
t
SRY
t
RYH
t
XCTL
t
SRY
t
RYH
t
SRY
t
RYH
t
SGA
Signifies QuickUSB Read
from the Data Bus
Signifies QuickUSB Write
to the Data Bus
t
XCTL
t
XCTL
Data Transfers
IFCLK IFCLK
Addr0
X
tDAH tSGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
RDYTST CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Read Cycle
X
Z
tSGA
READY RDY0
Addr1
Data1
Addr[N]
Data[N]Z Z
tSRY tRYH
…Addr[N+1]
…
tXCTL tXCTL tXCTL tIFCLK tSRY tRYH
Signifies QuickUSB Read from the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
IFCLK IFCLK
Addr0
X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
RDYTST CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
X
Z
t
SGA
READY RDY0
Addr1 Addr[N]
Z Z
t
SRY
t
RYH
Addr[N+1]
t
XCTL
t
XCTL
t
IFCLK
Data[N]
t
SRY
t
RYH
Data1
t
XGD
t
XCTL
…
Signifies QuickUSB Write to the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
High Speed Parallel Port 11

Designing Hardware for QuickUSB
Block Handshake I/O Model
Block handshake I/O model is best used for targets that need the benefits of
FIFO handshake but always transfer either 64 (Full Speed) or 512 (Hi-Speed)
byte blocks for each transaction. This I/O model checks the FIFO flags just once
at the beginning of the block and assume that it can transfer the entire block.
This I/O model is implemented in the QuickUSB firmware file
‘quickusb-blockhs vX.XX.qusb’ where X.XX is the firmware version number.
The Block I/O model is designed to provide the highest possible data rate
possible with hardware handshaking.
AS A RESULT, THERE ARE CERTAIN INVALID TRANSFER LENGTHS THAT MAY
RESULT IN A FATAL SOFTWARE ERROR WHICH MAY CRASH YOUR COMPUTER.
The simplest valid transfer length calculation is to request data transfer lengths
in multiples of 512 bytes for Hi-Speed mode or 64 bytes for Full-Speed mode.
For applications that cannot use this simplified method, see the Notes section
below.
Command Transfers
IFCLK IFCLK
Addr0X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGA
Signifies QuickUSB Write to
the Data Bus
t
XCTL
t
XCTL
IFCLK IFCLK
Addr0X
t
DAH
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Read Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGD
t
SGA
Signifies QuickUSB Read
from the Data Bus
t
XCTL
t
XCTL
12 High Speed Parallel Port

Designing Hardware for QuickUSB
Data Transfers
nEMPTY RDY0
nFULL RDY1 XX
Signifies QuickUSB Read from the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N = 255
t
SRY
t
RYH
IFCLK IFCLK
X
t
DAH
t
SGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
Z
Read Cycle
Addr1
XData0
Addr3 Addr4 Addr[N]
Data1 Data2 Data3
Data[N-1]
Z
t
SGA
t
IFCLK
t
XCTL
Data[N]
…
…X
t
XCTL
Addr0
t
XCTL
…Data4
Addr[N+1] Addr5Addr2 X…
nEMPTY RDY0
nFULL RDY1
X X
Signifies QuickUSB Write to the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N = 255
IFCLK IFCLK
Addr0
X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
Addr1
Data1
Addr2 Addr3 Addr4 …
Addr[N-1] Addr[N]
X
Data2 Data3 Data4
Data[N-1] Data[N]
Z
t
XCTL
t
IFCLK
Addr[N+1]
…
t
XCTL
t
SGA
Data[N+1]
t
SRY
t
RYH
Notes
The valid data transfer length for the Simple I/O model can be calculated with
the following pseudo code:
If (DesiredLength MOD PacketSize <= PreRead) Then
ValidLength = PreRead
Else
ValidLength = DesiredLength
Where:
DesiredLength = The desired transfer length
Valid = The valid transfer length
PreRead = 2 for Byte Wide Mode, 4 for Word Wide Mode
PacketSize = 512 for Hi-Speed, 64 for Full-Speed
High Speed Parallel Port 13

Designing Hardware for QuickUSB
Pipeline I/O Model
This I/O model implements a one-stage read pipeline. It performs transfers
without regard to the readiness of the target hardware. This model is suitable
for hardware that is always ready and that can transfer data as fast as the host
can deliver it. With this I/O model, the data is transferred one clock cycle after
the transfer is made via REN or WEN.
This I/O model is implemented in the QuickUSB firmware file
‘quickusb-pipe1 vX.XX.qusb’ where X.XX is the firmware version number.
The Pipeline I/O model is designed to provide the highest possible data rate
possible with hardware handshaking.
AS A RESULT, THERE ARE CERTAIN INVALID TRANSFER LENGTHS THAT MAY
RESULT IN A FATAL SOFTWARE ERROR WHICH MAY CRASH YOUR COMPUTER.
The simplest valid transfer length calculation is to request data transfer lengths
in multiples of 512 bytes for Hi-Speed mode or 64 bytes for Full-Speed mode.
For applications that cannot use this simplified method, see the Notes section
below.
Command Transfers
IFCLK IFCLK
Addr0X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGA
Signifies QuickUSB Write to
the Data Bus
t
XCTL
t
XCTL
IFCLK IFCLK
Addr0X
t
DAH
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Read Cycle
X
Z
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
t
SGD
t
SGA
Signifies QuickUSB Read
from the Data Bus
t
XCTL
t
XCTL
14 High Speed Parallel Port

Designing Hardware for QuickUSB
Data Transfers
IFCLK IFCLK
X
t
DAH
t
SGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
Z
Read Cycle
Addr1
XData0
Addr2 Addr3 Addr4
Addr[N-1] Addr[N]
X
Data1 Data2 Data3
Data[N-1]
Z
t
SGA
nEMPTY RDY0
nFULL RDY1 X
X
t
IFCLK
t
XCTL
Addr[N+1]
Data[N]
X
X
…
… X
Signifies QuickUSB Read from the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
t
XCTL
Addr0
Data[N-2]
t
XCTL
…
IFCLK IFCLK
Addr0X
t
XGD
CMD_DATA CTL0
REN CTL1
WEN CTL2
nREN CTL3
nWEN CTL4
nOE CTL5
GPIFADR GPIFADR
FD PB, PD
Name Pin
ZData0
Write Cycle
Addr1
Data1
Addr2 Addr3 Addr4 …
Addr[N-1] Addr[N]
X
Data2 Data3 Data4
Data[N-1] Data[N]
Z
t
SGA
nEMPTY RDY0
nFULL RDY1
X
t
XCTL
t
IFCLK
Addr[N+1]
X
X X
…
t
XCTL
t
XGD
t
SGA
Signifies QuickUSB Write to the Data Bus
Full Speed, Byte Wide: N = 63 High Speed, Byte Wide: N = 511
Full Speed, Word Wide: N = 31 High Speed, Word Wide: N=255
Data[N+1]
Notes
The valid data transfer length for the Simple I/O model can be calculated with
the following pseudo code:
If (DesiredLength MOD PacketSize <= PreRead) Then
ValidLength = PreRead
Else
ValidLength = DesiredLength
Where:
DesiredLength = The desired transfer length
Valid = The valid transfer length
PreRead = 2 for Byte Wide Mode, 4 for Word Wide Mode
PacketSize = 512 for Hi-Speed, 64 for Full-Speed
High Speed Parallel Port 15

Designing Hardware for QuickUSB
Slave FIFO I/O Models
The HSPP may also be operated in ‘Slave FIFO’ mode. In this mode, the GPIF
programmable DMA engine is disabled and the QuickUSB FIFOs are controlled
directly by external logic signals. GPIF master mode command/data transfers
are not applicable in slave FIFO mode since the GPIF programmable DMA
engine is disabled. Slave FIFO mode is selected by changing Bits1-0 of the
SETTING_FIFO_CONFIG setting and may be changed at any time. In slave FIFO
mode, data is transferred to and from the QuickUSB FIFOs using the standard
QuickUsbReadData (EP6) & QuickUsbWriteData (EP2) functions. These
endpoints are double-buffered by default. The QuickUSB module can be
configured to perform slave FIFO transfers in either synchronously or
asynchronously by changing Bit 3 of the SETTING_FIFO_CONFIG setting. The
slave FIFO flags may be queried using the SETTING_SLAVEFIFOFLAGS setting.
The following signals are required for slave mode operation:
Pin Name Alternate
Name Description Default Config
IFCLK IFCLK Clock for synchronous I/O Rising edge
FD[15:0] PD[7:0], PB[7:0] Bi-directional FIFO data bus N/A
CTL0 FLAGA Programmable level flag (Half-full) Indexed mode
CTL1 FLAGB FIFO Full Status Flag Indexed mode
CTL2 FLAGC FIFO Empty Status Flag Indexed Mode
PA2 nSLOE Enables the FD outputs for the selected
OUT FIFO Synchronous, Active low
RDY0 nSLRD FIFO read enable/clock Synchronous,
Active low
RDY1 nSLWR FIFO write enable/clock Synchronous,
Active low
PA6 nPKTEND Indicates the end of a short IN packet Synchronous,
Active low
PA7 nSLCS FIFO Chip Select Synchronous,
Active low
PA5:PA4 FIFOADR[1:0] Selects the active FIFO for FD and flags.
00=EP2, 01=EP4,10=EP6, 11=EP8 N/A
Table 3 - Slave FIFO Mode I/O Connections
There are three Slave FIFO I/O Models available with QuickUSB. For Slave FIFO
Modes, no special firmware file is required. Simply use the Simple I/O Model
firmware file and program the SETTING_FIFO_CONFIG bit appropriately to
implement the desired I/O model.
16 High Speed Parallel Port