BlueChip AIP-8d User manual

AIP-8d
8 Channel Analogue
Input Board
User Manual

AIP-8d
User Manual
Document Part N°127-1004.doc
Document Reference AIP-8d\..\127-1004.doc
Document Issue Level 2.0
Manual covers PCBs identified AIP-8d Rev. C
All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or
transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or
otherwise, without the prior permission, in writing, from the publisher. For permission in the UK
contact Blue Chip Technology.
Information offered in this manual is correct at the time of printing. Blue Chip Technology accepts
no responsibility for any inaccuracies. This information is subject to change without notice.
All trademarks and registered names acknowledged.
Blue Chip Technology Ltd.
Chowley Oak, Tattenhall
Chester, Cheshire
CH3 9EX.
Telephone : [phone] Facsimile : 01829 772001.

Amendment History
Issue
Level Issue Date Author Amendment Details
1.0 10/08/95 EGW First approved issue, new front sheet.
1.1 19/12/95 EGW Addition of EMC information to Technical
Section. Errors corrected. Earlier part no.
was 127-036. Filename was
…\User_g.doc.
2.0 07/05/98 SEJ New window front cover and logo. See
ECN

Contents
Blue Chip Technology Ltd. 3.doc
INTRODUCTION ...................................................................................1
ABOUT THE MANUAL ..........................................................................2
CHAPTER 1...........................................................................................3
Installing the AIP-8d...........................................................................3
Base Address ....................................................................................3
Interrupt Selection..............................................................................4
Selecting the A-D Range...................................................................5
Fitting the Card..................................................................................6
CHAPTER 2...........................................................................................7
Making the Right Connections...........................................................7
Input Mode.........................................................................................7
Input Noise.........................................................................................7
Typical Connection to the AIP-8d......................................................8
Analogue Connector (25-Way D-type Plug) ......................................8
CHAPTER 3...........................................................................................9
Hardware Description........................................................................9
µPD71054..........................................................................................9
Timer Modes......................................................................................9
I/O Mapping.....................................................................................10
Function Control Register................................................................11
Starting A-D Conversions................................................................12
Pacer Conversions ..........................................................................12
CHAPTER 4.........................................................................................16
Technical Specifications..................................................................16
APPENDIX A - NUMBERING SYSTEMS............................................20
Binary and Hexadecimal Numbers..................................................20
Base Address Selection...................................................................23
APPENDIX B - PC MAPS....................................................................24
PC/XT/AT I/O Address Map ............................................................24
PC/XT Interrupt Map........................................................................25
PC/AT Interrupt Map........................................................................26
DMA Channels.................................................................................26

Introduction Page 1
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INTRODUCTION
Thank you for purchasing the AIP-8d analogue input card. The card provides the
user with eight channels of 12 bit analogue inputs. The inputs range from
±50mV to ±5 volts, or 0 to +10 volts full scale.
The card features user selectable base address, interrupt source, interrupt level
and an on-board timer. The timer may be used as a pacer clock to control A-D
conversion cycles.

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ABOUT THE MANUAL
This manual is organised into four chapters and two appendices. Each chapter
covers a different aspect of using the AIP-8d. In order to get the best results
from the product, the user is urged to read all chapters, paying particular note to
Chapter 1 which deals with the initial installation of the card. The appendices
may be used for reference at any time.
Chapter 1 Explains how to configure the card to run in your computer via
the user selectable links.
Chapter 2 Details the connections to and from the card and provides
information regarding the type of signals that card is suitable
for use with.
Chapter 3 Gives details of the card’s address mapping and internal
register details allowing the user to write custom software to
control the card.
Chapter 4 Presents the card’s technical specification. Use this section to
determine the card’s suitability for a particular application.
Appendix A Gives a brief introduction to Binary and Hexadecimal
numbering systems for those unfamiliar with the concepts.
Appendix B Lists the IBM-PC I/O address map, interrupt and DMA
allocations and should be used along with Chapter 1 when first
installing the card.

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CHAPTER 1
Installing the AIP-8d
Before installing the card into your computer system, there are a number of user-
configurable links that must be set.
The positioning of these links will depend upon the computer system into which
the card is being fitted. Before fitting any links to the card please read the next
section.
If you are unfamiliar with binary and hexadecimal systems a primer is included in
the appendix.
Base Address
For correct communication between the card and the host computer, the range of
addresses that the card will occupy must be set up. The base address represents
the first address that the card will use. The AIP-8d requires a total of 8 addresses
(including the base address) for correct operation. All Blue Chip Technology
boards are factory set to a default address of 300 hex. Check to ensure that the
base address and the full range of addresses are free for use.
If the addresses are not free another range must be chosen. As a guide, please
use the information contained in appendix to assist in choosing a suitable base
address.
If you are not sure refer to your computer system handbook for information
relating to other peripheral devices possibly already installed (additional
communications card, parallel ports or games ports etc).
If the addresses are available for use then proceed as follows:
• Locate the row header pins (JP1). These pins are marked “BASE” and start
with the pair of pins marked with “08H”. This pair of pins represents the
LOWEST single base address selection. Subsequent pins represent addresses
of increasing value. The HIGHEST single base address link is 200 hex.

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• To select an address, a link position must be left OPEN. Placing a link on a
pair of pins DE-SELECTS that particular address.
Example: To select a base address of HEX 300, the set links as follows:
hex 200
hex 08
BASE ADDRESS
base address selected = HEX 300
(JP1)
Figure 1 Example Base Address Selection
Interrupt Selection
As part of the communication link between the AIP-8d and the host computer, an
interrupt signal may be set to occur whenever valid data is available to the user.
The use of interrupts is not essential but greatly enhances the functionality of the
card. In order for this mode of data transfer to operate correctly, the user must
select an INTERRUPT CHANNEL for the card to use. As with the selection of
base addresses, the chosen interrupt channel must be free for use. The appendix
may be used to identify the Interrupt channels that are normally already in use by
most systems and which ones will probably be free for use.
The AIP-8d allows interrupt selections from 2 to 7. Check that the Interrupt
channel is free for use.
If you are not sure refer to your computer system handbook for information
relating to other peripheral devices possibly already installed (additional
communications cards, parallel ports or games ports etc.).
If the interrupt channel chosen is available for use by the AIP-8d then set up the
card as follows:-
• Locate the row of header pins labelled “JP2”. These pins are marked “IRQ”
and start with Interrupt Signal 2 at the set of pins marked with an rrow.

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• To select an interrupt place a link on the pair of pins corresponding to the
chosen Interrupt Signal. All other pins must be left OPEN.
Example: To select and Interrupt Signal IRQ-5 set the links as follows:-
23 4567
SET INTERRUPT (JP2)
INTERRUPT SELECTED = IRQ5
Figure 2 Example Interrupt Signal Selection
Selecting the A-D Range
The full scale measurement range for the analogue inputs is set by a combination
of user configurable links.
JP3 and JP4 set the mode of operation for the A-D. Use the table below to
determine the jumper settings for the required input scaling range.
Gain
JP3 A-D Setting (J4) Full Scale Range
x 1 +5 volts +5 volts
x 1 +10 volts +10 volts
x 1 ±5 volts ±5 volts
x 10 +5 volts + 500mV
x 10 +10 volts + 1 volt
x 10 ±5 volts ±500 mV
x 100 +5 volts +50mV
x 100 +10 volts +100mV
x 100 ±5 volts ±50 mV
Figure 3 Configuring the A-D

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Figure 4 Setting the Input Gain and A-D Configuration
Fitting the Card
Once all links have been set, the card can be installed into the host computer.
Ensure that the power is turned off and follow all the manufacturer’s instructions
for opening the computer. Locate a free expansion slot in the machines and plug
the card firmly into it. Screw the bracket in place and re-assemble the computer.
NOTE: To avoid interference from other cards in the computer, if possible
locate the card away from “noisy” cards such as hard disk controllers and
network cards.
JP4 JP4 JP4
±5 VOLTS
+ 10 VOLTS+ 5 VOLTS
A-D SETTINGS (JP4)
GAIN = 1
JP3
GAIN = 10
JP3
GAIN = 100
JP3
A-D SETTINGS (JP3)

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CHAPTER 2
Making the Right Connections
This chapter explains the input configuration of the AIP-8d, provides typical
connection examples and gives the pin-outs for the analogue connector.
Input Mode
The input circuitry of the AIP-8d is configurable to handle signals ranging from
±50mV to ±5 Volts in bipolar modes and up to +10 Volts in uni-polar mode. All
modes are single ended.
A single ended input configuration measures the voltage applied to the input with
reference to the signal ground connection. This ground connection is common to
all input signals. With this input configuration the maximum voltage range that
the card can measure is +10 volts.
Input Noise
When using the 50mV full scale, special care should be exercised in sheilding
input cables against spurious noise. The A-D converter used on the AIP-8d is
extremely fast, requiring a mere 3µS to complete a 12 bit conversion. In addition
on the 50mV range, the sensitivity at the input terminals will be approximately
12µV per bit. The card is therefore very susceptible to interference, due to the
noisy environment within the host computer and some noise in the lower order
bits will be present in the acquired signal. This noise will be present, to a lesser
degree, on all ranges and the high speed of the A-D.

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Typical Connection to the AIP-8d
vvoltage source
25 way connector
14
1
single ended input
channel 1
Figure 5 Typical Connection to KFA8I
Analogue Connector (25-Way D-type Plug)
This connector is located at the front of the card and protrudes through the rear
bracket. All analogue inputs are presented at this connector.
PIN SIGNAL PIN SIGNAL
1 Channel 1 Input 14 Analogue Grid
2 Channel 2 Input 15 Analogue Grid
3 Channel 3 Input 16 Analogue Grid
4 Channel 4 Input 17 Analogue Grid
5 Channel 5 Input 18 Analogue Grid
6 Channel 6 Input 19 Analogue Grid
7 Channel 7 Input 20 Analogue Grid
8 Channel 8 Input 21 Analogue Grid
9 No Connection 22 No Connection
10 No Connection 23 Digital Grid
11 Digital Grid 24 Conversion Start/Stop
12 No Connection 25 Digital Grid
13 Analogue Grid
Conversion Start/Stop Signal Input:
+5V enables the conversion process
0 V disables the conversions

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CHAPTER 3
Hardware Description
This chapter presents details of the AIP-8d I/O mapping along with internal
register details. Details of the registers for the µPD71054 timer chip are not
given in detail, only brief functional description is provided. For the full details,
the user is referred to the manufacturer’s data book.
µPD71054
The µPD71054 timer chip contains three independent 16 bit counters which may
be operated in a variety of modes. Presented here is a brief summary of some of
the modes possible by programming the timers internal registers.
There are five basic modes of operation each providing a different output signal
from the “Tout” pin of the device. For the AIP-8d timers 0, 1 and 2 are connected
in series to provide a longer delay period.
Timer Modes
The following modes of operation are possible by programming the control
register within the µPD71054 .
MODE 0
When programme, the output will be set LOW. When the counter decrements
from the value loaded into the count registers to zero, the output pin will go
HIGH. It will remain high until the count is re-programmed into the count
registers.
MODE 1
When the count registers are programmed, the output pin will be set HIGH.
When a LOW going signal is applied to the gate input, the count starts and the
output will immediately fall LOW. After the time period programmed into the
count registers has elapsed, the output pin will return HIGH.

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MODE 2
This mode operates as a frequency divider with a roughly 1:1 mark-space ratio.
When programme the output pin will toggle HIGH and LOW alternatively each.
If the count value programmed is an odd number then the counter will reach zero
before the output pin toggles.
MODE 4
This mode is similar to Mode 2 but the output pin pulses when the count reaches
zero instead of 1.
MODE 5
As Mode 4 except count sequence is triggered by the gate line.
I/O Mapping
Address Function R/W
Base + 0 Timer 0 Count Register R/W
Base + 1 Timer 1 Count Register R/W
Base + 2 Timer 2 Count Register R/W
Base + 3 Timer Control Register W
Base + 4 Function Control Register W
Base + 5 A-D Start Convert W
Base + 6 A-D Read Data R
Base + 7 Status Register R
Figure 6 I/O Mapping for AIP-8d

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Function Control Register
This register controls various aspects of the AIP-8d operations such as input
channel selection, conversion mode etc.
Bits 4-7
Bit 7 Bit 6 Bit 5 Bit 4 Selects
1 0 0 0 Channel 1
1 0 0 1 Channel 2
1 0 1 0 Channel 3
1 0 1 1 Channel 4
1 1 0 0 Channel 5
1 1 0 1 Channel 6
1 1 1 0 Channel 7
1 1 1 1 Channel 8
1 0 0 0 Not Used
1 0 0 1 Not Used
1 0 1 0 Not Used
1 0 1 1 Not Used
1 1 0 0 Not Used
1 1 0 1 Not Used
1 1 1 0 Not Used
1 1 1 1 Not Used
0 x x x None
x = Don’t care
Analogue Input Channel Selection Bits
Bit 3 is not used. It’s programmed value does not affect the operation.
Bit 2 controls the Pacer Clock. The clock is disabled if bit 3 is set LOW and
enabled when set HIGH. The bit must be set high in order to program
the timer with values and for it to run. Setting this bit low prevents A-D
conversions from occurring and also stops the timer from being loaded
with new values.

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Bit 1 determines whether the input channels are automatically scanned as data
conversions occur or whether channel selection is via software
command. In automatic mode, a conversion occurs on every eighth
pacer clock “tick” followed by the generation of an interrupt from the
data ready signal. At this point the host computer reads the data from
the A-D. It is the read operation that selects the next channel ready for
the next start convert signal from the pacer. Setting bit LOW selects
“manual” or software selection of the input channel, setting it HIGH
selects automatic channel selection.
NOTE: When using the pacer timer conversions and auto scanning, any
interrupt service routine or data reading sub-routine must execute in less
time than the period between 8 pacer “ticks”.
Bit 0 selects whether conversions should occur automatically ecert 8 pacer
clock ticks or only when commanded to do so by software. Setting bit 0
LOW selects conversion using the pacer clock. Setting it HIGH selects
software controlled conversions.
The software signal required to start the conversion is an I/O write to
Base Address +5. Upon receipt of a write signal, 8 bits of the pacer
clock are allowed to occur to complete one conversion cycle.
Starting A-D Conversions
A-D conversions may be started either by the pacer clock or via software WRITE
to Base Address +5. Pacer driven conversion are straightforward provided that
any data service routine MUST be completed within 8 pacer clock timer periods.
For software start conversions, it is also necessary to program the timer. The
data to the timer is loaded with bit 2 of the function control register high. For
specific details on programming the timer device for use on AIP-8d see the next
section.
Pacer Conversions
The internal logic of the AIP-8d provides one conversion result for every 8 ticks
of the pacer clock. When working out sampling rates it is important to remember
this detail and this program the pacer clock at 8 times the desired sampling rate.

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I/O Start Convert
When issuing start convert signals by I/O note that from the point of issuing the
start convert command to the point where valid data is available is 8 pacer clock
periods. The start convert signal in this mode enables a burst of pacer clocks to
drive the conversion cycle.
When using this mode therefore, the pacer clock time values should be as short as
possible to avoid unduly long times between the start convert signal and the data
ready flag.
Reading the A-D
Once the conversion cycle is complete the user has a choice of signals to flag that
data is ready to be read from the card.
Interrupts
Using the interrupt line represents the most efficient way to acquire data from the
card since the controlling software is not required to remain in a loop reading the
card waiting for data to become available for use. To use the interrupt facility,
an interrupt handler routine must be written and installed prior to
running the main acquisition software.
Data Ready Flag
When the A-D has valid data, the “Data Ready Flag” goes to a logic low
condition. The flag will stay low until both bytes of the A-D value have been
read whereupon it will return high. This bit may be polled in order to determine
when the data should be read.
This method of operation ties the machine up for most of the time looking for the
data ready flag to change state.

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A-D Data Format
The A-D is a 12 bit resolution device although the card occupies only an 8 bit
slot. Because of this, two reads to the A-D are required to retrieve all of the data.
Both reads are to the same address (at Base Address +6) and provide the value
LOW BYTE first followed by HIGH BYTE. It is not necessary to mask the
upper nibble of the high byte since this always returns a value of zero.
Channel Scanning
When scanning through input channels, there is a limit to how quickly a channel
may be selected and then read. To allow for settling times of various
components, a scan rate not faster than 12µS is recommended. If the scan rate is
too quick, data values returned will not be as expected since the input will not
have had time to settle to the proper value before the A-D starts converting.
Programming the Pacer Clock
Irrespective of whether the A-D conversions are driven solely by the pacer or by
an I/O command, the µPD71054 timer must be programmed. The timer chip is
driven by a 4MHz clock signal which gives a timer resolution of 250nS. For
most timer modes, however, the minimum count period is 2 clock cycles. This
means the effective minimum time for a single counter is 500nS. For the AIP-8d,
all three timers are cascaded such that only the first timer (Timer 0) in the chain
is fed from the 4MHz clock. Timer 1 clock input signal is the output from Timer
0 and Timer 2 clock input signal is the output from Timer 1.
The minimum time period therefore for the pacer clock system as a whole is 2µS,
with the maximum being 2.23 years.

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To calculate the time period for the pacer clock, work out each of the three timer
sections individually, taking the clock value for each as the output from the
preceding one.
Timer 0: [CLOCK (4 MHz)/n] Hz
Timer 1: [CLOCK(out from Timer 0)/n] Hz
Timer 2: [CLOCK(out from Timer 1)/n] Hz, or
1 / [CLOCK(out from Timer 1)/n] seconds
“n” is the decimal value loaded to the counter
The pacer clock value to the A-D is the value obtained for the Timer 2
calculation. The sampling TIME for the system is 8 times the calculated time
period of the pacer.
NOTE: A pacer rate of less than 4µS is not permitted since this approaches
the conversion time for the A-D.

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CHAPTER 4
Technical Specifications
ANALOGUE INPUTS
Number Of Analogue Input Channels 8 (Single Ended)
Voltage Input Range From ±50 mV to +10 Volts
or, ±5 Volts
Programmable Gains x1, x10, x100
System Conversion Time: 12µS min
A-D Conversion Time: 3µS
Resolution 12 bit
Measurement Accuracy
+5V Range 0.1% FS +/- 4 Counts
+10V Range 0.1% FS +/- 4 Counts
±5V Range 0.1% FS +/- 4 Counts
Input Common Mode Range ±12 Volts
Data Transfer Modes I/O Port
Data Ready Flags Interrupt or Polling
Interrupt Channels IRQ-2 to -7