Burroughs -B9489 Flexible Disk Drive Technical Manual
TABLE
OF
CONTENTS (Continued)
Section 5 (Continued)
Fascia . . .
Receiver. . . . • . .
Stepper Motor and Carriage .
Head Solenoids
I..arnps
. . . . . . . . . . .
Pressure Pads . .
..'
Drive Belt . .
Page
5-1
5-1
5-1
5-2
5-2
5-2
5-2
Section 5 (Continued)
Preventive Maintenance Fuide. . . . .
Fault
Finding.
. . . . .
Recovery
of
Conta~inated
Disks.
Certified Disks. . . . . . . . . .
Section 6
INSTALLATION PROCEDURES
Installation Procedures. . .
LIST
OF
ILLUSTRATIONS
Figure
Page
Figure
I-I
Complete Unit.
1-1
2-16
Read Block Diagram.
1-2
Master/Slave Configuration.
1-2
2-17
Read Channel Test Points .
1-3
Major Assemblies.
1-2
2-18
Schematic -Read Channel
1-4
Stepper Motor and Leadscrew.
1-3
2-19
PLL/Data Relationship.
1-5
Carriage Assembly
1-4
2-20
Data Decode Timing.
1-6
Diagrammatic Recording Head
1-4
2-21
Schematic -Read Data Decode .
1-7
Magnetic Head Layout .
1-5
2-22
Worst
Case
Peak Shift
1-8
Head Schematic
1-5
1-9
Track Format (Upper Side)
1-5
3-1
Logic Example
1-10
Track Format (Lower Side)
1-5
3-2
SN7400
QJ.lad
2-Input NAND Gate .
1-11
Sector Configuration
1-6
3-3
SN7402 Quad 2-Input NOR Gate
1-12
Encoding Comparison
1-6
3-4
SN7404 HEX Inverter
~
1-13
Disk.
1-8
3-5
SN7405 HEX Inverter with Open
1-14
Jacket
1-8
Collector
Output
.'
1-15
Operator Controls
1-9
3-6
SN7410 Triple 3-Input NAND Gate.
1-16
Common Electronics
1-11
3-7
SN7420 Dual 4-Input NAND Gate .
1-17
Block Diagram.
1-12
3-8
SN7426 Quad 2-Input High Input
Voltage Interface NAND Gate with Open
2-1
Positioner Mechanics (Top View)
2-1
Collector Output
2-2
. Carriage (Side View) .
2-2
3-9
SN7438 Quad 2-Input Interface NAND
2-3
Positioner Electronics Block Diagram .
2-3
Gate with Open Collector Output .
2-4
Schematic -Address Counter/
3-10
SN74132 Quad 2-Input NAND Gate
Comparator
2-5
-Schmitt Triggers
2-5
Schematic -Positioner Clock and
3-11
SN7427 Triple 3-Input NOR Gate
Stepper Motor Drivers.
2-7
3-12
SN75452 Dual NAND Driver .
2-6
Stepper Motor. ,
2-8
3-13
SN7474 Dual D-type Flip Flop
2-7
Positioner Clock Start-Up .
2-8
3-14
ITT96015D Retriggerable Monostable
2-8
Schematic - Head Load Control.
2-12
Multivibrator.
2-9
Schematic -Index/Sector
J:lulses.
2-13
3-15
9602 Dual Retriggerable, Resettable,
2-10
Index and Sector
Generation.
2-14
Monostable Multivibrator.
2-11
Write Block Diagram.
2-15
3-16
8284 Hexadecimal Up/Down
Counter.
2-12
Write Timing
2-16
3-17
9308 Dual 4-Bit Latch .
2-13
Schematic -Write Data Encoder.
2-17
3-18
9322 Quad 2-Input Multiplexor .
2-14
Schematic -External Interface
Logic.
2-19
3-19
9324 5-Bit Comparator.
2-15
Schematic -Write Driver .
2-20
3-20
733 Differential Amplifier.
vi
page
5-2
5-2
5-2
5-2
6-1
Page
2-21
2-21
2-22
2-23
2-23
2-24
2-25
3-1
3-2
3-~
3-2
3-3
3-3
.3-3
3-3
3-4
3-4
3-4
3-4
3-5
3-5
3-5
3-6
3-6
3-6
3-6
3-7