BVM PMCDIO64 User manual

Manual P/N 854-11100 BVM Limited,
Hobb Lane,
Hedge End,
Southampton,
SO30 0GH, UK.
TEL: [phone]
FAX: [phone]
E-MAIL: [e-mail]
WEB: http://www.bvmltd.co.uk
User's Manual
PMCDIO64
64-bit Digital I/O
PMC Module
Board Revision A
Manual Revision B 04 April 2001
This material contains information of proprietary interest to BVM Ltd. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be
copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person
except to meet the purposes for which it was delivered.

This page is intentionally left blank.

i
DISCLAIMER
The information in this document has been checked and
is believed to be entirely reliable, however no
responsibility is assumed for inaccuracies. BVM Ltd.
reserves the right to make changes and/or improvements
in both the product and the product documentation without
notice. BVM Ltd. does not assume any liability arising out
of the application or use of any product described herein;
neither does it convey any licence under its patent rights
or the rights of others.
USE OF PRODUCT
This product has been designed to operate in a PMC
compatible electrical environment. Insertion and removal
of the module or cable(s) from the carrier board must not
be done whilst in a powered condition.
Do not lever out any devices from the product, which uses
surface-mounted devices extensively, as these can be
fractured by excessive force.
This product uses devices sensitive to static electricity.
Ensure adequate static electricity precautions are
observed when handling the product and associated
devices.
RF. INTERFERENCE
This product complies with European Council Directive
89/336/EEC (EMC directive), and conforms to EN55022 :
1994 Class B (Limits and methods of measurement of
radio interference characteristics of information
technology equipment) and EN50082-1 : 1997
(Electromagnetic compatibility - Generic immunity
standard, Part 1: residential, commercial and light
industry) when used in accordance with the BVM EMC
Guidelines Manual part number 454-77000 (available on
request from BVM Ltd.).
GENERAL NOTICES
UNPACKING AND INSPECTION
This product contains components which are
susceptible to static discharge, and should be
handled with appropriate caution.
Upon receipt of this product, visually inspect the board for
missing, broken or damaged components and for physical
damage to the printed circuit board or connectors. This
product was shipped in perfect physical condition. Any
physical damage to the product is the responsibility of the
shipping carrier and should be reported to the carrier's
agent immediately.
RETURN OF GOODS
Before returning a product for repair, verify as well as
possible that the suspected unit is at fault. Then call BVM
Ltd. for a Customer Return (CR) number. Carefully
package the unit, in the original shipping carton if this is
available, and ship prepaid and insured, preferably by
courier, with the CR number written on the outside of the
package.
Include a return address and the telephone number of a
technical contact, and a detailed description of the
observed fault. For out-of-warranty repairs, a purchase
order for repair charges must accompany the return. BVM
Ltd. will not be responsible for damage due to improper
packaging of returned items. Out of warranty repairs can
be arranged, and will be charged on a material and labour
basis, subject to a minimum repair charge. Return
transportation and insurance will be charged as part of the
repair and is in addition to the minimum charge.
SOFTWARE LICENCE NOTICE
Any software that is provided as Copyright BVM Ltd. is
proprietary and confidential property of BVM Ltd., and
each single copy is given on the agreed understanding
that it is licensed for use on product combinations
supplied by BVM Ltd. or their appointed distributors only.
The software product may not be copied (except for
backup purposes), given away, rented, loaned,
reproduced, distributed or transmitted in any way or form,
in whole or in part, without written permission of BVM Ltd.
This applies to any merged, modified or derivative version
of the software including, but not limited to, versions
produced by customising, translating, reverse
engineering, de-compiling or disassembly.
This licence may be automatically terminated without
notice if any of its provisions are breached. Reasonable
legal costs may be awarded to the prevailing party in
connection with this licence agreement. Use of, or
accepted delivery of these products shall constitute your
acceptance of the provisions of this licence agreement.
WARRANTY
A) BVM Ltd. warrants that the articles furnished hereunder
are free from defects in material and workmanship for one
year after the date of shipment.
B) All warranties and conditions, express and implied,
statutory and otherwise, as to the quality of the goods or
their fitness for any purpose are hereby excluded and with
the exception of liability for death or personal injury
caused by negligence as defined in the Unfair Contract
Terms Act 1977 the seller shall not be liable for any loss,
injury or damage arising directly or indirectly from the use,
application or storage of such goods.
C) Subclause (B) above shall not apply where the buyer
deals as a consumer as this expression is defined in the
Unfair Contract Terms Act 1977.
D) The liability of BVM Ltd. hereunder shall be limited to
repair or replacement at the manufacturers discretion of
any defective unit. Equipment or parts which have been
subject to abuse, misuse, accident, alteration, neglect,
unauthorised repair or installation are not covered by this
warranty. BVM Ltd. shall have the right of determination
as to the existence and cause of any defect.
E) The warranty period of the replacement or a repaired
product or part shall terminate with the termination of the
warranty period with respect to the original product or part
for all replacement parts supplied or repairs made during
the warranty period.
F) Although BVM Ltd. offer a high level of technical
support and advice, due to the complex nature and wide
application of product configurations it is the
responsibility of the purchaser to be satisfied at the time
of purchase that the products are suitable for the final
application.
G) The term 'Software' used herein is defined as 'any
program data or code in source or binary format recorded
in or on any readable device or media'.
H) BVM Ltd. will effect all reasonable effort to resolve
accepted reproducible software errors reported within 12
months of purchase. Acceptance of an error shall solely
be based on conformance to supporting specifications.
Proper operation of earlier releases is not guaranteed.
NOTICES
Copyright 2000 by BVM Ltd.
All trademarks are acknowledged to their respective
owners.

ii
This page is intentionally left blank.

iii
Table Of Contents
Contents Page
1. Introduction.......................................................................................................................................1
1.1 Scope.........................................................................................................................................1
1.2 PMCDIO64 Part Numbers..........................................................................................................1
1.3 PMC I/O Board Part Numbers....................................................................................................1
2. Overview...........................................................................................................................................2
2.1 Board Layout..............................................................................................................................2
2.2 Features.....................................................................................................................................3
2.3 Applications................................................................................................................................3
3. Operation..........................................................................................................................................4
3.1 Block Diagram............................................................................................................................4
3.2 PCI9030 PCI Interface ...............................................................................................................4
3.3 Main Logic..................................................................................................................................5
3.3.1 Input Register..........................................................................................................................5
3.3.2 Output Register.......................................................................................................................5
3.3.3 Change Flags Register...........................................................................................................5
3.3.4 Direction Register ...................................................................................................................5
3.3.5 Function Register....................................................................................................................5
3.3.6 Control & Status Register.......................................................................................................5
3.3.7 Watchdog Trigger Register ....................................................................................................5
3.3.8 Watchdog Timer Register ......................................................................................................5
3.3.9 Watchdog Status Register......................................................................................................5
3.4 I/O Interface ...............................................................................................................................6
3.5 93CS56 EEPROM......................................................................................................................6
3.6 18V256 EEPROM ......................................................................................................................6
4. Installation.........................................................................................................................................7
5. Configuration ....................................................................................................................................8
5.1 Link Positions.............................................................................................................................8
5.2 Link Definitions...........................................................................................................................8
5.2.1 LK1 to LK8 I/O Pull-Up Enable...............................................................................................8
5.2.2 LK9 to LK12 P5 Common Select ...........................................................................................9
6. Connections....................................................................................................................................10
6.1 Front Panel Connector.............................................................................................................10
6.2 Rear I/O Connector..................................................................................................................11
6.3 PMC I/O Board.........................................................................................................................11
6.4 PCI Connections ......................................................................................................................12
7. Programming..................................................................................................................................13
7.1 PCI Configuration Details.........................................................................................................13
7.2 Address Map............................................................................................................................13
7.3 Register Descriptions...............................................................................................................13
7.3.1 Input Register........................................................................................................................13
7.3.2 Output Register.....................................................................................................................13
7.3.3 Change Flags Register.........................................................................................................13
7.3.4 Direction Register .................................................................................................................14
7.3.5 Function Register..................................................................................................................14
7.3.6 Status & Control Register.....................................................................................................14

iv
7.3.6.1 Watchdog Interrupt Enable (Bit 3: WINEN) ........................................................14
7.3.6.2 Global Output Enable (Bit 4: GOPEN)................................................................14
7.3.6.3 Internal Watchdog Enable (Bit 6: IWDEN)..........................................................14
7.3.6.4 Watchdog Status (Bit 7: WDGST) ......................................................................14
7.3.6.5 Input Lock (Bit 12: INLOCK) ...............................................................................14
7.3.6.6 Output Hold (Bit 13: OUTHLD) ...........................................................................14
7.3.6.7 Interrupt On Change-of-State Enable (Bit 14: IOCEN).......................................14
7.3.6.8 Interrupt On Change-of-State Status (Bit 15: IOCST).........................................14
7.3.7 Watchdog Trigger Register ..................................................................................................15
7.3.8 Watchdog Timer Register ....................................................................................................15
7.3.9 Watchdog Status Register....................................................................................................15
7.4 Interrupts..................................................................................................................................15
7.5 Windows®Driver Disc..............................................................................................................15
8. Specification ...................................................................................................................................16
8.1 On-Board Functions.................................................................................................................16
8.1.1 PCI9030 PCI Interface..........................................................................................................16
8.1.2 SpartanXL FPGA..................................................................................................................16
8.1.3 Local Clocks..........................................................................................................................16
8.2 Board Configuration .................................................................................................................16
8.3 I/O Interface .............................................................................................................................16
8.4 PMC Interface ..........................................................................................................................16
8.5 Operating Environment ............................................................................................................16
Appendix A - Data Sheets & Manual References...............................................................................17
A.1 PCI9030 PCI Interface .............................................................................................................17
A.2 Spartan-XL FPGA ....................................................................................................................17
A.3 74ABT16245A Buffers .............................................................................................................17
A.4 PMC Specification....................................................................................................................17
List of Figures
Figure Page
Figure 1 Board Layout Topside...............................................................................................................2
Figure 2 Board Layout Underside ...........................................................................................................2
Figure 3 Block Diagram...........................................................................................................................4
Figure 4 Link Positions............................................................................................................................8
Figure 5 Connector Pin-outs for 9-pin D-type........................................................................................11

PMCDIO64
Copyright 2000 BVM Ltd.
1
1. Introduction
1.1 Scope
This manual provides:-
A getting started guide.
Configuration details.
A user reference guide.
Details of implementation specific considerations for major devices.
General Hardware Description.
This user manual does not provide:-
Detailed data on the operation of the PCI interface or FPGA logic devices.
Detailed data on the operation of the configuration EEPROMS.
Details on the content of the PMC specification.
Details on the Windows®device driver.
Information is provided to allow the module to be integrated into a system and configured by a system
engineer. This User's Manual is intended for use by system integrators, service personnel, software
engineers and end users.
This User's Manual covers details of the PMCDIO64 only, which is one in a range of PMCDIO digital
I/O and PMCCTR counter/timer I/O PMC modules from BVM.
Unless otherwise stated, address information is in hexadecimal notation.
1.2 PMCDIO64 Part Numbers
Part Number Type Description
853-11111 PMCDIO64 64-bit TTL digital I/O & change-of-state
A Windows®driver disc is available containing the digital I/O drivers and BVM installation files.
Part Number Description
850-11150 Windows®Driver Disc
1.3 PMC I/O Board Part Numbers
An 8 Port PMC I/O Board is available for the PMCDIO64 converting from the I/O connections to
standard 9-pin D-type connectors.
Part Number Description
853-19900 8 Port PMC I/O Board rear straight
853-19901 8 Port PMC I/O Board rear right-angle
853-19902 8 Port PMC I/O Board front straight
853-19903 8 Port PMC I/O Board front right-angle

PMCDIO64
Copyright 2000 BVM Ltd.
2
2. Overview
2.1 Board Layout
Figure 1 Board Layout Topside
Figure 2 Board Layout Underside

PMCDIO64
Copyright 2000 BVM Ltd.
3
2.2 Features
•64-bits of TTL level compatible I/O.
•I/O byte selectable as input or outputs.
•Inputs latched on 33MHz PCI clock.
•Interrupt on change-of-state.
•Change-of-state double-sampled on 33Mhz PCI clock.
•Watchdog period programmable 125ms to 2sec.
•Watchdog interrupt.
•Watchdog tri-states outputs.
•Front panel and rear I/O connections.
•Conforms to PMC standard IEEE P1386.1/Draft 2.3 9th October 2000.
•Conforms to PCI Local Bus Specification Revision 2.2.
2.3 Applications
•Interfacing industrial equipment.
•General purpose industrial I/O.
•32-bit or 64-bit data I/O.
•Fail-safe control.

PMCDIO64
Copyright 2000 BVM Ltd.
4
3. Operation
3.1 Block Diagram
PLX PCI9030
PCI to Local Bus
Interface
PCI Bus
16 bit local bus
Xilinx SpartanXL
for
Logic Functions
Config.
EEPROM
Config.
EEPROM
Watchdog
Xtal
32.768kHz
5V
tolerant
3.3V
Buffer
External
Connection
Figure 3 Block Diagram
3.2 PCI9030 PCI Interface
The PMCDIO64 uses a PLX PCI9030 PCI interface to a 16-bit local bus on-board. The general
features of the PCI9030 are listed below.
•PCI Local Bus Specification V2.2-compliant 32-bit, 33 MHz Bus Target Interface Device
enabling PCI Burst Transfers up to 132 MB/s.
•PCI Bus Power Management Interface Specification V1.1 compliant.
•PCI Local Bus Specification V2.2 Vital Product Data (VPD) configuration support.
•PCI Target Programmable Burst Management.
•PCI Target Read Ahead mode.
•PCI Target Delayed Read mode.
•PCI Target Delayed Write mode.
•Programmable Interrupt Generator/Controller.
•Two programmable FIFOS for zero wait state burst operation.
•Flexible Local Bus provides 32-bit Multiplexed or Non-Multiplexed Protocol for 8, 16, or 32-bit
Peripheral and Memory devices.
•Serial EEPROM interface.
•Nine programmable General Purpose I/O (GPIOS).
•Five programmable Local Address spaces.
•Four programmable independent chip selects.
•Programmable Local Bus wait states.
•Programmable Local Read pre-fetch mechanism.
•Local Bus can run asynchronously to the PCI Bus.
•Two programmable Local-to-PCI interrupts.
•Endian Byte Swapping.
Note that not all of these features are pertinent to the PMCDIO64 - see section "A.1 PCI9030 PCI
Interface (on page 17)" for further details of the device.

PMCDIO64
Copyright 2000 BVM Ltd.
5
3.3 Main Logic
The PMCDIO64 uses a Xilinx SpartanXL FPGA connected to the 16-bit local bus to provide the on-
board logic functions as described below.
3.3.1 Input Register
A 64-bit Input Register containing a latched version of the I/O pins on the logic device. The signal is
latched by the 33MHz PCI clock.
3.3.2 Output Register
A 64-bit Output Register whose contents are output to valid output pins.
3.3.3 Change Flags Register
A 64-bit Change Flags Register where each bit indicates an input that has changed state since
interrupt on change-of-state was enabled.
3.3.4 Direction Register
An 8-bit Direction Register where each bit corresponds to a group of 8 I/O bits. If the corresponding bit
is set to 1 output is enabled otherwise input is enabled.
3.3.5 Function Register
An 8-bit Function Register which contains the low byte of the PCI Subsystem Device ID - used to
determine the type of board fitted from the PMCDIO and PMCCTR range.
3.3.6 Control & Status Register
A 16-bit Control & Status Register where the bits are used to control and monitor the status of the
following functions.
•Watchdog Interrupt Control.
•Global Output Control.
•Watchdog Enable Control.
•Watchdog Status.
•Lock Inputs Control.
•Hold Outputs Control.
•Change-of-State Interrupt Control.
•Change-of-State Status.
3.3.7 Watchdog Trigger Register
A 8-bit register in which bit 0 must be written alternately 0 and 1 within ±25% of the watchdog refresh
period.
3.3.8 Watchdog Timer Register
An 8-bit register defining the watchdog refresh period: 125ms; 250ms; 500ms; 1sec or 2sec.
3.3.9 Watchdog Status Register
An 8-bit register which indicates if the watchdog has timed out.

PMCDIO64
Copyright 2000 BVM Ltd.
6
3.4 I/O Interface
The 64-bits of I/O are connected to the outside world via 74ABT16245A buffer devices with 2 bytes
per device with separate output enables. These buffer devices have a 32mA source capability or
64mA sink capability when connected to outside signals. The I/O signals may be biased with 10KΩ
pull-up resistors on a per byte basis.
There are 4 common connections which can be used as power sources or ground returns for the I/O
signals - see section "5.2.2 LK9 to LK12 P5 Common Select (on page 9)" for further details.
3.5 93CS56 EEPROM
The PMCDIO64 is fitted with a 93CS56 EEPROM which is supplied pre-programmed by BVM. The
contents of this EEPROM are read by the PCI9030 on coming out of reset and are used to set up the
control registers after reset, configuring the PCI interface configuration, PCI Device/Vendor ID's &
various other board specific parameters. See section "7.1 PCI Configuration Details (on page 13)" and
"A.1 PCI9030 PCI Interface (on page 17)" for further details.
3.6 18V256 EEPROM
The PMCDIO64 is fitted with a 18V256 EEPROM, which is supplied pre-programmed by BVM. The
contents of this EEPROM are read by the SpartanXL FPGA on power up and are used to initialise the
logic functions in the FPGA.

PMCDIO64
Copyright 2000 BVM Ltd.
7
4. Installation
1. PMC modules should only be installed when the host carrier board is in a powered-off condition to
avoid damage to the PMC module and host carrier board.
2. After removing any blanking panels on the host carrier front panel, the PMC module should be
offered up to the host carrier site and the front panel carefully positioned through the host carrier
front panel opening, taking care not to damage the EMC gasket on the PMC module front panel.
3. The PMC module should be fixed to the host carrier using four M2.5 x 6mm pan-head screws into
the four fixing holes provided (two on the front panel and two on the spacers).
4. There is no voltage keying on the PMCDIO64, it will work in both +3.3V and +5V host carriers.
5. The PMCDIO64 can be used with a BVM supplied connecting lead to standard 9-pin D-type
connectors, or a user supplied alternative.
6. Links must be set accordingly for I/O pull-up enable/disable and common select - see section "5.2
Link (on page 8)".
7. The installation can be tested with the example software on the Windows®Driver Disc - see
section "7.5 Windows®Driver Disc (on page 15)".

PMCDIO64
Copyright 2000 BVM Ltd.
8
5. Configuration
5.1 Link Positions
Figure 4 Link Positions
5.2 Link Definitions
The following link definitions refer to the link positions as the shown above, i.e. with the PMC Front
Panel connector to the right. Pin 1 is denoted by a filled in pin position. Link positions marked with a !
below show the default configuration.
5.2.1 LK1 to LK8 I/O Pull-Up Enable
The digital I/O signals to the PMCDIO64 may be pulled-up to +5V via 10KΩresistor networks in
groups of 8 if link selected. See the table below for link to I/O equivalence.
OPERATIONLINK FITTED OMITTED
LK1 Pull-up IO0 - IO7 via 10KΩ!IO0 - IO7 NOT pulled-up
LK2 Pull-up IO8 - IO15 via 10KΩ!IO8 - IO15 NOT pulled-up
LK3 Pull-up IO16 - IO23 via 10KΩ!IO16 - IO23 NOT pulled-up
LK4 Pull-up IO24 - IO31 via 10KΩ!IO24 - IO31 NOT pulled-up
LK5 Pull-up IO32 - IO39 via 10KΩ!IO32 - IO39 NOT pulled-up
LK6 Pull-up IO40 - IO47 via 10KΩ!IO40 - IO47 NOT pulled-up
LK7 Pull-up IO48 - IO55 via 10KΩ!IO48 - IO55 NOT pulled-up
LK8 Pull-up IO56 - IO63 via 10KΩ!IO56 - IO63 NOT pulled-up

PMCDIO64
Copyright 2000 BVM Ltd.
9
5.2.2 LK9 to LK12 P5 Common Select
The front panel I/O connector P5 has 68 connections which allow 4 pins to be used as commons for
the other 64 I/O signal connections. The commons may be individually selected as +5V (fused), GND
or not-connected.
OPERATIONLINK FITTED 1 TO 2 FITTED 2 TO 3 OMITTED
LK9 COM0 +5V !COM0 GND COM0 N/C
LK10 COM1 +5V !COM1 GND COM1 N/C
LK11 COM2 +5V !COM2 GND COM2 N/C
LK12 COM3 +5V !COM3 GND COM3 N/C

PMCDIO64
Copyright 2000 BVM Ltd.
10
6. Connections
6.1 Front Panel Connector
The I/O signals are available through a 68-pin SCSI-III style connector fitted to the front of the board -
the pin-out is shown below. If a PMC I/O board is used the D-type connector pin-out equivalents are
also shown below - see section "6.3 PMC I/O Board (on page 11)" for further details.
Pin No. Signal D-type D-type Signal Pin No.
1 IO0 P1-1 P5-1 IO32 35
2 IO1 P1-6 P5-6 IO33 36
3 IO2 P1-2 P5-2 IO34 37
4 IO3 P1-7 P5-7 IO35 38
5 IO4 P1-3 P5-3 IO36 39
6 IO5 P1-8 P5-8 IO37 40
7 IO6 P1-4 P5-4 IO38 41
8 IO7 P1-9 P5-9 IO39 42
9 IO8 P2-1 P6-1 IO40 43
10 IO9 P2-6 P6-6 IO41 44
11 IO10 P2-2 P6-2 IO42 45
12 IO11 P2-7 P6-7 IO43 46
13 IO12 P2-3 P6-3 IO44 47
14 IO13 P2-8 P6-8 IO45 48
15 IO14 P2-4 P6-4 IO46 49
16 IO15 P2-9 P6-9 IO47 50
17 COM0 P1-5 &
P2-5 P5-5 & P6-5 COM2 51
18 COM1 P3-5 &
P4-5 P7-5 & P8-5 COM3 52
19 IO16 P3-1 P7-1 IO48 53
20 IO17 P3-6 P7-6 IO49 54
21 IO18 P3-2 P7-2 IO50 55
22 IO19 P3-7 P7-7 IO51 56
23 IO20 P3-3 P7-3 IO52 57
24 IO21 P3-8 P7-8 IO53 58
25 IO22 P3-4 P7-4 IO54 59
26 IO23 P3-9 P7-9 IO55 60
27 IO24 P4-1 P8-1 IO56 61
28 IO25 P4-6 P8-6 IO57 62
29 IO26 P4-2 P8-2 IO58 63
30 IO27 P4-7 P8-7 IO59 64
31 IO28 P4-3 P8-3 IO60 65
32 IO29 P4-8 P8-8 IO61 66
33 IO30 P4-4 P8-4 IO62 67
34 IO31 P4-9 P8-9 IO63 68

PMCDIO64
Copyright 2000 BVM Ltd.
11
6.2 Rear I/O Connector
The I/O signals are also connected to the P4 connector - the pin-out is shown below. This pin-out is
compatible with the BVM cIO200 used with cPC200 i.e. the same lead may be used with the front
panel or rear panel I/O. With the rear panel there are no common pins supplied from the PMCDIO64.
If the rear I/O is to be used it is important that a suitable common is provided.
Pin No. Signal Signal Pin No.
1 IO0 IO32 2
3 IO1 IO33 4
5 IO2 IO34 6
7 IO3 IO35 8
9 IO4 IO36 10
11 IO5 IO37 12
13 IO6 IO38 14
15 IO7 IO39 16
17 IO8 IO40 18
19 IO9 IO41 20
21 IO10 IO42 22
23 IO11 IO43 24
25 IO12 IO44 26
27 IO13 IO45 28
29 IO14 IO46 30
31 IO15 IO47 32
33 IO16 IO48 34
35 IO17 IO49 36
37 IO18 IO50 38
39 IO19 IO51 40
41 IO20 IO52 42
43 IO21 IO53 44
45 IO22 IO54 46
47 IO23 IO55 48
49 IO24 IO56 50
51 IO25 IO57 52
53 IO26 IO58 54
55 IO27 IO59 56
57 IO28 IO60 58
59 IO29 IO61 60
61 IO30 IO62 62
63 IO31 IO63 64
6.3 PMC I/O Board
If required, a SCSI-III style lead can be used to connect to the BVM 8 Port PMC I/O Board from either
the Front Panel Connector or the Rear I/O Connector providing 8 off 9 pin D-type connectors - see
section "1.3 PMC I/O Board Part Numbers (on page 1)" - in which case the resulting 9 pin D-type pin-
outs are shown below in Figure 5.
1
2
3
4
5
6
7
8
9
IO0+(Nx8)
IO2+(Nx8)
IO4+(Nx8)
IO6+(Nx8)
COM
IO1+(Nx8)
IO3+(Nx8)
IO5+(Nx8)
IO7+(Nx8)
N = 0 to 7
Figure 5 Connector Pin-outs for 9-pin D-type

PMCDIO64
Copyright 2000 BVM Ltd.
12
6.4 PCI Connections
P1 and P2 provide the standard PCI signals on the PMC module, as defined in the PMC specification
and reproduced for reference purposes below.
P1 32 Bit PCI P2 32 Bit PCI
Pin Signal
Name Signal Name Pin Pin Signal Name Signal Name Pin
1 TCK -12V 2 1 +12V TRST# 2
3 Ground INTA# 4 3 TMS TDO 4
5 INTB# INTC# 6 5 TDI Ground 6
7 BUSMODE1# +5V 8 7 Ground PCI-RSVD* 8
9 INTD# PCI-RSVD* 10 9 PCI-RSVD* PCI-RSVD* 10
11 Ground PCI-RSVD* 12 11 BUSMODE2# +3.3V 12
13 CLK Ground 14 13 RST# BUSMODE3# 14
15 Ground GNT# 16 15 3.3V BUSMODE4# 16
17 REQ# +5V 18 17 PME# Ground 18
19 V (I/O) AD[31] 20 19 AD[30] AD[29] 20
21 AD[28] AD[27] 22 21 Ground AD[26] 22
23 AD[25] Ground 24 23 AD[24] +3.3V 24
25 Ground C/BE[3]# 26 25 IDSEL AD[23] 26
27 AD[22] AD[21] 28 27 +3.3V AD[20] 28
29 AD[19] +5V 30 29 AD[18] Ground 30
31 V (I/O) AD[17] 32 31 AD[16] C/BE[2]# 32
33 FRAME# Ground 34 33 Ground PMC-RSVD 34
35 Ground IRDY# 36 35 TRDY# +3.3V 36
37 DEVSEL# +5V 38 37 Ground STOP# 38
39 Ground LOCK# 40 39 PERR# Ground 40
41 SDONE# SBO# 42 41 +3.3V SERR# 42
43 PAR Ground 44 43 C/BE[1]# Ground 44
45 V (I/O) AD[15] 46 45 AD[14] AD[13] 46
47 AD[12] AD[11] 48 47 Ground AD[10] 48
49 AD[09] +5V 50 49 AD[08] +3.3V 50
51 Ground C/BE[0]# 52 51 AD[07] PMC-RSVD 52
53 AD[06] AD[05] 54 53 +3.3V PMC-RSVD 54
55 AD[04] Ground 56 55 PMC-RSVD Ground 56
57 V (I/O) AD[03] 58 57 PMC-RSVD PMC-RSVD 58
59 AD[02] AD[01] 60 59 Ground PMC-RSVD 60
61 AD[00] +5V 62 61 ACK64# +3.3V 62
63 Ground REQ64# 64 63 Ground PMC-RSVD 64

PMCDIO64
Copyright 2000 BVM Ltd.
13
7. Programming
7.1 PCI Configuration Details
A pre-programmed EEPROM contains the BVM PCI Vendor ID, which is 15C0 (hexadecimal) and the
PCI Device ID, which is 02FF (hexadecimal) and the BVM PCI Subsystem Vendor ID, which is 15C0
(hexadecimal) and the PCI Subsystem Device ID, which is 0265 (hexadecimal).
7.2 Address Map
The PMCDIO64 uses BAR2 for access to the user accessible registers which are mapped into PCI
memory space as shown below. BAR0 is used for access to the PCI9030 configuration register offsets
which are also mapped into PCI memory space. Details of PCI9030 configuration are not covered in
this User's Manual - see section "A.1 PCI9030 PCI Interface (on page 17)" for further details. BAR1,
BAR3 and above are unused.
Address Description Access Size
007 - 000 Input Register R 64
00f - 008 Output Register R/W 64
017 - 010 Change Flags Register R 64
018 Direction Register R/W 8
019 Function Register R 8
01B - 01A Status & Control Register R/W 16
0FF - 01C Reserved (reads 0) R
100 Watchdog Trigger Register R/W 8
103 - 101 Unused (undefined)
104 Watchdog Timer Register R/W 8
107 - 105 Unused (undefined)
108 Watchdog Status Register R 8
1FF - 109 Unused (undefined)
7.3 Register Descriptions
7.3.1 Input Register
The 64-bit read only Input Register contains a latched version of the I/O pins on the logic device. The
signal is latched by the 33MHz PCI clock. When reading back the output signals, no account is taken
of values beyond the I/O buffers. To read a 64-bit register requires two 32-bit PCI read cycles, each of
which generates two 16-bit read cycles on the local bus. As data consistency across the register
cannot be guaranteed, an "input lock bit" is provided in the Status & Control Register - see section
"7.3.6.5 Input Lock (Bit 12: INLOCK) (on page 14)" - when this bit is set the input buffer will not update.
7.3.2 Output Register
The 64-bit read/write Output Register contents are output to valid output pins. To write to a 64-bit
register requires two 32-bit PCI writes, each requiring two 16-bit write cycles on the local bus. This
means that it is impossible to ensure that all outputs are updated at the same time. For this reason an
"output hold bit" is provided in the Status & Control Register - see section "7.3.6.6 Output Hold (Bit 13:
OUTHLD) (on page 14)" - when this bit is set the contents of the output buffer can be altered without
affecting the outputs, when this bit is cleared all outputs will change to their new value at the same
time.
7.3.3 Change Flags Register
The 64-bit read only Change Flags Register contains bits which indicate whether that particular input
caused a change-of-state to occur. The change-of-state function is enabled in the Status & Control
Register - see section "7.3.6.7 Interrupt On Change-of-State Enable (Bit 14: IOCEN) (on page 14)".
The overall status of the change-of-state can be determined in the Status & Control Register where
the Change Flags can also be cleared - see section "7.3.6.8 Interrupt On Change-of-State Status (Bit
15: IOCST) (on page 14)".

PMCDIO64
Copyright 2000 BVM Ltd.
14
7.3.4 Direction Register
The 8-bit read/write Direction Register where each bit corresponds to a group of 8 I/O bits. If the
corresponding bit is set to 1 the bit is enabled as an output otherwise it is enabled as an input.
7 6 5 4 3 2 1 0
IO63-56 IO55-48 IO47-40 IO39-32 IO31-24 IO23-16 IO15-8 IO7-0
7.3.5 Function Register
The 8-bit read only Function Register contains the low byte of the PCI Subsystem Device ID - in this
case 65 (hexadecimal). This can be used to determine the type of board fitted from the PMCDIO and
PMCCTR range.
7.3.6 Status & Control Register
The 16-bit read/write Status & Control Register is used to control a number of the module functions as
described below. Reserved bits (RSVD) read as zero and should be written as zero for future
compatibility.
76543210
WDGST IWDEN RSVD GOPEN WINEN RSVD RSVD RSVD
15 14 13 12 11 10 9 8
IOCST IOCEN OUTHLD INLOCK RSVD RSVD RSVD RSVD
7.3.6.1 Watchdog Interrupt Enable (Bit 3: WINEN)
When set to 1 this bit enables the generation of a PCI Interrupt if an enabled internal watchdog times
out - see section "7.3.6.3 Internal Watchdog Enable (Bit 6: IWDEN) (below)". If clear no PCI Interrupt
will be generated.
7.3.6.2 Global Output Enable (Bit 4: GOPEN)
When set to 1 signals selected as outputs are enabled. If clear signals selected as outputs are
disabled. Input signals are unaffected.
7.3.6.3 Internal Watchdog Enable (Bit 6: IWDEN)
When set to 1 the internal watchdog function is enabled and if the watchdog times-out then the
outputs will be disabled. If clear the state of the watchdog is ignored.
7.3.6.4 Watchdog Status (Bit 7: WDGST)
When set to 1 this bit indicates an enabled internal watchdog has timed-out - see section "7.3.6.3
Internal Watchdog Enable (Bit 6: IWDEN) (above)". Once set this bit cannot be cleared.
7.3.6.5 Input Lock (Bit 12: INLOCK)
When set to 1 the Input Register will be locked and will not be updated when the input signals change.
If clear the Input Register will reflect the state of the input signals.
7.3.6.6 Output Hold (Bit 13: OUTHLD)
When set to 1 then signals selected as outputs will not be updated from the Output Register, but the
Output Register can still be written. When clear then the signals selected as outputs will reflect the
state of the Output Register
7.3.6.7 Interrupt On Change-of-State Enable (Bit 14: IOCEN)
When set to 1 a PCI interrupt will be generated when signals selected as inputs change state. When
clear no PCI interrupt will be generated on input change-of-state. Note that when change-of-state
mode is enabled that the Input Register will be locked and will not be updated until the mode is
disabled.
7.3.6.8 Interrupt On Change-of-State Status (Bit 15: IOCST)
This bit is set to 1 if any change flags are set after Interrupt On Change-of-State has been enabled.
Writing a 1 clears all change flags.