When in the IDLE or PAUSED states, no transfers are performed.
To minimize writing in the same sector of the external memory multiple times, a wearing level mechanism is implemented. On
initialization, the application scans the external memory to locate the last sector written by the application. Every time a new
record is started, the application erases and writes new data in the next sector available. This mechanism reduces the number
of times the same sector is erased/written. The same sector will only be erased/written when all other sectors are used.
The firmware uses FreeRTOS to execute the processes required by this application. All tasks run in the Arm®Cortex®-M4 CPU.
The following tasks are created:
1. RecorderTask: handles recording and playing. It controls the transfers between the FIFOs, SRAM, and external memory.
2. TouchTask: handles CapSense touches on the buttons and slider.
3. EventsTask: handles any events that occur, such as touches from CapSense or recording/playing events.
4. GraphicsTask: handles updates and draws on the LCD.
Other RTOS elements used for synchronization and communication are:
1. Event Queue: used to notify EventsTask when specific events occur. The RecorderTask and TouchTask are senders.
2. GUI Queue: used to notify GraphicsTask to update or draw something on the screen. RecorderTask and EventsTask are
senders.
3. SMIF Semaphore: used to lock the SMIF interface for accessing the external memory.
4. DMA Event Group Bits: used to notify RecorderTask that a DMA interrupt occurred.
Components and Settings
Table 1 lists the PSoC Creator Components used in this example, how they are used in the design, and the non-default settings
required so they function as intended.
Table 1. PSoC Creator Components
SMIF Datalines[0:1] checked
SMIF Datalines[2:3] checked
SMIF SPI Slave Select 0 checked
Generate code from cy_smif.cysmif file checked
All other parameters unchecked
See Figure 5 for SMIF Configuration Tool
(Launch by clicking with right mouse button over
the SMIF component)
