Diamond Systems ZIRCON-MM User manual

ZIRCON-MM
8-Bit Resolution Analog & Digital I/O
PC/104 Module
User Manual V2.11
Copyright 2002
Diamond Systems Corporation
8430-D Central Ave.
Newark, CA 94560
Tel [phone]
Fax [phone]
[email protected]
www.diamondsystems.com

ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 2
TABLE OF CONTENTS
1. General Description..............................................................................................................3
2. ZIRCON-MM I/O Header Pinout............................................................................................4
3. Base Address Configuration..................................................................................................5
4. Interrupt Configuration..........................................................................................................5
5. Analog I/O Configuration.......................................................................................................6
6. Zircon-MM Board Drawing ....................................................................................................8
7. Register Map ........................................................................................................................9
8. Register definitions .............................................................................................................10
9. Digital I/O Operation...........................................................................................................13
10. Counter/Timers (ZMM-DX only) ..........................................................................................14
11. Analog I/O ..........................................................................................................................15
12. Analog Input Formulas........................................................................................................16
13. Analog Output Formulas.....................................................................................................16
14. Specifications .....................................................................................................................17

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1. GENERAL DESCRIPTION
ZIRCON-MM is a PC/104 format I/O module with 8 analog inputs, 1 analog output, 24 digital I/O
lines, 3 16-bit counter/timers (DX version), and 1 interrupt line. Both the analog input and output
resolution are 8 bits (1/256). The analog circuitry requires no calibration over the lifetime of the
product.
The digital I/O is based on an 82C55 chip with 3 8-bit ports and one configuration register. All I/O
lines are TTL and CMOS compatible.
The counter/timers are based on an 82C54 chip with 3 16-bit counter/timers and one configuration
register. Two counters are cascaded together to form a 32-bit counter/timer; The input to this
combined counter/timer is driven by an on-board 4MHz clock oscillator. The third counter/timer is
available at the I/O header. All I/O lines are TTL and CMOS compatible.
ZIRCON-MM is an 8-bit bus module and conforms to the physical and electrical specifications for 8-
bit PC/104 modules published in the PC/104 Specification, Version 2.1, July 1994. As it is an 8-bit
module, it does not contain the 16-bit expansion bus connector.
One 50-pin right-angle pin headers is provided for all I/O. The pinout of this header is defined at the
end of this manual. All digital I/O signals are TTL compatible.
Three versions are available:
ZMM-LC: Contains no counter/timer; all analog I/O is unipolar (positive voltages) only.
ZMM-DX: Contains the counter/timer; analog I/O can be unipolar or bipolar.
ZIRCON-MM operates on +5V power supply only. Model ZMM-DX provides an on-board DC/DC
converter to provide +/-5V for the analog circuitry. Model ZMM-LC uses the system +5V and ground
for the analog supply.

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2. ZIRCON-MM I/O HEADER PINOUT
J3 is the I/O header for Zircon-MM. It is a standard 50-pin dual row male header.
Analog In 7 12Analog In 6
Analog In 5 34Analog In 4
Analog In 3 56Analog In 2
Analog In 1 78Analog In 0
Analog Gnd 910 Analog Gnd
Analog Out 11 12 Analog Gnd
Analog Gnd 13 14 Analog Gnd
+5 Analog 15 16 -5 Analog
Analog Gnd 17 18 Analog Gnd
Digital Gnd 19 20 External Trigger
Gate 1/2 21 22 In 0
Gate 0 23 24 Out 0
A7 25 26 A6
A5 27 28 A4
A3 29 30 A2
A1 31 32 A0
C7 33 34 C6
C5 35 36 C4
C3 37 38 C2
C1 39 40 C0
B7 41 42 B6
B5 43 44 B4
B3 45 46 B2
B1 47 48 B0
+5 Digital 49 50 Digital Gnd
Definitions
Analog In 7 -0 Analog input channels; range depends on configuration
Analog Out Analog output channel; range depends on configuration
In 0, Gate 0, Out 0 Counter 0 input (clock), gate, and output pins
Gate 1/2 Counters 1 and 2 gate control pin
External Trigger External Trigger for interrupt-based A/D conversions
A7 -A0 Digital I/O port A (82C55)
B7 -B0 Digital I/O port B (82C55)
C7 -C0 Digital I/O port C (82C55)
+5 Digital, Digital Ground Access to main PC/104 power supply voltages
+5 Analog ZMM-DX: +5V from the on-board analog power supply;
ZMM-LC+5 Digital
-5 Analog ZMM-DX: -5V from the on-board analog power supply;
ZMM-LC: No connection
Analog Ground Ground reference for the analog input/output signals

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3. BASE ADDRESS CONFIGURATION
The base address is the address of the lowest location in the board’s I/O map. Zircon-MM's base
address is set with header J5, located at the lower right corner of the board. Seven different base
addresses are available; see the table below. The default setting is 300 Hex. "Open" means an open
position, and "Inst" means a position with a jumper installed. Note that 3 jumpers are never installed,
only 0, 1 or 2.
Base Address Header J5 Position
Hex Decimal CBA
240 576 Open Open Open
280 640 Open Open Inst
2C0 704 Open Inst Open
300 768 (Default) Open Inst Inst
340 832 Inst Open Open
380 896 Inst Open Inst
3C0 960 Inst Inst Open
4. INTERRUPT CONFIGURATION
Interrupt operation is configured with header J6, located in the lower center of the board.
One position is used for the PC/104 1KΩpulldown resistor to enable interrupt sharing. This resistor
should be connected if interrupts are used. Only one resistor should be connected to any interrupt
line on the bus. Interrupts on Zircon-MM are driven by a tristate driver. When an interrupt is pending,
the interrupt line is driven high, and when it is not pending, the output is in high-impedance mode,
and the 1KΩresistor pulls it down to a logic 0 state.
Once an interrupt request is generated by Zircon-MM, it is reset by reading from the A/D converter
(read from base + 0 or base + 1).
Interrupts are enabled, disabled, and reset under software control. This header is used only to select
the level and the resistor configuration.
Position Function Open Jumper
R1KΩResistor No pulldown Pulldown (max 1 per level)
2IRQ2
3IRQ3 Install only one jumper in
4IRQ4 any of these 6 locations
5IRQ5 to select the interrupt level
6IRQ6
7IRQ7

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5. ANALOG I/O CONFIGURATION
This section describes how to configure the analog input and analog output full-scale ranges. The
full-scale range for the analog inputs is the maximum range that an input signal can swing, still be
readable by the board and not cause damage to the board. The full-scale range for the analog output
is the maximum range of voltages that the board can generate on the analog output.
Model ZMM-LC has unipolar analog input and output ranges. This means that the analog inputs can
only accept positive voltages, and the analog output can only create positive voltages. The input and
output ranges are always the same on these models. The analog input/output range on these models
can be set to either 0 -1.25V or 0 -2.5V.
Model ZMM-DX has both unipolar and bipolar ranges, meaning that the analog inputs can accept
both negative and positive input voltages, and the analog output can create both negative and
positive voltages. The analog input range on this model can be set to 0-1.25V, 0-2.5V, or 0-5V in
unipolar mode and +/-1.25V, +/-2.5V, or +/-5V in bipolar mode.
Header J4 at the top of the board is used to configure the analog input and output ranges. This 2x4
header had the labels “D R B U” above the four positions. The meanings of these positions are
described below. However the simplest way to configure the board is just to refer to the table at the
bottom of page 7.
Note: All settings are valid for model ZMM-DX. However, only two settings are valid for ZMM-LC.
These settings are marked with an asterisk in the table.
Note: There is an additional header labeled J7 near J4. The jumpers on this header are set at the
factory and should not be altered. For ZMM-LC, both jumpers should be in the right positions (over
the middle and right pins). For ZMM-DX, both jumpers should be in the left positions (over the middle
and left pins). Do not alter the positions of these jumpers, since doing so will prevent the board from
functioning properly.

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DDouble the analog input range relative to the analog output range. For example, if the analog
range is set to +/-2.5V, inserting a jumper in this position sets the analog input range to +/-5V.
The analog output range, however, is still +/-2.5V. Doubling the analog input range is
accomplished by inserting a voltage divider in the path of the analog input signal to divide the
signal by 2. This means that the signal reaching the A/D converter is 1/2 the signal at the input to
the board, so the input signal can swing twice as wide as the A/D full-scale range.
The D position can only be used on model ZMM-DX. On model ZMM-LC, this jumper has no
effect, and the analog input and analog output ranges are always the same.
RRange. Installing a jumper in this position sets the range to 0-1.25V or +/-1.25V, and removing
the jumper sets the range to 0-2.5V or +/-2.5V. On ZMM-DX, the range setting is further modified
by the setting of D above.
BBipolar range. On ZMM-DX, installing a jumper in this position will configure the analog inputs
and output for bipolar ranges, depending on the position of D and R above.
WARNING: Do not install a jumper in this position on ZMM-LC, as the analog circuitry will
not function properly.
UUnipolar range. On ZMM-DX, installing a jumper in this position will configure the analog inputs
and output for unipolar ranges, depending on the positions of D and R above.
This jumper must be installed on models ZMM-LC and ZMM-LC2 for the board to function
properly.
WARNING: Do not install a jumper in both B and U on ZMM-DX, since doing so will short
the -5V supply to Ground.
The table below illustrates all valid settings for these jumpers and the resulting analog input and
output ranges.
Analog I/O Configuration Settings
DRBUInput range Output range
*Out Out Out In 0-2.5V 0-2.5V
Out Out In Out +/-2.5V +/-2.5V
*Out In Out In 0-1.25V 0-1.25V
Out In In Out +/-1.25V +/-1.25V
In Out Out In 0-5V 0-2.5V
In Out In Out +/-5V +/-2.5V
In In Out In 0-2.5V 0-1.25V
In In In Out +/-2.5V +/-1.25V
*These are the only valid settings for ZMM-LC.

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6. ZIRCON-MM BOARD DRAWING
This drawing will help to locate various key features on the board as described in the configuration
sections above.

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7. REGISTER MAP
Base + Write Read
0Analog Output A/D register
1Analog Output (duplicate) A/D register (duplicate)
2Start A/D conversion --
3Start A/D conversion (duplicate) --
4Control register Status register
5Control register (duplicate) Status register (duplicate)
6-- --
7-- --
8Digital I/O port A (82C55) Digital I/O port A
9Digital I/O port B Digital I/O port B
10 Digital I/O port C Digital I/O port C
11 Digital I/O configuration register --
12 Counter/timer 0 data (82C54) Counter/timer 0 data
13 Counter/timer 1 data Counter/timer 1 data
14 Counter/timer 2 data Counter/timer 2 data
15 Counter/timer configuration register Counter/timer configuration register
A/D, D/A, Control, and Status register definitions are shown starting on the next page. For digital I/O
and counter/timer register definitions, refer to the 82C55 and 82C54 datasheets, respectively.
Counter/timers are not available on model ZMM-LC.

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8. REGISTER DEFINITIONS
Base + 0 or 1: D/A Register (Write only)
Both these addresses map to the same physical register on the board.
Bit 76543210
Name D7D6 D5 D4 D3 D2 D1 D0
D7 -D0 8-bit digital value for output; D7 = most significant bit, D0 = least significant bit
See Section 11 for formulas to convert the desired output voltage to the corresponding input output
code.
Base + 0 or 1: A/D Register (Read only)
Both these addresses map to the same physical register on the board.
Bit 76543210
Name A7 A6 A5 A4 A3 A2 A1 A0
A7 -A0 8-bit digital value from A/D; D7 = most significant bit, D0 = least significant bit
See Section 10 for formulas to convert this reading to the corresponding input voltage
Base + 2 or 3: Start A/D Conversion (Write only)
Both these addresses map to the same physical register on the board.
Writing to this register starts an A/D conversion. The value written does not matter.

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Base + 4 or 5: Control register (Write only)
Both these addresses map to the same physical register on the board.
Bit 76543210
Name XXXTrigE TrigC Ch2 Ch1 Ch0
XNot used
TrigE Trigger enable for External Trigger
1External Trigger generates A/D conversions
0External Trigger is not used
TrigC Trigger enable for Counter 2 output (ZMM-DX only)
1Counter 2 output generates A/D conversions
0Counter 2 output is not used
Ch2 -Ch0 A/D channel select:
Ch2 Ch1 Ch0 Input channel
0000
0011
0102
0113
1004
1015
1106
1117
Base + 4 or 5: Status register (Read only)
Both these addresses map to the same physical register on the board.
Bit 76543210
Name Busy Range Int TrigE TrigC Ch2Ch1 Ch0
Busy A/D converter status:
0A/D converter busy (A/D conversion in progress)
1A/D converter idle (A/D conversion complete)
Range A/D Range selection from configuration header J4; see page 7 for details on the
meaning of this bit
TrigE, TrigC Readback of these control register bits (see above)
Ch2, Ch1, Ch0 Readback of these control register bits (see above)

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Base+8through Base+11 Read/Write 82C55 Digital I/O Chip Registers
These registers map directly to the 82C55 24-line digital I/O chip.
Base + n, Dir, Function D7 D6 D5 D4 D3 D2 D1 D0
8, R/W, Port A A7 A6 A5 A4 A3 A2 A1 A0
9, R/W, Port B B7 B6 B5 B4 B3 B2 B1 B0
10, R/W, Port C C7 C6 C5 C4 C3 C2 C1 C0
11, W, Config Register 1ModeC ModeA DirA DirCH ModeB DirB DirCL
Configuration Register
The configuration register is programmed by writing to Base + 11 using the format below. Once you
have set the port directions with this register, you can read and write to the ports as desired.
Bit No. 76543210
Name 1ModeC ModeA DirA DirCH ModeB DirB DirCL
Definitions:
1Bit 7 must be set to 1 to indicate port mode set operation.
DirA Direction control for bits A7 –A0: 0 = output, 1 = input
DirB Direction control for bits B7 –B0: 0 = output, 1 = input
DirCL Direction control for bits C3 –C0: 0 = output, 1 = input
DirCH Direction control for bits C7 –C4: 0 = output, 1 = input
ModeA, ModeB, ModeC I/O Mode for each port, 0 or 1
Here is a list of common configuration register values (others are possible):
Configuration Byte
Hex Decimal Port A Port B Port C (both halves)
9B 155 Input Input Input (all ports input)
92 146 Input Input Output
99 153 Input Output Input
90 144 Input Output Output
8B 139 Output Input Input
82 130 Output Input Output
89 137 Output Output Input
80 128 Output Output Output (all ports output)

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9. DIGITAL I/O OPERATION
Addresses 8 –11 on the board map to the 82C55 digital I/O chip on Zircon-MM. This chip provides 3
8-bit ports, called A, B, and C, for a total of 24 I/O lines. The chip contains four registers, 1 each for
A, B, and C and 1 for control. These four registers are mapped to Ruby-MM-416’s I/O map at base +
12 through base + 15. The 24 I/O lines are brought out to pins 25 -48 on the user I/O header J3.
The I/O lines are standard CMOS logic with ±2.5mA output current capability. If more output current
is required, use a buffer chip such as 74F244 or 74ACT244.
Each port’s direction is determined through a control register. In normal “Mode 0” operation (the most
common operating mode), ports A and B can be independently configured for input or output, and
each half of port C can be independently configured for input or output. Output data is latched in the
chip, but input data is not latched. When reading a port that is in input mode, the current logic levels
of the port at the time of the read operation will be returned. To latch data into the port, you must use
Modes 1 or Mode 2. In “Mode 1” and “Mode 2” operation, A and B are again configurable for
input/output, but port C is reconfigured to provide control signals for transfer requests and data
latching. A complete 82C55 datasheet is included at the end of this manual; please refer to it for
programming details.
At power up, hardware reset, or board reset (write to base + 8), the 82C55 is set to all input and the
data registers for ports A, B, and C are set to 0.
When a port is set to output mode, the contents of its output register are cleared to 0.
See page 12 for more detail on the 82C55 registers and operation, and see the 82C55 datasheet at
the back of this manual for a complete description of the chip.

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10. COUNTER/TIMERS (ZMM-DX ONLY)
Addresses 12 –15 on model ZMM-DX map to an 82C54 counter/timer chip on the board. This chip
provides 3 16-bit counter/timers. Each counter/timer has an input pin, a gate pin, and an output pin.
The input pin responds to positive edges. A datasheet on the 82C54 is provided in the Appendix.
This datasheet provides complete details on the operation and programming of the 82C54.
On ZMM-DX, counters 2 and 1 are cascaded together to create a 32-bit wide timer for A/D
conversion timing and interrupts. An on-board oscillator provides a 4MHz clock that drives the input
of counter 2. Counter 2’s output is connected to counter 1’s input. Each counter is generally
programmed or Mode 2 operation (rate generator). In this way each counter is a divide-by-n counter,
meaning that the output frequency is equal to the input frequency divided by the programmed 16-bit
value (the divisor). The formula for determining the output frequency of this counter pair is:
Output frequency = 4Mz / (counter 2 divisor x counter 1 divisor)
The minimum divisor value for each counter is 2. Thus this counter pair can be used to generate a
clock between 1MHz (4MHz / (2 x 2)) and .0009313Hz (4MHz / (65535 * 65535), or 1 pulse every
1,074 seconds). The output of counter 1 is generally used as a source for interrupt-based A/D
conversions, although it can be used for other interrupt operations as well.
Counter 1’s output is used as a trigger source for A/D conversions. The end of an A/D conversion
can be used to generate interrupts on the bus. This sequence of operations should be remembered.
When using the counter/timers for interrupt operations (e.g. A/D conversions driven by interrupts),
typically the first step is to program counters 2 and 1 for Mode 2 operation, selecting the desired
interrupt rate by using the formula above. Then A/D conversions are initiated.
Counter 0 is completely independent. All three control pins are available on the I/O header. Input and
gate pins are connected to +5V through 10KΩpull-up resistors.

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11. ANALOG I/O
Zircon-MM contains an 8-bit resolution A/D converter and an 8-bit resolution D/A converter on a
single chip. The A/D converter input is fed by an 8 channel analog input multiplexor to expand the
number of input channels to 8 single-ended analog voltage inputs. The D/A converter is
nonmultiplexed, providing a single analog voltage output.
The A/D and D/A converter chip is factory calibrated for accuracy, and no user trims are provided (or
available). Zircon-MM therefore requires no calibration over its entire operating lifetime.
The analog I/O can be set to several different ranges, depending on the model of Zircon-MM. For
model ZMM-LC, the analog circuitry is powered from the system +5/Ground supplies, so all analog
I/O is limited to positive voltages (0 -2.5V or 0 -1.25V ranges). On ZMM-DX, the analog circuitry is
powered by an on-board DC/DC converter that provides dedicated +5/-5 supplies to the board. Using
these supplies bipolar input and output ranges are available, including +/-2.5V and +/-1.25V.
In addition, on ZMM-DX the input impedance is improved by the addition of a precision op amp
between the input multiplexor and the A/D converter. The addition of this op amp further enables the
use of a voltage divider network to provide two additional input ranges: +/-5V and 0-5V. The voltage
divider network, however, has the side effect of reducing the input impedance of the analog input
channels.
On ZMM-LC, the D/A converter is unbuffered and directly drives the output pin on the user I/O
header. This output can develop up to 1.25mA of current across a 2KΩload (at a maximum output
voltage of 2.5V). On ZMM-DX, the output is buffered through an op amp as described above,
providing up to 30mA of drive current capability.

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12. ANALOG INPUT FORMULAS
Zircon-MM uses an 8-bit A/D converter to read analog inputs. The output of this converter ranges
from 0 to 255 in unipolar mode (true binary value) and from -128 to +127 in bipolar mode (twos
complement value). The formulas below show how to convert the A/D converter reading to the
corresponding input voltage. In bipolar mode, the following conversion must be applied before using
these formulas, because the twos complement number is only an 8-bit wide value:
if A/D code >= 128 then A/D code = A/D code -256
This will convert readings in the range +128 to +255 into their proper values of -128 to -1.
Since the A/D converter is 8 bits wide, it can resolve the input voltage signal (detect changes in input
voltage) to within 1/28, or 1/256, of the full input range. This minimum detectable voltage difference
is equal to 1 least significant bit, or 1 LSB, because it is the change in input voltage required to cause
the A/D reading to change by 1 LSB. The value of 1LSB for each input range is shown below.
Converting A/D Converter Values to Equivalent Input Voltages
Input range 1LSB Conversion formula Notes
+/-5V 39.1mV Input voltage = 10V x A/D code / 256 ZMM-DX only
+/-2.5V 19.5mV Input voltage = 5V x A/D code / 256 ZMM-DX only
+/-1.25V 9.8mV Input voltage = 2.5V x A/D code / 256 ZMM-DX only
0 -5V 19.5mV Input voltage = 5V x A/D code / 256 ZMM-DX only
0 -2.5V 9.8mV Input voltage = 2.5V x A/D code / 256
0 -1.25V 4.9mV Input voltage = 1.25V x A/D code / 256
13. ANALOG OUTPUT FORMULAS
Zircon-MM uses an 8-bit D/A converter to generate analog outputs. In all cases except when the
input voltage divider is used on ZMM-DX, the analog output range is identical to the analog input
range.
Zircon-MM uses true binary coding for unipolar output ranges and offset binary coding for bipolar
ranges. This means that writing a 0 to the D/A will always product an output at negative full scale,
and writing 255 to the D/A will always product an output at positive full scale (minus 1 LSB). Because
of offset binary coding, an offset must be added to the output code in bipolar mode to produce the
desired output voltage.
The table below shows how to calculate the output code needed to generate the desired output
voltage for each output voltage range on Zircon-MM. The output code is the 8-bit value written to the
D/A converter.
Converting Desired Output Voltages to D/A Converter Codes
Output range 1LSB Conversion formula Notes
+/-2.5V 19.5mV Output code = (Output voltage / 5V) x 256 ZMM-DX only
+/-1.25V 9.8mV Output code = (Output voltage / 2.5V) x 256 ZMM-DX only
0 -2.5V 9.8mV Output code = (Output voltage / 2.5V) x 256
0 -1.25V 4.9mV Output code = (Output voltage / 1.25V) x 256

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14. SPECIFICATIONS
All specifications at 25oC. A/D conversion rate on 386-25MHz CPU.
Analog Input
No. / type of channels 8 single-ended
Resolution 8 bits (1 part in 256)
A/D conversion time 2.6 µs max
Maximum conversion rate 40 KHz typical (interrupt-based single conversions)
64 KHz typical (interrupt-based 8-channel scan)
Relative accuracy +/-1 LSB max
Offset error +/-3 LSB max
Full-scale error -4, +0 LSB max
Input current +/-300 µA max (ZMM-LC)
+/-60 nA max (ZMM-DX, D jumper not installed)
+/-25 µA max (ZMM-DX, D jumper installed)
Analog Output
No. / type of channels 1, voltage output
Resolution 8 bits (1 part in 256)
Settling time 4 µs max to +/-1/2 LSB
Offset error +/-2 LSB max
Full-scale error +/-2 LSB max
Output current +/-1.25mA max
Digital I/O
No. of lines 24 (using 82C55 chip)
Compatibility TTL / CMOS
Pull-up resistors 10KΩon each I/O line
Output voltage Logic 1: 3.0V min, 4.6V max; Logic 0: 0.0V min, 0.4V max
Output current Logic 1: -2.5mA max; Logic 0: +2.5mA max
Input voltage Logic 1: 2.0V min, 5.0V max; Logic 0: 0.0V min, 0.8V max
Counter/Timers
No. of counter/timers 3
Width 16 bits
Compatibility TTL / CMOS
Maximum clock frequency 10 MHz
On-board clock oscillator 4MHz
Configuration Counters 1 and 2 cascaded for interrupts; Counter 0 free
General
Dimensions 3.55” x 3.775” (PC/104 standard)
Operating temperature 0 -70oC
Power supply +5VDC ±10%
Current consumption ZMM-DX: 127mA
(typical, all outputs open) ZMM-LC: 100mA
PC/104 bus 8-bit bus used; 16-bit header footprint on board for passthrough

SEMICONDUCTOR
4-215
March 1997
82C54
CMOS Programmable Interval Timer
Features
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .10mA at 8MHz
• Operating Temperature Ranges
- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Harris 82C54 is a high performance CMOS Programma-
ble Interval Timer manufactured using an advanced 2 micron
CMOS process.
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Harris 80C86, 80C88,
and 80C286 CMOS microprocessors along with many other
industry standard processors. Six programmable timer
modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot, and many
other applications. Static CMOS circuit design insures low
power operation.
The Harris advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
Pinouts
82C54 (PDIP, CERDIP, SOIC)
TOP VIEW 82C54 (PLCC/CLCC) TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
D7
D6
D5
D4
D3
D2
D1
D0
CLK 0
OUT 0
GATE 0
GND
VCC
RD
CS
A1
A0
OUT 2
CLK 1
GATE 1
OUT 1
WR
CLK 2
GATE 2
GND
NC
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
D7
NC
VCC
WR
RD
D5 D6
CS
A1
A0
CLK2
NC
GATE 2
OUT 2
1234
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
D3
D2
D1
D0
D4
NC
CLK 0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 2970.1

4-216
Functional Diagram
Ordering Information
PART NUMBERS TEMPERATURE
RANGE PACKAGE PKG. NO.8MHz 10MHz 12MHz
CP82C54 CP82C54-10 CP82C54-12 0oC to +70oC 24 Lead PDIP E24.6
IP82C54 IP82C54-10 IP82C54-12 -40oC to +85oC 24 Lead PDIP E24.6
CS82C54 CS82C54-10 CS82C54-12 0oC to +70oC 28 Lead PLCC N28.45
IS82C54 IS82C54-10 IS82C54-12 -40oC to +85oC 28 Lead PLCC N28.45
CD82C54 CD82C54-10 CD82C54-12 0oC to +70oC 24 Lead CERDIP F24.6
ID82C54 ID82C54-10 ID82C54-12 -40oC to +85oC 24 Lead CERDIP F24.6
MD82C54/B MD82C54-10/B MD82C54-12/B -55oC to +125oC 24 Lead CERDIP F24.6
MR82C54/B MR82C54-10/B MR82C54-12/B -55oC to +125oC 28 Lead CLCC J28.A
SMD # 8406501JA - 8406502JA -55oC to +125oC 24 Lead CERDIP F24.6
SMD# 84065013A - 84065023A -55oC to +125oC 28 Lead CLCC J28.A
CM82C54 CM82C54-10 CM82C54-12 0oC to +70oC 24 Lead SOIC M24.3
Pin Description
SYMBOL DIP PIN NUMBER TYPE DEFINITION
D7 - D0 1 - 8 I/O DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLK 0 9 I CLOCK 0: Clock input of Counter 0.
OUT 0 10 O OUT 0: Output of Counter 0.
GATE 0 11 I GATE 0: Gate input of Counter 0.
GND 12 GROUND: Power supply connection.
OUT 1 13 O OUT 1: Output of Counter 1.
GATE 1 14 I GATE 1: Gate input of Counter 1.
CLK 1 15 I CLOCK 1: Clock input of Counter 1.
GATE 2 16 I GATE 2: Gate input of Counter 2.
OUT 2 17 O OUT 2: Output of Counter 2.
CONTROL
WORD
REGISTER
READ/
WRITE
LOGIC
DATA/
BUS
BUFFER
COUNTER
2
COUNTER
1
COUNTER
0
INTERNAL BUS
INTERNAL BUS
CONTROL
LOGIC
CONTROL
WORD
REGISTER
STATUS
LATCH
STATUS
REGISTER
CLK n
GATE n
OUT n
OUT 2
GATE 2
CLK 2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
WR
RD
D7- D0
A0
A1
CS
OLMOLL
CE
CRMCRL
COUNTER INTERNAL BLOCK DIAGRAM
8
82C54

4-217
Functional Description
General
The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and vari-
able length delays can easily be accommodated.
Some of the other computer/timer functions common to micro-
computers which can be implemented with the 82C54 are:
• Real time clock
• Event counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to inter-
face the 82C54 to the system bus (see Figure 1).
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the
82C54. A1 and A0 select one of the three counters or the Con-
trol Word Register to be read from/written into. A “low” on the
RD input tells the 82C54 that the CPU is reading one of the
counters. A “low” on the WR input tells the 82C54 that the CPU
is writing either a Control Word or an initial count. BothRD and
WR are qualified by CS; RD and WR are ignored unless the
82C54 has been selected by holdingCS low.
CLK 2 18 I CLOCK 2: Clock input of Counter 2.
A0, A1 19 - 20 I ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
CS 21 I CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and
WR are ignored otherwise.
RD 22 I READ: This input is low during CPU read operations.
WR 23 I WRITE: This input is low during CPU write operations.
VCC 24 VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended
for decoupling.
Pin Description (Continued)
SYMBOL DIP PIN NUMBER TYPE DEFINITION
A1 A0 SELECTS
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
CONTROL
WORD
REGISTER COUNTER
2
COUNTER
1
COUNTER
0
INTERNAL BUS
OUT 2
GATE 2
CLK 2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
WR
RD
D7- D0
A0
A1
CS
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTIONS
8DATA/
BUS
BUFFER
READ/
WRITE
LOGIC
82C54