Fibocom GTS-4E-00 Quick setup guide

GTS-4E GPS Module
Hardware Integration Manual
Version: V1.0.0
Date: 2011-1-24

GTS-4E GPS Module Hardware Integration Manual Page 2 of 22
Confidential Material
This document contains information highly confidential to Shenzhen G&T Industrial Development Co.,
Ltd (Fibocom). Fibocom offers this information as a service to its customers, to support application and
engineering efforts that use the products designed by Fibocom. The information provided is based upon
requirements specifically provided to Fibocom by the customers. All specifications supplied herein are
subject to change. Disclosure of this information to other parties is prohibited without the written
consent of G&T.
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Copyright ©1999-2011 Shenzhen G&T Industrial Development Co., Ltd. All rights reserved.
Revision History
Version
Date
Remarks
V1.0.0
2011-01-24
Initial Release
Trademarks Notice
The FIBOCOM Logo is registered by Shenzhen G&T Industrial Development Co., Ltd. All other product
or service names or Logos are the property of their respective owners.
Copyright ©1999-2010 Shenzhen G&T Industrial Development Co., Ltd.All rights reserved.

GTS-4E GPS Module Hardware Integration Manual Page 3 of 22
Preface .......................................................................................................................................................4
Manual Scope.....................................................................................................................................4
Target Audience ..................................................................................................................................4
How to use this Manual.......................................................................................................................4
1 Hardware Description..........................................................................................................................5
1.1 Functional Overview.............................................................................................................5
1.2 Naming rule of Part Number.................................................................................................5
1.3 Block Diagram ......................................................................................................................6
2 Design-In.............................................................................................................................................6
2.1 Power Management .............................................................................................................6
2.1.1 Connecting Power.........................................................................................................6
2.1.2 Power Modes ................................................................................................................7
2.2 Interfaces..............................................................................................................................8
2.2.1 Host Port UART.............................................................................................................8
2.2.2 Host Port SPI.................................................................................................................8
2.2.3 Dead Reckoning I2C bus..............................................................................................9
2.2.4 ON_OFF control input.................................................................................................10
2.2.5 Antenna input...............................................................................................................11
2.2.6 Active GPS antenna.....................................................................................................11
2.2.7 Time Mark TM.............................................................................................................12
2.2.8 ECLK...........................................................................................................................12
2.2.9 TSYNC ........................................................................................................................12
2.3 HW Information...................................................................................................................12
2.3.1 Pin Assignment ...........................................................................................................12
3 Electrical Specifications....................................................................................................................13
3.1 Absolute Maximum Ratings................................................................................................13
3.2 Operating Condition............................................................................................................13
4 Mechanical Specifications.................................................................................................................14
5 Layout................................................................................................................................................15
5.1 Paste Mask.........................................................................................................................15
5.2 Placement...........................................................................................................................16
5.3 Antenna Connection and Grounding Plane Design...........................................................17
5.4 Antenna and Antenna Supervisor......................................................................................19
5.4.1 Passive Antenna .........................................................................................................19
5.4.2 Active Antenna............................................................................................................20
6 ESD Protection Measures.................................................................................................................21
6.1 ESD Precautions for Antennas...........................................................................................21
7 Contact
................................................................................................................. 错误！未定义书签。

GTS-4E GPS Module Hardware Integration Manual Page 4 of 22
Preface
Manual Scope
This Manual provides hardware design instructions and information on how to set up production and
final product tests.
Target Audience
This manual is intended for hardware developers who communicate with the GTS-4E module.
How to use this Manual
This manual has a modular structure. It is not necessary to read it from the beginning to the end. To
help in finding needed information, a brief section overview is provided below:
1. Hardware Description: This chapter introduces the basics of function and architecture of the
GTS-4E module.
2. Design-In: This chapter provides the Design-In information necessary for a successful design.
3. Electrical Specifications: This chapter provides information about testing of OEM receivers in
production.
4. Mechanical Specifications: The Appendix includes a Reference Design, guidelines on how to
successfully migrate to GTS-4E designs, and useful information about the different antenna
types available on the market and how to reduce interference in your GPS design.
5. Layout: This chapter provides some layout matters needing attention for external circuit of
GTS-4E module.
6. ESD Protection Measures: This chapter provides some ESD matters needing attention when
no ESD device in the GTS-4E module.
7. Referent Design: This chapter provides a Referent Design for hardware development.

GTS-4E GPS Module Hardware Integration Manual Page 5 of 22
1 Hardware Description
1.1 Functional Overview
The GTS-4E designed by FIBOCOM basing on the SIRF-IV is a new generation of GPS receiving
module, and also in price competitive advantage. It’s a new 48-channel ultra-high sensitive GPS
receiving module. Based on new highly integrated SIRF-IV chips and meticulously integration key parts
of FIBOCOM, casting a brand-new GTS - 4E products, in the same chip specifications, product has
faster GPS signals ability to capture, lower power consumption, more strong anti-jamming performance
and more wide working voltage range.
GTS - 4E module designed with industrial requirements, using stamps package, can adapt to wet high
temperature, electromagnetic interference etc odiously working environment. It is widely used in
monitoring, positioning, mapping, navigation, security applications such as the ideal platform.
1.2 Naming rule of Part Number
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Serials number:
000:Base use(No DGPS and AGPS )
001:With DGPS and AGPS
Other reserved
Reserve
Reserve
0: NO EEPROM
1: EEPROM ON
0: NO ESD
1: ESD ON
0:UAR
T
1:SPI
Table 1：Naming rule of Part Number
Part Number in common use：
Table 2：Part Number in common use
UART
SPI
ESD
EEPROM
AGPS
DGPS
Lowpower
GTS-4E-00
●
●
GTS-4E-01
●
●
GTS-4E-02
●
●
●
GTS-4E-03
●
●
●
GTS-4E-20
●
●
●
●
GTS-4E-21
●
●
●
●
GTS-4E-22
●
●
●
●
●
GTS-4E-23
●
●
●
●
●
GTS-4E-24
●
●
●
●
●
GTS-4E-26
●
●
●
●
●
●

GTS-4E GPS Module Hardware Integration Manual Page 6 of 22
1.3 Block Diagram
Figure 1: Hardware Block Schematic
2 Design-In
2.1 Power Management
2.1.1 Connecting Power
GTS-4E receivers have two power supply pins: VCC, V_BCKP.
2.1.1.1 VCC - Main Power
The main power supply is fed through the VCC pin. During operation, the current drawn by the GTS-4E
GPS module. It is important that the system power supply circuitry is able to support the peak power
(see datasheet for specification) for a short time. In order to define a battery capacity for specific
applications the sustained power figure shall be used.
2.1.1.2 V_BACK - Backup Battery
The V_BACK should always on both in Sleep mode and working on mode. That is to say only VCC
- Main Power can not power on the module, it needs both VCC - Main Power and V_BACK.There are
three ways for you to connection V_BACK pin:

GTS-4E GPS Module Hardware Integration Manual Page 7 of 22
1. Backup Battery
2. Directly Connect to or by switcher to VCC - Main Power
3. GPIO
In case of a power failure on pin VCC, the real-time clock and backup RAM are supplied through pin
V_BACK.This enables the GTS-4E receiver to recover from a VCC - Main power failure with either a
Hotstart or a Warmstart(depending on the duration of VCC outage) and to maintain the configuration
settings. If no backup battery is connected, the receiver performs a Coldstart at power up.
2.1.2 Power Modes
GTS-4E offer five power modes for user, list as:
Full Power Mode: The module will enter Hibernate state after first power up with factory
configuration settings. TheNavigation mode will start after waking up from Hibernate state in cold
start mode by sending ON_OFF signal interrupt pulse from host. Power consumption will vary
depending on the amount of satellite acquisitions and number of satellites in track. This mode is
also referenced as full on, Full Power or Navigation mode.Navigation is available and any
configuration settings are valid s long as the VDD power supply is active. When the VDD is
powered off, settings are reset to factory configuration and receiver performs a cold start on next
power up.VDD supply is intended to be kept active all the time and navigation activity is suggested
to be controlled to low quiescent Hibernate state via ON_OFF control input.
Deep Sleep Mode:By cut VCC - Main Power off with V_BACK on.
Advanced Power Management (APM): APM allows power savings while ensuring that the quality of
the solution is maintained when signal levels drop. APM does not engage until all necessary
information is received. Host can configure e.g. number of APM cycles(continuous or up to 255),
time between fixes (10… 180 sec), Power duty cycle (5…100%) and max position error. Rest of
the time the receiver stays in Hibernate state. This mode is configurable with SiRF binary protocol
message ID53.
Push-to-Fix Mode (PTF): In this mode the receiver is configured to wake up periodically, typically
every 1800 sec (configurable range 10… 7200 sec), for position update and to collect new
ephemeris data from rising satellites. Rest of the time the receiver stays in Hibernate state. When
position update is needed, the host can wake up the receiver by ON_OFF control input interrupt
(pulse low-high-low >90us after which the receiver performs either Snap or Hot start and a valid fix
is available within 1… 8 seconds typ.This mode is configurable with SiRF binary protocol message

GTS-4E GPS Module Hardware Integration Manual Page 8 of 22
ID151 & 167.
Adaptive TricklePower (ATP): In this mode the receiver stays at full on power state for 200…
900ms and provides a valid fix. Between fixes with 1… 10 sec interval the receiver stays in
Hibernate state. ATP mode is configurable with SiRF binary protocol message ID151. The receiver
stays once in while in Full on power mode automatically (typ.every 1800 sec) to receive new
ephemeris data from rising satellites or if received signal levels drop below certain level.
2.2 Interfaces
There are two communication interfaces, Uart and SPI, for user port. It is valid for different part
number(refer to Table 1：Naming rule of Part Number).
For uart port the default protocol for host communication is NMEA 4800 baud. Protocol is switchable to
SiRF binary OSP (One Socket Protocol) by NMEA protocol command $PSRF100.
Default NMEA message configuration: $GPGGA, $GPGSA and $GPRMC rate every second (in this
order) and $GPGSV messages (can be 1… 4) every 5 seconds (sent after $GPGSA message).
GTS-4E also offer a I2C bus for external EEPROM and Accelerometer, it is valid in some part number.
2.2.1 Host Port UART
UART is normally used for GPS data reports and receiver control. Serial data rates are selectable from
1200 baud to 1.8432 Mbaud. Default baud rate is 4800 baud; default protocol is NMEA(protocol and
baud rate can be configured by NMEA $PSRF100 message). RX signal is suggested to be pulled up
externally when not used.
2.2.2 Host Port SPI
The host interface SPI is a slave mode SPI:
Supports both SPI and Microwire formats
An interrupt is provided when the transmit FIFO and output serial register (SR) are both empty
The transmitter and receiver each have independent 1024B FIFO buffers
The transmitter and receiver have individual software-defined 2-byte idle patterns of 0xA7 0xB4
Clock polarity: default SPI mode 1 (CPOL=0; CPHA=1) i.e. data is captured on the clock's
falling edge and data is propagated on a rising edge
SPI detects synchronization errors and is reset by software

GTS-4E GPS Module Hardware Integration Manual Page 9 of 22
Supports a maximum clock of 6.8MHz.
Signals: TX (SPI_DO, MISO), RX (SPI_DI, MOSI), CTS_N (SPI_CLK) and RTS_N (SPI_SS_N)
At system level the slave has no way of forcing data to the master to indicate it is ready for transmission;
the master must poll the client periodically. Since the specified idle byte pattern for both receive and
transmit is A7 B4, the master can transmit this idle pattern into the slave repeatedly.If the master
receives idle patterns back from the slave, it indicates that the slave currently has nothing to transmit
but is ready to communicate. Default protocol is NMEA (protocol can be configured by NMEA
$PSRF100 message).
On the receive side, the host is expected to transmit idle pattern A7 B4 when it is querying the
module’s transmit buffer, unless it has traffic to send to the module. In this way, the volume of
discarded bytes is kept nearly as low as in the UART implementation because the hardware does
not place most idle pattern bytes in its RX FIFO.
The FIFO thresholds are placed to detect large messages requiring interrupt-driven servicing. On the
transmit side, the intent is to fill the FIFO only when it is disabled and empty. In this condition, the SPI
driver software loads as many queued messages as can completely fit in the FIFO. Then the FIFO is
enabled. The host is required to poll messages until idle pattern bytes are detected. At this point the
FIFO is empty and disabled, allowing the SPI driver to again respond to an empty FIFO interrupt and
load the FIFO with any messages in queue.
Figure 2: SPI host port timing diagram, SPI mode 1 (assuming one byte transfer)
2.2.3 Dead Reckoning I2C bus
The DR_I2C bus (master) provides optional connectivity to the following devices:

GTS-4E GPS Module Hardware Integration Manual Page 10 of 22
Optional Dead Reckoning sensors (e.g. 3-D Accelerometer)
Optional connectivity to EEPROM for Client Generated Extended Ephemeris (CGEE) data storage
Optional ROM patch code storage to EEPROM and upload to IT430
.
The accelerometer MEMS sensor provides stationary detection, which allows to reduce the position
spread when stationary with weak GPS signals e.g. indoors. Other features will follow like Point & Tell,
i.e. attitude (heading) information based on 3-D compass (contact Fastrax support for details). When
MEMS sensor is used connect also the sensor’s INT output to IT430’s EIT input. The bus signals
require external pull up resistors 2.2kohm on both signals. Connect both signals to GND (or pull up)
when not used.
DR I²C interface supports:
Common sensor formats (Kionix, KXTF9-4100 device)
Common EEPROM data formats (STMicroelectronics, M24M01, 1 Mbit device)
Typical data lengths (command + in/data out) of several bytes
Standard I²C bus maximum data rate 400kbps
Minimum data rate 100kbps
2.2.4 ON_OFF control input
The ON_OFF control input must be used by the host to wakeup the module after first power up and to
control the receiver activity between Normal and Hibernate states and also to generate interrupt in
Push-to-Fix and SiRFAware modes of operation.
The module will boot to Hibernate state after power up. First ON_OFF interrupt wakes up the module
for Normal (Navigation) operation. Consequent ON_OFF interrupts switch the operation mode between
Hibernate and Navigation modes.
The ON_OFF interrupt is generated by rising edge of a low-high-low pulse, which should be longer than
90us and less than 1s (suggestion is abt. 100ms pulse length). Do not generate ON_OFF interrupts
less than 1 sec intervals. Especially take care that any multiple switch bounce pulses are filtered out.
During Hibernate state the I/O Keep Alive is still active, thus I/O signals keep respective states except
TX and RX signals, which are configured to high input impedance state.