GV Virtex-II DSP GVA-395 User manual

GVA-395
Virtex-II Hardware Accelerator
User’s Manual
GV & Associates, Inc
23540 Oriente Way
Ramona, CA 92065
[phone]
www.gvassociates.com

GV-395 Virtex-II DSP Hardware Accelerator Manual
GV & Associates, Inc.
07/10/04
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1.0 GVA-395 INTRODUCTION AND GENERAL DESCRIPTION ...............................................................4
1.1.1 GVA-395 DSP Demonstration Platform Block Diagram.......................................................................5
2.0 GVA-395 POWER CONFIGURATION .......................................................................................................6
2.1.1 GVA-395 Power Configuration Table ...................................................................................................6
3.0 INITIAL GVA-395 DIAGNOSTIC CHECK-OUT ......................................................................................6
4.0 XILINX FPGA CONFIGURATION .............................................................................................................7
4.1 JTAG CABLE CONFIGURATION ......................................................................................................................7
4.2 SLAVE SERIAL CABLE CONFIGURATION .........................................................................................................7
4.3 PARALLEL DOWN-LOAD CONFIGURATION .....................................................................................................7
4.4 SLAVE SERIAL PROGRAMMING OF ON-BOARD EEPROM (U2)......................................................................7
4.4.1.1 EEPROM Slave Serial Programming Configuration Table ............................................................................... 8
5.0 FLASH EEPROM CONFIGURATION FPGA (U1)....................................................................................8
6.0 ON-BOARD SYSTEM CLOCK CONFIGURATION.................................................................................8
6.1 EXTERNAL CLOCK CONFIGURATION ..............................................................................................................8
7.0 XILINX FPGA POWER-ON RESET AND MANUAL RESET PUSH BUTTON SWITCH...................8
7.1.1 Power-on Reset Interconnect Table.......................................................................................................8
8.0 ACX FPGA (U10) ............................................................................................................................................9
8.1 ACX FPGA (U10) TO DAUGHTER I/O PCB INTERFACE.................................................................................9
8.1.1.1 ACX FPGA (U10) to PC1 and PC2 Interconnection Table ............................................................................... 9
8.1.1.2 ACX FPGA (U10) to PC3 and PC4 Interconnection Table .............................................................................10
8.1.1.3 ACX FPGA (U10) to PC6 and PC7 Interconnection Table .............................................................................11
8.1.1.4 ACX FPGA (U10) to PC8 and PC9 Interconnection Table .............................................................................12
8.2 ACX FPGA HP LOGIC ANALYZER MICTOR CONNECTOR ............................................................................13
8.2.1.1 ACX FPGA (U10) to HC1 Interconnection Table ........................................................................................... 13
8.3 ACX FPGA 256K X16 ZBT RAM..............................................................................................................14
8.3.1 ACX FPGA (U10) ZBT RAM Pin Configuration Table .......................................................................14
8.4 ACX FPGA LED CONFIGURATION..............................................................................................................14
8.4.1 ACX FPGA (U10) LED Configuration Table ......................................................................................14
8.5 ACX FPGA- AC FPGA XBUS CONFIGURATION. .......................................................................................15
8.5.1 ACX FPGA (U10) to AC FPGA (U12) XBUS Configuration Table ....................................................15
9.0 AC FPGA (U12) .............................................................................................................................................16
9.1 AC FPGA (U12) TO DAUGHTER I/O PCB INTERFACE..................................................................................16
9.1.1.1 AC FPGA (U12) to PC9 and PC10 Interconnection Table .............................................................................. 16
9.2 AC FPGA HP LOGIC ANALYZER MICTOR CONNECTOR...............................................................................17
9.2.1.1 AC FPGA (U12) to HC1 Interconnection Table .............................................................................................. 17
9.3 AC FPGA 256K X16 ZBT RAM ................................................................................................................18
9.3.1 AC FPGA (U12) ZBT RAM Pin Configuration Table .........................................................................18
9.4 AC FPGA LED CONFIGURATION.................................................................................................................18
9.4.1 AC FPGA (U12) LED Configuration Table ........................................................................................18
9.5 AC FPGA -DP FPGA XBUS_A CONFIGURATION. .....................................................................................19
9.5.1 AC FPGA (U12) to DP FPGA (U14) XBUS_A Configuration Table..................................................19

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10.0 DP FPGA (U14) .............................................................................................................................................20
10.1 DP FPGA (U14) TO DAUGHTER I/O PCB INTERFACE. .................................................................................20
10.1.1.1 DP FPGA (U14) to PC11 and PC12 Interconnection Table ........................................................................ 20
10.2 DP FPGA HP LOGIC ANALYZER MICTOR CONNECTOR ...............................................................................21
10.2.1.1 DP FPGA (U14) to HC2 Interconnection Table .......................................................................................... 21
10.3 DP FPGA 1M X16 ZBT RAM ....................................................................................................................22
10.3.1 DP FPGA (U14) ZBT RAM Pin Configuration Table .........................................................................22
10.4 DP FPGA LED CONFIGURATION. ................................................................................................................22
10.4.1 DP FPGA (U14) LED Configuration Table ........................................................................................22
10.5 DP USB INTERFACE .....................................................................................................................................23
10.5.1 USB Interface for DP FPGA Interconnection Table ...........................................................................23
10.6 DP FPGA -DPX FPGA XBUS_B CONFIGURATION....................................................................................24
10.6.1 DP FPGA (U14) to DPX FPGA (U16) XBUS_B Configuration Table ...............................................24
11.0 DPX FPGA (U16)...........................................................................................................................................25
11.1 DPX FPGA 4X1M X16 ZBT RAM...........................................................................................................25
11.1.1 DPX FPGA (U16) ZBT RAM Pin Configuration Table.......................................................................25
11.2 DPX FPGA LED CONFIGURATION. .............................................................................................................25
11.2.1 DPX FPGA (U16) LED Configuration Table......................................................................................25
11.3 DPX USB INTERFACE ..................................................................................................................................26
11.3.1 USB Interface for DPX FPGA Interconnection Table.........................................................................26
11.4 DPX FPGA LVDS INTERFACE.....................................................................................................................27
11.4.1 DPX FPGA LVDS Bus Interconnection Table for J6 ..........................................................................27
11.4.2 DPX FPGA LVDS Bus Interconnection Table for J7 ..........................................................................27
12.0 EI FPGA (U18)...............................................................................................................................................28
12.1 EI FPGA XE_BUS CONFIGURATION. ..........................................................................................................28
12.1.1 XE_BUS Interconnection Table..........................................................................................................28
12.2 EXTERNAL SPARTAN INTERFACE FPGA CONNECTORS ................................................................................29
12.2.1 External Interface FPGA Bus Interconnection Table for J1................................................................29
12.2.2 External Interface FPGA Bus Interconnection Table for J2................................................................29
12.3 EI FPGA LED..............................................................................................................................................29
13.0 OPTIONAL DAUGHTER I/O PCBS FOR ANALOG CONTROL FPGA (U14) DESCRIPTIONS ....30
13.1 GVA-AD9430 170 MSPS 12 BIT A/D .........................................................................................................30
13.1.1 AC Coupled Analog Input Path ...........................................................................................................30
13.1.2 GVA-AD9430 Output Configuration ...................................................................................................30
13.1.2.1 GVA-AD9430 to GVA-395 PC Connection Interface Table....................................................................... 31
13.1.2.2 GVA-AD9430 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 31
13.1.3 GVA-AD9430 to GVA-395 AC FPGA PC No. 6-9 Connection Table .................................................32
13.1.3.1 GVA-AD9430 Digital Output Format Jumper Configuration Table ........................................................... 33
13.2 GVA-AD9432 100 MSPS 12 BIT A/D .........................................................................................................33
13.2.1 AC Coupled Analog Input Path ...........................................................................................................33
13.2.2 DC Coupled Analog Input Path...........................................................................................................33
13.2.3 GVA-AD9432 Analog Input Configuration..........................................................................................33
13.2.3.1 GVA-AD9432 Analog Input Jumper Configuration Table.......................................................................... 33
13.2.3.2 GVA-AD9432 to GVA-395 PC Connection Interface Table....................................................................... 34
13.2.3.3 GVA-AD9432 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 34
13.2.3.4 GVA-DA9432 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 35
13.3 GVA-DA6645 100 MSPS 14 BIT A/D .........................................................................................................36
13.3.1 AC Coupled Analog Input Path ...........................................................................................................36
13.3.2 DC Coupled Analog Input Path...........................................................................................................36
13.3.3 GVA-DA6645 Analog Input Configuration..........................................................................................36
13.3.3.1 GVA-AD6645 Analog Input Jumper Configuration Table.......................................................................... 36
13.3.3.2 GVA-DA6645 to GVA-395 Interface Table................................................................................................ 37
13.3.3.3 GVA-AD6645 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 37
13.3.3.4 GVA-DA6645 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 38

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13.4 GVA-DA9762 125 MSPS 12 BIT D/A .........................................................................................................39
13.4.1 Single-Ended Output Path ...................................................................................................................39
13.4.2 Differential Coupled Analog Output Path ...........................................................................................39
13.4.3 GVA-DA9762 Analog Output Configuration.......................................................................................39
13.4.3.1 GVA-DA9762 Analog Output Jumper Configuration Table ....................................................................... 39
13.4.3.2 GVA-DA9762 to GVA-395 Interface Table................................................................................................ 40
13.4.3.3 GVA-DA9762 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 40
13.4.3.4 GVA-DA9762 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 41
13.5 GVA-DA9772 125 MSPS 14 BIT D/A .........................................................................................................42
13.5.1 Single-Ended Output Path ...................................................................................................................42
13.5.2 Differential Coupled Analog Output Path ...........................................................................................42
13.5.3 GVA-DA9772 Analog Output Configuration.......................................................................................42
13.5.3.1 GVA-DA9772 Analog Output Jumper Configuration Table ....................................................................... 42
13.5.4 GVA-DA9772 PLL Configuration.......................................................................................................42
13.5.4.1 GVA-DA9772 to GVA-395 Interface Table................................................................................................ 43
13.5.4.2 GVA-DA9772 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 44
13.5.4.3 GVA-DA9772 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 45
14.0 GVA-395 CONFIGURATION JUMPER SETTINGS ...............................................................................46
14.1.1 GVA-395 Jumper Configuration Table................................................................................................46
15.0 GVA-395 TEST POINT DESCRIPTION....................................................................................................47
16.0 APPENDIX A: GVA-395 HARDWARE ACCELERATOR SCHEMATIC............................................48
17.0 APPENDIX B: GVA-395 SELF TEST FGPA SCHEMATIC ..................................................................49
18.0 APPENDIX C: GVA-395 FLASH EEPROM DOWNLOAD AND SYSTEM CLOCK
CONFIGURATION SPARTAN-II SCHEMATIC.................................................................................................50

GV-395 Virtex-II DSP Hardware Accelerator Manual
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1.0 GVA-395 Introduction and General Description
The GVA-395 Modular DSP Development Platform consists of three Xilinx FPGAs. Two Virtex-II FPGAs are used for Analog Control
(ACX and AC) and two Virtex-II FPGAs are used for Data Processing (DP and DPX) respectively. The DPX FPGA also serves as the
primary FPGA for external communication. A Spartan-II FPGA (EI) is used for interfacing to provide a 5V tolerant external interface.
An additional Spartan-II FPGA is used to assist in programming the bit stream into the Flash EPROM and the configuration of the other
FPGAs.
The platform’s general configuration consists of 12 interchangeable daughter PCBs that allow for a wide range of I/O capability. Eight of
the daughter PCBs are dedicated to the ACX FPGA. Two daughter PCBs are dedicated to the AC FPGA and an additional two daughter
PCBs are dedicated to the DP FPGA. Daughter PCB modules are to be as follows:
•100 MSPS 12 bit A/D (GVA-AD9432)
•170 MSPS 12 bit A/D (GVA-AD9430)
•100 MSPS 14 bit A/D (GVA-AD6645)
•100 MSPS 12 bit D/A (GVA-AD9762)
•160 MSPS 14 bit D/A (GVA-AD9772)
•Customer specific designs may be implemented.
The digitized data from the daughter PCB may be processed by the ACX FPGA and passed to the other FPGPs for further processing.
The processed data may also be sent to the external LVDS data port via the DPX Virtex-II FPGA. A data file may also be uploaded via a
USB or Parallel Port interface and may be imported into MatLab for additional analysis. A data file may also be downloaded to the on-
board SDRAM via two USBs interface for processing by the GVA-395.
The ACX and AC FPGAs have access to an external 256K x 18 ZBT SRAM, the DP FPGAS has access to an external 1M x 18 ZBT
SRAM, and the DPX has access to four external 1M x 18 ZBT SRAMs that can be used for temporary data storage. Each Virtex-II
FPGA also has up to 1,728,000 bits of internal Block SelectRAM. There individual 100 bit dedicated local buses connecting the ACX,
AC, DP and the DPX FPGAs. Additionally, there is a shared 43 bit local buses between the ACX, AC, DP, DPX and the EI FPGAs.
The external interface Spartan II FPGA (EI) is used to provide a +5V CMOS tolerant interface between the Virtex-II FPGAs and other
external devices. However, this FPGA could be used for additional processing as determined by the user.
Using the 48-bit external bus interface, the GVA-395 could be configured to have an off-board interface to an external processor such as
a TMS320C31 or other Digital Signal Processors. Additionally, the GVA-395 can be configured either by the Multilinx JTAG cable or
by the on-board FLASH EPROM. The on-board FLASH EPROM can be programmed through the use of the Multilinx Slave Serial
configuration connector. The Xilinx FPGAs may also access unused address space in the configuration EPROM by interfacing to the
Spartan-II configuration FPGA via either the FPGA local bus or the dedicated 32 bit Spartan-II external interface bus. For non-specific
clock requirements, an external clock source is available.
Additional features are listed below and will be explained in detail in Section 2.0.
•4 Virtex™-II FPGAs for Signal Processing
•1 Spartan™-II FPGA for External Interface
•1 Spartan™-II FPGA for Configuration Control
•3 USB interfaces
•Supports Xilinx ChipScope-ILA
•12 Interchangable I/O Daughter PCB capability
•Dedicated external communication FPGA for analog control
•Eight Digital Clock Managers per Virtex-II FPGA
•Up to 168 18x18 Multipliers per Virtex-II FPGA
•+5 V tolerant 48 bit external I/O
•32 Bit LVDS interface
•FPGA logic expansion (1.5M to 3M gates)
•Each Virtex-II FPGA has at least a dedicated 256K x 18 ZBT SRAM
•Up to 3,024,000 bits of internal Block SelectRAM™
•100 bit local bus between the each of Virtex-II FPGAs
•43 bit shared local bus between Virtex-II and Spartan-II FPGAs
•JTAG download configurable
•On-board 16M x 8 FLASH EPROM
•On-board FLASH EPROM programming
•On-board 20 Amp 1.5V Core Power supply
•Programmable A/D and D/A sample clocks
•On-board 50 MHz clock oscillator (which can be doubled by the Virtex-II DLL).
•External high stability clock Input
•Four bit DIP Switch for internal use by FPGAs

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1.1.1 GVA-395 DSP Demonstration Platform Block Diagram

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2.0 GVA-395 Power Configuration
The GVA-395 Hardware Accelerator was delivered with Molex power connector. Care should be taken to insure
that the proper power levels are applied to this power connector. The power configuration is shown in Table 2.1.1.
Power Connector Pin No. Power Connector Wire Color
1 Ground Black
2 Ground Black
3 Ground Black
4 Ground Black
5 +5V Red
6 +5V Red
7 +5V Red
8 +5V Red
2.1.1 GVA-395 Power Configuration Table
The GVA-395 Hardware Accelerator comes configured for a single supply mode (+5V).
3.0 Initial GVA-395 Diagnostic Check-out
In order to verify proper operation of the GVA-395, the customer should perform the following tests upon receipt of
the unit. The GVA-395 on-board Flash EEPROM when delivered is configured with the diagnostic program for all
of the tests. Additionally, the GVA-395 is setup to configure the FPGAs for the diagnostic routine.
1. Insure that a jumper block is on the jumper block at JP5 and JP9.
2. Connect the power cable to at least a 3 A +5V regulated power supply as describe in Section 2.0.
3. Attach a 34-wire ribbon cable to J1 and J2 for the LVDS loop back test.
4. Attach a 34-wire ribbon cable to J4 and J5 for the LVTTL loop back test.
5. Apply power to the GVA-395.
6. Verify that the proper voltages are present: +5V->TP8, +3.3V->TP9, +2.5V->TP10, 1.5V->TP11.
7. The LEDS of AR3 will toggle while the FPGA are being programmed
8. Once the tests which are described in Section 16 are run, all of the LEDs (D1 thru D40) should be lite. This
indicates that the tests have been successfully completed.
9. Using a function generator, an analog signal should be connected to P1 thru P4. The same waveform may
then be viewed with either an oscilloscope or spectrum analyzer at P7 thru P10. It should be noted that the
customer should use an anti-aliasing filter such as SLP-30 (Mini-Circuits) on each input channel and a
similar smoothing filter on each output channel. Without the filters, excessive noise may be present.
10. The diagnostic tests may be re-initiated by pressing the reset button SW1.

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4.0 Xilinx FPGA Configuration
The three Xilinx FPGAs may be configured three ways.
4.1 JTAG Cable Configuration
To use the JTAG download cable, the jumper block must be installed on JP1 and jumper block on JP9 must be
removed. The Virtex-II FGPA at U10 will be configured first, then the Virtex-II FPGA at U12, then the Virtex-II
FPGA at U14, then the Virtex-II FPGA at U16, and finally the Spartan II FPGA at U18. Attach the JTAP Cable to
JP10 as follows: VCC ->1, GND->2, TDO -> 3, TDI -> 4, TCK ->5, TMS ->6. Pin 1 will be the pin closest to SW1.
4.2 Slave Serial Cable Configuration
To use the Slave Serial download cable, a jumper block must be installed on JP1 and JP9. The Virtex-II FGPA at
U10 will be configured first, then the Virtex-II FPGA at U12, then the Virtex-II FPGA at U14, then the Virtex-II
FPGA at U16, and finally the Spartan II FPGA at U18. Attach the Slave Serial Cable to JP5 as follows: VCC -> 1,
GND -> 2, CCLK -> 4, DONE -> 5, DIN -> 6, PROG -> 7, INIT -> 8, RST -> 9. Pin 1 will be the pin closest to
U13.
4.3 Parallel Down-Load Configuration
To use the parallel Flash EPROM (U2) to configure the Xilinx FPGAs, the jumper block at JP3 and JP9 must be
installed and the jumper block on JP2 must be removed. The EPROM file must be programmed from the bottom up.
This file must then be uploaded to the FLASH EPROM (U37) using the Slave Serial configuration mode. This is
further described in the section below. The Virtex-II FGPA at U10 will be configured first, then the Virtex-II FPGA
at U12, then the Virtex-II FPGA at U14, then the Virtex-II FPGA at U16, and finally the Spartan II FPGA at U18.
4.4 Slave Serial Programming of On-Board EEPROM (U2)
1. Install the jumper blocks on JP1, JP2 and JP9.
2. Remove the jumper blocks from JP3.
3. Using the Parallel Cable IV Programming Adapter, connect the Slave Serial cable to the JP5 of the GVA-
395 as shown in the table below.
4. Apply power to the GVA-395.
5. Press the reset button SW1.
6. LED D41 will be lited for approximately 10 seconds while the Flash Memory is being erased.
7. Wait for the LED D41 to extinguish.
8. It is necessary to use the serial cable connection for the Programming Adapter in order to use a the slower
57 Kbps serial transfer rate.
9. From the Xilinx Foundation Project Manager, select the Programming icon.
10. Select the Hardware Debugger.
11. From the Hardware Debugger, select the desire exo file to be programmed into the EEPROM. Please note
that the FPGA will also be programmed as the data is being written into the EEPROM.
12. While the data is being written into the EEPROM, the LEDs D42 thru D44 will be toggling
13. When all of the LED D41 thru D44 are lite, the program function has been completed.
14. Remove power from the GVA-395 and remove the Slave Serial cable. Install that jumper blocks are install
on JP3 and JP9 with the jumper block on JP2 is removed. When power is reapplied, the GVA-395 will
configured from the EEPROM.

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Slave Serial Signal JP5 Connection
VCC 1
GND 2
CCLK 4
DONE 5
DIN 6
PROG 7
INIT 8
4.4.1.1 EEPROM Slave Serial Programming Configuration Table
5.0 Flash EEPROM Configuration FPGA (U1)
Normally, this FPGA will be configured by the serial prom (U3) which is programmed at the factory to perform the
configurations operations described in Section 4. However, this FPGA maybe reprogrammed by installing a jumper
block on JP4. The FPGA may now be reprogrammed by connecting the JTAG download cable to JP7 as follows:
VCC ->1, GND->2, TDO -> 3, TDI -> 4, TCK ->5, TMS ->6. This is not recommended but it would have no
adverse effects on the GVA-395 as long as the configuration pins for the other FPGAs are not used. Please refer to
the schematic for additional information.
6.0 On-Board System Clock Configuration
The GVA-395 uses an 50 MHz oscillator to generate the on-board system clock. which has a SG-615 form factor such as those
found in the Digi-Key catalog. The System clock is on pin AF18 for Virtex-II FPGAs and on pin 15 of the Spartan-II FPGAs. To
select the on-board oscillator as the system clock connect a jumper block between pins1 and 2 of JP8
6.1 External Clock Configuration
An exterior clock source (P1) may be selected as the system clock by installing a jumper block between pins 2 and 3
of JP8. Insure that this clock source meet the TTL minimum value (Vih = 2.4V and Vil = 0.4V) and does not exceed
7V in reference to Ground before attaching the source to P1.
7.0 Xilinx FPGA Power-On Reset and Manual Reset Push Button Switch
The power-on reset may be used for initialization purposes. There is also a manual reset push button switch (SW1)
which will reactive the reset signal. It should be noted that if the +3.3V supply voltage drops below +3.00V the
power-on reset will trigger.
Signal
Name
ACX FPGA
(U10)
Pin No.
AC FPGA
(U12)
Pin No.
DP FPGA
(U14)
Pin No.
DPX FPGA
(U16)
Pin No.
E1 FPGA
(U18)
Pin No.
RESETL AG18 AG18 AG18 AG18 18
7.1.1 Power-on Reset Interconnect Table

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8.0 ACX FPGA (U10)
8.1 ACX FPGA (U10) to Daughter I/O PCB Interface.
. The data is then transferred to the Xilinx ACX FPGA (U10). The data may then be processed by the FPGA.
Signal PC1 Pin No. ACX FPGA Pin Signal PC2 Pin No. ACX FPGA Pin
AD0_DN0 1 E1 AD1_DN0 1 M1
AD0_DP0 2 D1 AD1_DP0 2 L1
AD0_DN1 3 E2 AD1_DN1 3 M2
AD0_DP1 4 D2 AD1_DP1 4 L2
AD0_DN2 5 E3 AD1_DN2 5 M3
AD0_DP2 6 D3 AD1_DP2 6 L3
AD0_DN3 7 G1 AD1_DN3 7 L4
AD0_DP3 8 F1 AD1_DP3 8 K4
AD0_DN4 9 G2 AD1_DN4 9 P2
AD0_DP4 10 F2 AD1_DP4 10 N2
AD0_DN5 11 G3 AD1_DN5 11 N4
AD0_DP5 12 F3 AD1_DP5 12 M4
AD0_DN6 13 F4 AD1_DN6 13 P3
AD0_DP6 14 E4 AD1_DP6 14 N3
AD0_DN7 15 F5 AD1_DN7 15 P5
AD0_DP7 16 G5 AD1_DP7 16 N5
AD0_DN8 17 J1 AD1_DN8 17 N6
AD0_DP8 18 H2 AD1_DP8 18 P6
AD0_DN9 19 J3 AD1_DN9 19 T2
AD0_DP9 20 H3 AD1_DP9 20 R1
AD0_DN10 21 J4 AD1_DN10 21 T3
AD0_DP10 22 H4 AD1_DP10 22 R3
AD0_DN11 23 J5 AD1_DN11 23 R4
AD0_DP11 24 H5 AD1_DP11 24 P4
AD0_CLKN 25 U1 AD1_CLKN 25 U3
ADO_CLK 26 U2 AD1_CLK 26 V4
+3.3V 27 No. Connect +3.3V 27 No. Connect
+3.3V 28 No. Connect +3.3V 28 No. Connect
+5V 29 No. Connect +5V 29 No. Connect
+5V 30 No. Connect +5V 30 No. Connect
AD0_DN12 31 E19 (GCLKP) AD1_DN12 31 K18 (GCLKP)
AD0_DP12 32 E18 (GCLKS) AD1_DP12 32 J18 (GCLKS)
AD0_DN13 33 K2 AD1_DN13 33 L6
AD0_DP13 34 J2 AD1_DP13 34 M6
AD0_DN14 35 L5 AD1_DN14 35 N7
AD0_DP14 36 K5 AD1_DP14 36 M7
AD0_DN15 37 J6 AD1_DN15 37 N8
AD0_DP15 38 K6 AD1_DP15 38 P8
DGND 39 No. Connect DGND 39 No. Connect
DGND 40 No. Connect DGND 40 No. Connect
DGND 41 No. Connect DGND 41 No. Connect
DGND 42 No. Connect DGND 42 No. Connect
DGND 43 No. Connect DGND 43 No. Connect
8.1.1.1 ACX FPGA (U10) to PC1 and PC2 Interconnection Table

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Signal PC3 Pin No. ACX FPGA Pin Signal PC4 Pin No. ACX FPGA Pin
AD2_DN0 1 AA1 AD3_DN0 1 AE2
AD2_DP0 2 AB1 AD3_DP0 2 AF1
AD2_DN1 3 AA2 AD3_DN1 3 AF2
AD2_DP1 4 AB2 AD3_DP1 4 AG2
AD2_DN2 5 AA4 AD3_DN2 5 AF3
AD2_DP2 6 AB4 AD3_DP2 6 AG3
AD2_DN3 7 AA5 AD3_DN3 7 AH1
AD2_DP3 8 AB5 AD3_DP3 8 AJ1
AD2_DN4 9 AD1 AD3_DN4 9 AH2
AD2_DP4 10 AC1 AD3_DP4 10 AJ2
AD2_DN5 11 AC2 AD3_DN5 11 AH3
AD2_DP5 12 AD2 AD3_DP5 12 AJ3
AD2_DN6 13 AC3 AD3_DN6 13 AK2
AD2_DP6 14 AD3 AD3_DP6 14 AL2
AD2_DN7 15 AC4 AD3_DN7 15 AL1
AD2_DP7 16 AD4 AD3_DP7 16 AK1
AD2_DN8 17 AB6 AD3_DN8 17 AH6
AD2_DP8 18 AC6 AD3_DP8 18 AJ5
AD2_DN9 19 AD5 AD3_DN9 19 AJ4
AD2_DP9 20 AE5 AD3_DP9 20 AK4
AD2_DN10 21 AE4 AD3_DN10 21 AF5
AD2_DP10 22 AF4 AD3_DP10 22 AG5
AD2_DN11 23 V5 AD3_DN11 23 AF6
AD2_DP11 24 W5 AD3_DP11 24 AG6
AD2_CLKN 25 V1 AD3_CLKN 25 W3
AD2_CLK 26 V2 AD3_CLK 26 Y3
+3.3V 27 No. Connect +3.3V 27 No. Connect
+3.3V 28 No. Connect +3.3V 28 No. Connect
+5V 29 No. Connect +5V 29 No. Connect
+5V 30 No. Connect +5V 30 No. Connect
AD2_DN12 31 E17 (GCLKP) AD3_DN12 31 H17 (GCLKP)
AD2_DP12 32 E16 (GCLKS) AD3_DP12 32 H16 (GCLKS)
AD2_DN13 33 V6 AD3_DN13 33 AG4
AD2_DP13 34 W6 AD3_DP13 34 AH5
AD2_DN14 35 V7 AD3_DN14 35 AD6
AD2_DP14 36 W7 AD3_DP14 36 AE6
AD2_DN15 37 Y7 AD3_DN15 37 AD7
AD2_DP15 38 AA8 AD3_DP15 38 AE7
DGND 39 No. Connect DGND 39 No. Connect
DGND 40 No. Connect DGND 40 No. Connect
DGND 41 No. Connect DGND 41 No. Connect
DGND 42 No. Connect DGND 42 No. Connect
DGND 43 No. Connect DGND 43 No. Connect
8.1.1.2 ACX FPGA (U10) to PC3 and PC4 Interconnection Table

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Signal PC5 Pin No. ACX FPGA Pin Signal PC6 Pin No. ACX FPGA Pin
DA0_DN0 1 E34 DA1_DN0 1 K31
DA0_DP0 2 D34 DA1_DP0 2 K30
DA0_DN1 3 E33 DA1_DN1 3 M34
DA0_DP1 4 D33 DA1_DP1 4 L34
DA0_DN2 5 E32 DA1_DN2 5 M33
DA0_DP2 6 D32 DA1_DP2 6 L33
DA0_DN3 7 F31 DA1_DN3 7 M32
DA0_DP3 8 E31 DA1_DP3 8 L32
DA0_DN4 9 G34 DA1_DN4 9 M31
DA0_DP4 10 F34 DA1_DP4 10 L31
DA0_DN5 11 G33 DA1_DN5 11 L30
DA0_DP5 12 F33 DA1_DP5 12 K29
DA0_DN6 13 G32 DA1_DN6 13 L29
DA0_DP6 14 F32 DA1_DP6 14 M29
DA0_DN7 15 F30 DA1_DN7 15 P33
DA0_DP7 16 G30 DA1_DP7 16 N33
DA0_DN8 17 J34 DA1_DN8 17 P32
DA0_DP8 18 H33 DA1_DP8 18 N32
DA0_DN9 19 J31 DA1_DN9 19 P31
DA0_DP9 20 H31 DA1_DP9 20 N31
DA0_DN10 21 H29 DA1_DN10 21 P30
DA0_DP10 22 G29 DA1_DP10 22 N30
DA0_DN11 23 J29 DA1_DN11 23 N29
DA0_DP11 24 H28 DA1_DP11 24 P29
DA0_CLKN 25 V31 DA1_CLKN 25 U34
DA0_CLK 26 U31 DA1_CLK 26 U33
+3.3V 27 No. Connect +3.3V 27 No. Connect
+3.3V 28 No. Connect +3.3V 28 No. Connect
+5V 29 No. Connect +5V 29 No. Connect
+5V 30 No. Connect +5V 30 No. Connect
DA0_DN12 31 K33 DA1_DN12 31 R28
DA0_DP12 32 J33 DA1_DP12 32 R29
DA0_DN13 33 J32 DA1_DN13 33 U30
DA0_DP13 34 H32 DA1_DP13 34 T30
DA0_DN14 35 H30 DA1_DN14 35 T29
DA0_DP14 36 J30 DA1_DP14 36 U29
DA0_DN15 37 L28 DA1_DN15 37 U28
DA0_DP15 38 K28 DA1_DP15 38 T28
DGND 39 No. Connect DGND 39 No. Connect
DGND 40 No. Connect DGND 40 No. Connect
DGND 41 No. Connect DGND 41 No. Connect
DGND 42 No. Connect DGND 42 No. Connect
DGND 43 No. Connect DGND 43 No. Connect
8.1.1.3 ACX FPGA (U10) to PC6 and PC7 Interconnection Table

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Signal PC8 Pin No. ACX FPGA Pin Signal PC9 Pin No. ACX FPGA Pin
DA2_DN0 1 V34 DA3_DN0 1 AD26
DA2_DP0 2 V33 DA3_DP0 2 AE26
DA2_DN1 3 V27 DA3_DN1 3 AD28
DA2_DP1 4 V26 DA3_DP1 4 AE28
DA2_DN2 5 V28 DA3_DN2 5 AE25
DA2_DP2 6 W28 DA3_DP2 6 AF25
DA2_DN3 7 W31 DA3_DN3 7 AE27
DA2_DP3 8 Y31 DA3_DP3 8 AF27
DA2_DN4 9 Y29 DA3_DN4 9 AE29
DA2_DP4 10 Y28 DA3_DP4 10 AF29
DA2_DN5 11 W27 DA3_DN5 11 AF26
DA2_DP5 12 Y27 DA3_DP5 12 AG26
DA2_DN6 13 AB30 DA3_DN6 13 AF28
DA2_DP6 14 AA30 DA3_DP6 14 AG28
DA2_DN7 15 AA33 DA3_DN7 15 AF30
DA2_DP7 16 AB33 DA3_DP7 16 AG30
DA2_DN8 17 AA31 DA3_DN8 17 AG31
DA2_DP8 18 AB31 DA3_DP8 18 AF31
DA2_DN9 19 AA29 DA3_DN9 19 AG32
DA2_DP9 20 AB29 DA3_DP9 20 AF32
DA2_DN10 21 AB32 DA3_DN10 21 AG29
DA2_DP10 22 AC32 DA3_DP10 22 AH29
DA2_DN11 23 AD31 DA3_DN11 23 AH32
DA2_DP11 24 AC31 DA3_DP11 24 AJ32
DA2_CLKN 25 W32 DA3_CLKN 25 V30
DA2_CLK 26 V32 DA3_CLK 26 W30
+3.3V 27 No. Connect +3.3V 27 No. Connect
+3.3V 28 No. Connect +3.3V 28 No. Connect
+5V 29 No. Connect +5V 29 No. Connect
+5V 30 No. Connect +5V 30 No. Connect
DA2_DN12 31 AC34 DA3_DN12 31 AK31
DA2_DP12 32 AD34 DA3_DP12 32 AJ31
DA2_DN13 33 AC33 DA3_DN13 33 AK32
DA2_DP13 34 AD33 DA3_DP13 34 AL32
DA2_DN14 35 Y26 DA3_DN14 35 AK33
DA2_DP14 36 AA26 DA3_DP14 36 AL33
DA2_DN15 37 Y25 DA3_DN15 37 AK34
DA2_DP15 38 AA25 DA3_DP15 38 AL34
DGND 39 No. Connect DGND 39 No. Connect
DGND 40 No. Connect DGND 40 No. Connect
DGND 41 No. Connect DGND 41 No. Connect
DGND 42 No. Connect DGND 42 No. Connect
DGND 43 No. Connect DGND 43 No. Connect
8.1.1.4 ACX FPGA (U10) to PC8 and PC9 Interconnection Table

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8.2 ACX FPGA HP Logic Analyzer Mictor Connector
Signal HC1 Pin No. ACX FPGA Pin No.
No Connection 1
No Connection 2
No Connection 3
No Connection 4
HP0_SIG0 5 C7
HP0_SIG1 6 C8
HP0_SIG2 7 C13
HP0_SIG3 8 C14
HP0_SIG4 9 C16
HP0_SIG5 10 C15
HP0_SIG6 11 D9
HP0_SIG7 12 C9
HP0_SIG8 13 C11
HP0_SIG9 14 C12
HP0_SIG10 15 D12
HP0_SIG11 16 D13
HP0_SIG12 17 D10
HP0_SIG13 18 D11
HP0_SIG14 19 E8
HP0_SIG15 20 E9
HP0_SIG16 21 E13
HP0_SIG17 22 E14
HP0_SIG18 23 F14
HP0_SIG19 24 F13
HP0_SIG20 25 G12
HP0_SIG21 26 G13
HP0_SIG22 27 F15
HP0_SIG23 28 G15
HP0_SIG24 29 G16
HP0_SIG25 30 G17
HP0_SIG26 31 F16
HP0_SIG27 32 F17
HP0_SIG28 33 E11
HP0_SIG29 34 E10
HP0_SIG30 35 F10
HP0_SIG31 36 G9
HP0_SIG32 37 G10
HP0_SIG33 38 G11
DGND 39 No Connection
DGND 40 No Connection
DGND 41 No Connection
DGND 42 No Connection
DGND 43 No Connection
8.2.1.1 ACX FPGA (U10) to HC1 Interconnection Table

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8.3 ACX FPGA 256K X 16 ZBT RAM
Each Virtex-II FPGA has access to a 256K x 18 ZBT RAM. The access time for each Static RAM is 7.5
nanoseconds. Refer to the data sheet for the IDT71V3558 for more detailed information. The interconnection is
shown in the table below.
Description Signal Pin No. Description Signal Pin No.
Address Bit 0 ZBT0_A0 A31 Data Bit 0 ZBT0_D0 A12
Address Bit 1 ZBT0_A1 A30 Data Bit 1 ZBT0_D1 A11
Address Bit 2 ZBT0_A2 A28 Data Bit 2 ZBT0_D2 A9
Address Bit 3 ZBT0_A3 A29 Data Bit 3 ZBT0_D3 A7
Address Bit 4 ZBT0_A4 A26 Data Bit 4 ZBT0_D4 A6
Address Bit 5 ZBT0_A5 A24 Data Bit 5 ZBT0_D5 A5
Address Bit 6 ZBT0_A6 A23 Data Bit 6 ZBT0_D6 A4
Address Bit 7 ZBT0_A7 B32 Data Bit 7 ZBT0_D7 B12
Address Bit 8 ZBT0_A8 B31 Data Bit 8 ZBT0_D8 B11
Address Bit 9 ZBT0_A9 B30 Data Bit 9 ZBT0_D9 B10
Address Bit 10 ZBT0_A10 B28 Data Bit 10 ZBT0_D10 B9
Address Bit 11 ZBT0_A11 B29 Data Bit 11 ZBT0_D11 B8
Address Bit 12 ZBT0_A12 B27 Data Bit 12 ZBT0_D12 B7
Address Bit 13 ZBT0_A13 B24 Data Bit 13 ZBT0_D13 B6
Address Bit 14 ZBT0_A14 B23 Data Bit 14 ZBT0_D14 B5
Address Bit 15 ZBT0_A15 B22 Data Bit 15 ZBT0_D15 B4
Address Bit 16 ZBT0_A16 B21 Data Bit 16 ZBT0_D16 B3
Address Bit 17 ZBT0_A17 C33 Data Bit 17 ZBT0_D17 C2
Address Bit 18 ZBT0_A18 C28 RAM ReDA / Write ZBT0_RW B13
Address Bit 19 ZBT0_A19 C27 RAM Byte Write
Enable 1
ZBT0_BW1 D18
RAM Clock ZBT0_CLK B14 RAM Byte Write
Enable 2
ZBT0_BW2 D19
RAM Clock
Enable
ZBT0_CEN C19 RAM Linear Burst
Order
ZBT0_LBO D6
RAM Chip
Enable
ZBT0_CE C18 RAM Internal
Register LoDA
ZBT0_ALD D8
RAM Output Enable ZBT0_OE C6
8.3.1 ACX FPGA (U10) ZBT RAM Pin Configuration Table
8.4 ACX FPGA LED Configuration.
The each Virtex-II FPGA has 10 amber LEDs for general purpose use.
Signal LED ACX FPGA Pin No.
ACXLED0 D1 K21
ACXLED1 D2 K20
ACXLED2 D3 C22
ACXLED3 D4 C23
ACXLED4 D5 E21
ACXLED5 D6 E22
ACXLED6 D7 H21
ACXLED7 D8 H20
ACXLED8 D9 G20
ACXLED9 D10 F20
8.4.1 ACX FPGA (U10) LED Configuration Table

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8.5 ACX FPGA- AC FPGA XBUS Configuration.
Signal ACX Pin No. AC Pin No. Signal ACX Pin No. AC Pin No.
XBUS0 AH11 AH11 XBUS50 AL12 AL12
XBUS1 AL6 AL6 XBUS51 AF14 AF14
XBUS2 AM6 AM6 XBUS52 AF15 AF15
XBUS3 AK6 AK6 XBUS53 AM13 AM13
XBUS4 AJ8 AJ8 XBUS54 AM12 AM12
XBUS5 AM8 AM8 XBUS55 AP12 AP12
XBUS6 AM7 AM7 XBUS56 AP11 AP11
XBUS7 AN3 AN3 XBUS57 AG15 AG15
XBUS8 AM2 AM2 XBUS58 AG16 AG16
XBUS9 AJ10 AJ10 XBUS59 AN14 AN14
XBUS10 AJ9 AJ9 XBUS60 AN13 AN13
XBUS11 AH9 AH9 XBUS61 AP14 AP14
XBUS12 AH10 AH10 XBUS62 AP13 AP13
XBUS13 AN5 AN5 XBUS63 AD16 AD16
XBUS14 AN4 AN4 XBUS64 AD17 AD17
XBUS15 AE12 AE12 XBUS65 AK14 AK14
XBUS16 AE13 AE13 XBUS66 AK13 AK13
XBUS17 AM9 AM9 XBUS67 AL16 AL16
XBUS18 AL8 AL8 XBUS68 AL17 AL17
XBUS19 AP5 AP5 XBUS69 AJ17 AJ17
XBUS20 AP4 AP4 XBUS70 AJ16 AJ16
XBUS21 AG11 AG11 XBUS71 AM15 AM15
XBUS22 AG12 AG12 XBUS72 AM14 AM14
XBUS23 AN7 AN7 XBUS73 AM16 AM16
XBUS24 AN6 AN6 XBUS74 AM17 AM17
XBUS25 AL10 AL10 XBUS75 AF17 AF17
XBUS26 AL9 AL9 XBUS76 AG17 AG17
XBUS27 AF12 AF12 XBUS77 AK16 AK16
XBUS28 AF13 AF13 XBUS78 AK17 AK17
XBUS29 AK10 AK10 XBUS79 AL30 AL30
XBUS30 AK11 AK11 XBUS80 AM31 AM31
XBUS31 AP7 AP7 XBUS81 AG24 AG24
XBUS32 AP6 AP6 XBUS82 AG25 AG25
XBUS33 AH13 AH13 XBUS83 AK28 AK28
XBUS34 AH12 AH12 XBUS84 AL29 AL29
XBUS35 AJ11 AJ11 XBUS85 AM28 AM28
XBUS36 AJ12 AJ12 XBUS86 AM29 AM29
XBUS37 AP9 AP9 XBUS87 AJ27 AJ27
XBUS38 AN8 AN8 XBUS88 AJ26 AJ26
XBUS39 AG13 AG13 XBUS89 AM33 AM33
XBUS40 AG14 AG14 XBUS90 AN32 AN32
XBUS41 AM11 AM11 XBUS91 AG23 AG23
XBUS42 AL11 AL11 XBUS92 AF24 AF24
XBUS43 AN12 AN12 XBUS93 AK26 AK26
XBUS44 AN11 AN11 XBUS94 AK27 AK27
XBUS45 AE14 AE14 XBUS95 AN31 AN31
XBUS46 AE15 AE15 XBUS96 AN30 AN30
XBUS47 AJ13 AJ13 XBUS97 AH26 AH26
XBUS48 AJ14 AJ14 XBUS98 AJ25 AJ25
XBUS49 AL13 AL13 XBUS99 AL27 AL27
8.5.1 ACX FPGA (U10) to AC FPGA (U12) XBUS Configuration Table

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9.0 AC FPGA (U12)
9.1 AC FPGA (U12) to Daughter I/O PCB Interface.
. The data is then transferred to the Xilinx AC FPGA (U12). The data may then be processed by the FPGA.
Signal PC9 Pin No. AC FPGA Pin Signal PC10 Pin No. AC FPGA Pin
AD4_DN0 1 M1 DA4_DN0 1 K31
AD4_DP0 2 L1 DA4_DP0 2 K30
AD4_DN1 3 M2 DA4_DN1 3 M34
AD4_DP1 4 L2 DA4_DP1 4 L34
AD4_DN2 5 M3 DA4_DN2 5 M33
AD4_DP2 6 L3 DA4_DP2 6 L33
AD4_DN3 7 L4 DA4_DN3 7 M32
AD4_DP3 8 K4 DA4_DP3 8 L32
AD4_DN4 9 P2 DA4_DN4 9 M31
AD4_DP4 10 N2 DA4_DP4 10 L31
AD4_DN5 11 N4 DA4_DN5 11 L30
AD4_DP5 12 M4 DA4_DP5 12 K29
AD4_DN6 13 P3 DA4_DN6 13 L29
AD4_DP6 14 N3 DA4_DP6 14 M29
AD4_DN7 15 P5 DA4_DN7 15 P33
AD4_DP7 16 N5 DA4_DP7 16 N33
AD4_DN8 17 N6 DA4_DN8 17 P32
AD4_DP8 18 P6 DA4_DP8 18 N32
AD4_DN9 19 T2 DA4_DN9 19 P31
AD4_DP9 20 R1 DA4_DP9 20 N31
AD4_DN10 21 T3 DA4_DN10 21 P30
AD4_DP10 22 R3 DA4_DP10 22 N30
AD4_DN11 23 R4 DA4_DN11 23 N29
AD4_DP11 24 P4 DA4_DP11 24 P29
AD4_CLKN 25 U3 DA4_CLKN 25 U34
AD4_CLK 26 V4 DA4_CLK 26 U33
+3.3V 27 No. Connect +3.3V 27 No. Connect
+3.3V 28 No. Connect +3.3V 28 No. Connect
+5V 29 No. Connect +5V 29 No. Connect
+5V 30 No. Connect +5V 30 No. Connect
AD4_DN12 31 K18 (GCLKP) DA4_DN12 31 R28
AD4_DP12 32 J18 (GCLKS) DA4_DP12 32 R29
AD4_DN13 33 L6 DA4_DN13 33 U30
AD4_DP13 34 M6 DA4_DP13 34 T30
AD4_DN14 35 N7 DA4_DN14 35 T29
AD4_DP14 36 M7 DA4_DP14 36 U29
AD4_DN15 37 N8 DA4_DN15 37 U28
AD4_DP15 38 P8 DA4_DP15 38 T28
DGND 39 No. Connect DGND 39 No. Connect
DGND 40 No. Connect DGND 40 No. Connect
DGND 41 No. Connect DGND 41 No. Connect
DGND 42 No. Connect DGND 42 No. Connect
DGND 43 No. Connect DGND 43 No. Connect
9.1.1.1 AC FPGA (U12) to PC9 and PC10 Interconnection Table

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9.2 AC FPGA HP Logic Analyzer Mictor Connector
Signal HC1 Pin No. AC FPGA Pin No.
No Connection 1
No Connection 2
No Connection 3
No Connection 4
HP1_SIG0 5 C7
HP1_SIG1 6 C8
HP1_SIG2 7 C13
HP1_SIG3 8 C14
HP1_SIG4 9 C16
HP1_SIG5 10 C15
HP1_SIG6 11 D9
HP1_SIG7 12 C9
HP1_SIG8 13 C11
HP1_SIG9 14 C12
HP1_SIG10 15 D12
HP1_SIG11 16 D13
HP1_SIG12 17 D10
HP1_SIG13 18 D11
HP1_SIG14 19 E8
HP1_SIG15 20 E9
HP1_SIG16 21 E13
HP1_SIG17 22 E14
HP1_SIG18 23 F14
HP1_SIG19 24 F13
HP1_SIG20 25 G12
HP1_SIG21 26 G13
HP1_SIG22 27 F15
HP1_SIG23 28 G15
HP1_SIG24 29 G16
HP1_SIG25 30 G17
HP1_SIG26 31 F16
HP1_SIG27 32 F17
HP1_SIG28 33 E11
HP1_SIG29 34 E10
HP1_SIG30 35 F10
HP1_SIG31 36 G9
HP1_SIG32 37 G10
HP1_SIG33 38 G11
DGND 39 No Connection
DGND 40 No Connection
DGND 41 No Connection
DGND 42 No Connection
DGND 43 No Connection
9.2.1.1 AC FPGA (U12) to HC1 Interconnection Table

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9.3 AC FPGA 256K X 16 ZBT RAM
Each Virtex-II FPGA has access to a 256K x 18 ZBT RAM. The access time for each Static RAM is 7.5
nanoseconds. Refer to the data sheet for the IDT71V3558 for more detailed information. The interconnection is
shown in the table below.
Description Signal Pin No. Description Signal Pin No.
Address Bit 0 ZBT1_A0 A31 Data Bit 0 ZBT1_D0 A12
Address Bit 1 ZBT1_A1 A30 Data Bit 1 ZBT1_D1 A11
Address Bit 2 ZBT1_A2 A28 Data Bit 2 ZBT1_D2 A9
Address Bit 3 ZBT1_A3 A29 Data Bit 3 ZBT1_D3 A7
Address Bit 4 ZBT1_A4 A26 Data Bit 4 ZBT1_D4 A6
Address Bit 5 ZBT1_A5 A24 Data Bit 5 ZBT1_D5 A5
Address Bit 6 ZBT1_A6 A23 Data Bit 6 ZBT1_D6 A4
Address Bit 7 ZBT1_A7 B32 Data Bit 7 ZBT1_D7 B12
Address Bit 8 ZBT1_A8 B31 Data Bit 8 ZBT1_D8 B11
Address Bit 9 ZBT1_A9 B30 Data Bit 9 ZBT1_D9 B10
Address Bit 10 ZBT1_A10 B28 Data Bit 10 ZBT1_D10 B9
Address Bit 11 ZBT1_A11 B29 Data Bit 11 ZBT1_D11 B8
Address Bit 12 ZBT1_A12 B27 Data Bit 12 ZBT1_D12 B7
Address Bit 13 ZBT1_A13 B24 Data Bit 13 ZBT1_D13 B6
Address Bit 14 ZBT1_A14 B23 Data Bit 14 ZBT1_D14 B5
Address Bit 15 ZBT1_A15 B22 Data Bit 15 ZBT1_D15 B4
Address Bit 16 ZBT1_A16 B21 Data Bit 16 ZBT1_D16 B3
Address Bit 17 ZBT1_A17 C33 Data Bit 17 ZBT1_D17 C2
Address Bit 18 ZBT1_A18 C28 RAM ReDA / Write ZBT1_RW B13
Address Bit 19 ZBT1_A19 C27 RAM Byte Write
Enable 1
ZBT1_BW1 D18
RAM Clock ZBT1_CLK B14 RAM Byte Write
Enable 2
ZBT1_BW2 D19
RAM Clock
Enable
ZBT1_CEN C19 RAM Linear Burst
Order
ZBT1_LBO D6
RAM Chip
Enable
ZBT1_CE C18 RAM Internal
Register LoDA
ZBT1_ALD D8
RAM Output Enable ZBT1_OE C6
9.3.1 AC FPGA (U12) ZBT RAM Pin Configuration Table
9.4 AC FPGA LED Configuration.
The each Virtex-II FPGA has 10 amber LEDs for general purpose use.
Signal LED AC FPGA Pin No.
ACLED0 D11 K21
ACLED1 D12 K20
ACLED2 D13 C22
ACLED3 D14 C23
ACLED4 D15 E21
ACLED5 D16 E22
ACLED6 D17 H21
ACLED7 D18 H20
ACLED8 D19 G20
ACLED9 D20 F20
9.4.1 AC FPGA (U12) LED Configuration Table

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9.5 AC FPGA - DP FPGA XBUS_A Configuration.
Signal AC Pin No. DP Pin No. Signal AC Pin No. DP Pin No.
XBUS_A0 AD25 E2 XBUS_A50 AG33 L6
XBUS_A1 AE24 D2 XBUS_A51 AF33 M6
XBUS_A2 AK32 F5 XBUS_A52 AB28 M3
XBUS_A3 AL32 G5 XBUS_A53 AC28 L3
XBUS_A4 AE25 E3 XBUS_A54 AE33 L4
XBUS_A5 AF25 D3 XBUS_A55 AF34 K4
XBUS_A6 AK31 J9 XBUS_A56 AA27 N4
XBUS_A7 AJ31 K9 XBUS_A57 AB27 M4
XBUS_A8 AG29 F4 XBUS_A58 Y25 M2
XBUS_A9 AH29 E4 XBUS_A59 AA25 L2
XBUS_A10 AF26 E1 XBUS_A60 AC33 N8
XBUS_A11 AG26 D1 XBUS_A61 AD33 P8
XBUS_A12 AK33 J8 XBUS_A62 AB32 N6
XBUS_A13 AL33 K8 XBUS_A63 AC32 P6
XBUS_A14 AH32 H7 XBUS_A64 Y26 P5
XBUS_A15 AJ32 J7 XBUS_A65 AA26 N5
XBUS_A16 AF28 H6 XBUS_A66 AC34 P10
XBUS_A17 AG28 G6 XBUS_A67 AD34 R10
XBUS_A18 AF30 L10 XBUS_A68 AD31 P3
XBUS_A19 AG30 L9 XBUS_A69 AC31 N3
XBUS_A20 AE29 G3 XBUS_A70 W27 M1
XBUS_A21 AF29 F3 XBUS_A71 Y27 L1
XBUS_A22 AE27 G2 XBUS_A72 AA29 P9
XBUS_A23 AF27 F2 XBUS_A73 AB29 R9
XBUS_A24 AK34 M10 XBUS_A74 AA31 P2
XBUS_A25 AL34 N10 XBUS_A75 AB31 N2
XBUS_A26 AD28 J6 XBUS_A76 Y29 R4
XBUS_A27 AE28 K6 XBUS_A77 Y28 P4
XBUS_A28 AD26 J5 XBUS_A78 AA33 R8
XBUS_A29 AE26 H5 XBUS_A79 AB33 T8
XBUS_A30 AG31 L7 XBUS_A80 AB30 T3
XBUS_A31 AF31 K7 XBUS_A81 AA30 R3
XBUS_A32 AG32 J4 XBUS_A82 V28 T2
XBUS_A33 AF32 H4 XBUS_A83 W28 R1
XBUS_A34 AB25 G1 XBUS_A84 V34 U7
XBUS_A35 AC25 F1 XBUS_A85 V33 T7
XBUS_A36 AH33 L8 XBUS_A86 W31 T6
XBUS_A37 AJ33 M8 XBUS_A87 Y31 U6
XBUS_A38 AD32 J1 XBUS_A88 V27 U1
XBUS_A39 AE31 H2 XBUS_A89 V26 U2
XBUS_A40 AC27 J3 XBUS_A90 V30 U9
XBUS_A41 AD27 H3 XBUS_A91 W30 U8
XBUS_A42 AH34 M9 XBUS_A92 W32 U3
XBUS_A43 AJ34 N9 XBUS_A93 V32 V4
XBUS_A44 AD30 L5 XBUS_A94 H32 AC9
XBUS_A45 AE30 K5 XBUS_A95 J32 AB9
XBUS_A46 AB26 K2 XBUS_A96 N26 AF1
XBUS_A47 AC26 J2 XBUS_A97 M26 AE2
XBUS_A48 AC29 N7 XBUS_A98 J33 AE6
XBUS_A49 AD29 M7 XBUS_A99 K33 AD6
9.5.1 AC FPGA (U12) to DP FPGA (U14) XBUS_A Configuration Table