GV Virtex-II DSP GVA-395 User manual

GVA-395
Virtex-II Hardware Accelerator
User’s Manual
GV & Associates, Inc
23540 Oriente Way
Ramona, CA 92065
[phone]
www.gvassociates.com

GV-395 Virtex-II DSP Hardware Accelerator Manual
GV & Associates, Inc.
07/10/04
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1.0 GVA-395 INTRODUCTION AND GENERAL DESCRIPTION ...............................................................4
1.1.1 GVA-395 DSP Demonstration Platform Block Diagram.......................................................................5
2.0 GVA-395 POWER CONFIGURATION .......................................................................................................6
2.1.1 GVA-395 Power Configuration Table ...................................................................................................6
3.0 INITIAL GVA-395 DIAGNOSTIC CHECK-OUT ......................................................................................6
4.0 XILINX FPGA CONFIGURATION .............................................................................................................7
4.1 JTAG CABLE CONFIGURATION ......................................................................................................................7
4.2 SLAVE SERIAL CABLE CONFIGURATION .........................................................................................................7
4.3 PARALLEL DOWN-LOAD CONFIGURATION .....................................................................................................7
4.4 SLAVE SERIAL PROGRAMMING OF ON-BOARD EEPROM (U2)......................................................................7
4.4.1.1 EEPROM Slave Serial Programming Configuration Table ............................................................................... 8
5.0 FLASH EEPROM CONFIGURATION FPGA (U1)....................................................................................8
6.0 ON-BOARD SYSTEM CLOCK CONFIGURATION.................................................................................8
6.1 EXTERNAL CLOCK CONFIGURATION ..............................................................................................................8
7.0 XILINX FPGA POWER-ON RESET AND MANUAL RESET PUSH BUTTON SWITCH...................8
7.1.1 Power-on Reset Interconnect Table.......................................................................................................8
8.0 ACX FPGA (U10) ............................................................................................................................................9
8.1 ACX FPGA (U10) TO DAUGHTER I/O PCB INTERFACE.................................................................................9
8.1.1.1 ACX FPGA (U10) to PC1 and PC2 Interconnection Table ............................................................................... 9
8.1.1.2 ACX FPGA (U10) to PC3 and PC4 Interconnection Table .............................................................................10
8.1.1.3 ACX FPGA (U10) to PC6 and PC7 Interconnection Table .............................................................................11
8.1.1.4 ACX FPGA (U10) to PC8 and PC9 Interconnection Table .............................................................................12
8.2 ACX FPGA HP LOGIC ANALYZER MICTOR CONNECTOR ............................................................................13
8.2.1.1 ACX FPGA (U10) to HC1 Interconnection Table ........................................................................................... 13
8.3 ACX FPGA 256K X16 ZBT RAM..............................................................................................................14
8.3.1 ACX FPGA (U10) ZBT RAM Pin Configuration Table .......................................................................14
8.4 ACX FPGA LED CONFIGURATION..............................................................................................................14
8.4.1 ACX FPGA (U10) LED Configuration Table ......................................................................................14
8.5 ACX FPGA- AC FPGA XBUS CONFIGURATION. .......................................................................................15
8.5.1 ACX FPGA (U10) to AC FPGA (U12) XBUS Configuration Table ....................................................15
9.0 AC FPGA (U12) .............................................................................................................................................16
9.1 AC FPGA (U12) TO DAUGHTER I/O PCB INTERFACE..................................................................................16
9.1.1.1 AC FPGA (U12) to PC9 and PC10 Interconnection Table .............................................................................. 16
9.2 AC FPGA HP LOGIC ANALYZER MICTOR CONNECTOR...............................................................................17
9.2.1.1 AC FPGA (U12) to HC1 Interconnection Table .............................................................................................. 17
9.3 AC FPGA 256K X16 ZBT RAM ................................................................................................................18
9.3.1 AC FPGA (U12) ZBT RAM Pin Configuration Table .........................................................................18
9.4 AC FPGA LED CONFIGURATION.................................................................................................................18
9.4.1 AC FPGA (U12) LED Configuration Table ........................................................................................18
9.5 AC FPGA -DP FPGA XBUS_A CONFIGURATION. .....................................................................................19
9.5.1 AC FPGA (U12) to DP FPGA (U14) XBUS_A Configuration Table..................................................19

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10.0 DP FPGA (U14) .............................................................................................................................................20
10.1 DP FPGA (U14) TO DAUGHTER I/O PCB INTERFACE. .................................................................................20
10.1.1.1 DP FPGA (U14) to PC11 and PC12 Interconnection Table ........................................................................ 20
10.2 DP FPGA HP LOGIC ANALYZER MICTOR CONNECTOR ...............................................................................21
10.2.1.1 DP FPGA (U14) to HC2 Interconnection Table .......................................................................................... 21
10.3 DP FPGA 1M X16 ZBT RAM ....................................................................................................................22
10.3.1 DP FPGA (U14) ZBT RAM Pin Configuration Table .........................................................................22
10.4 DP FPGA LED CONFIGURATION. ................................................................................................................22
10.4.1 DP FPGA (U14) LED Configuration Table ........................................................................................22
10.5 DP USB INTERFACE .....................................................................................................................................23
10.5.1 USB Interface for DP FPGA Interconnection Table ...........................................................................23
10.6 DP FPGA -DPX FPGA XBUS_B CONFIGURATION....................................................................................24
10.6.1 DP FPGA (U14) to DPX FPGA (U16) XBUS_B Configuration Table ...............................................24
11.0 DPX FPGA (U16)...........................................................................................................................................25
11.1 DPX FPGA 4X1M X16 ZBT RAM...........................................................................................................25
11.1.1 DPX FPGA (U16) ZBT RAM Pin Configuration Table.......................................................................25
11.2 DPX FPGA LED CONFIGURATION. .............................................................................................................25
11.2.1 DPX FPGA (U16) LED Configuration Table......................................................................................25
11.3 DPX USB INTERFACE ..................................................................................................................................26
11.3.1 USB Interface for DPX FPGA Interconnection Table.........................................................................26
11.4 DPX FPGA LVDS INTERFACE.....................................................................................................................27
11.4.1 DPX FPGA LVDS Bus Interconnection Table for J6 ..........................................................................27
11.4.2 DPX FPGA LVDS Bus Interconnection Table for J7 ..........................................................................27
12.0 EI FPGA (U18)...............................................................................................................................................28
12.1 EI FPGA XE_BUS CONFIGURATION. ..........................................................................................................28
12.1.1 XE_BUS Interconnection Table..........................................................................................................28
12.2 EXTERNAL SPARTAN INTERFACE FPGA CONNECTORS ................................................................................29
12.2.1 External Interface FPGA Bus Interconnection Table for J1................................................................29
12.2.2 External Interface FPGA Bus Interconnection Table for J2................................................................29
12.3 EI FPGA LED..............................................................................................................................................29
13.0 OPTIONAL DAUGHTER I/O PCBS FOR ANALOG CONTROL FPGA (U14) DESCRIPTIONS ....30
13.1 GVA-AD9430 170 MSPS 12 BIT A/D .........................................................................................................30
13.1.1 AC Coupled Analog Input Path ...........................................................................................................30
13.1.2 GVA-AD9430 Output Configuration ...................................................................................................30
13.1.2.1 GVA-AD9430 to GVA-395 PC Connection Interface Table....................................................................... 31
13.1.2.2 GVA-AD9430 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 31
13.1.3 GVA-AD9430 to GVA-395 AC FPGA PC No. 6-9 Connection Table .................................................32
13.1.3.1 GVA-AD9430 Digital Output Format Jumper Configuration Table ........................................................... 33
13.2 GVA-AD9432 100 MSPS 12 BIT A/D .........................................................................................................33
13.2.1 AC Coupled Analog Input Path ...........................................................................................................33
13.2.2 DC Coupled Analog Input Path...........................................................................................................33
13.2.3 GVA-AD9432 Analog Input Configuration..........................................................................................33
13.2.3.1 GVA-AD9432 Analog Input Jumper Configuration Table.......................................................................... 33
13.2.3.2 GVA-AD9432 to GVA-395 PC Connection Interface Table....................................................................... 34
13.2.3.3 GVA-AD9432 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 34
13.2.3.4 GVA-DA9432 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 35
13.3 GVA-DA6645 100 MSPS 14 BIT A/D .........................................................................................................36
13.3.1 AC Coupled Analog Input Path ...........................................................................................................36
13.3.2 DC Coupled Analog Input Path...........................................................................................................36
13.3.3 GVA-DA6645 Analog Input Configuration..........................................................................................36
13.3.3.1 GVA-AD6645 Analog Input Jumper Configuration Table.......................................................................... 36
13.3.3.2 GVA-DA6645 to GVA-395 Interface Table................................................................................................ 37
13.3.3.3 GVA-AD6645 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 37
13.3.3.4 GVA-DA6645 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 38

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13.4 GVA-DA9762 125 MSPS 12 BIT D/A .........................................................................................................39
13.4.1 Single-Ended Output Path ...................................................................................................................39
13.4.2 Differential Coupled Analog Output Path ...........................................................................................39
13.4.3 GVA-DA9762 Analog Output Configuration.......................................................................................39
13.4.3.1 GVA-DA9762 Analog Output Jumper Configuration Table ....................................................................... 39
13.4.3.2 GVA-DA9762 to GVA-395 Interface Table................................................................................................ 40
13.4.3.3 GVA-DA9762 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 40
13.4.3.4 GVA-DA9762 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 41
13.5 GVA-DA9772 125 MSPS 14 BIT D/A .........................................................................................................42
13.5.1 Single-Ended Output Path ...................................................................................................................42
13.5.2 Differential Coupled Analog Output Path ...........................................................................................42
13.5.3 GVA-DA9772 Analog Output Configuration.......................................................................................42
13.5.3.1 GVA-DA9772 Analog Output Jumper Configuration Table ....................................................................... 42
13.5.4 GVA-DA9772 PLL Configuration.......................................................................................................42
13.5.4.1 GVA-DA9772 to GVA-395 Interface Table................................................................................................ 43
13.5.4.2 GVA-DA9772 to GVA-395 AC FPGA PC No. 2-5 Connection Table....................................................... 44
13.5.4.3 GVA-DA9772 to GVA-395 AC FPGA PC No. 6-9 Connection Table....................................................... 45
14.0 GVA-395 CONFIGURATION JUMPER SETTINGS ...............................................................................46
14.1.1 GVA-395 Jumper Configuration Table................................................................................................46
15.0 GVA-395 TEST POINT DESCRIPTION....................................................................................................47
16.0 APPENDIX A: GVA-395 HARDWARE ACCELERATOR SCHEMATIC............................................48
17.0 APPENDIX B: GVA-395 SELF TEST FGPA SCHEMATIC ..................................................................49
18.0 APPENDIX C: GVA-395 FLASH EEPROM DOWNLOAD AND SYSTEM CLOCK
CONFIGURATION SPARTAN-II SCHEMATIC.................................................................................................50

GV-395 Virtex-II DSP Hardware Accelerator Manual
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1.0 GVA-395 Introduction and General Description
The GVA-395 Modular DSP Development Platform consists of three Xilinx FPGAs. Two Virtex-II FPGAs are used for Analog Control
(ACX and AC) and two Virtex-II FPGAs are used for Data Processing (DP and DPX) respectively. The DPX FPGA also serves as the
primary FPGA for external communication. A Spartan-II FPGA (EI) is used for interfacing to provide a 5V tolerant external interface.
An additional Spartan-II FPGA is used to assist in programming the bit stream into the Flash EPROM and the configuration of the other
FPGAs.
The platform’s general configuration consists of 12 interchangeable daughter PCBs that allow for a wide range of I/O capability. Eight of
the daughter PCBs are dedicated to the ACX FPGA. Two daughter PCBs are dedicated to the AC FPGA and an additional two daughter
PCBs are dedicated to the DP FPGA. Daughter PCB modules are to be as follows:
•100 MSPS 12 bit A/D (GVA-AD9432)
•170 MSPS 12 bit A/D (GVA-AD9430)
•100 MSPS 14 bit A/D (GVA-AD6645)
•100 MSPS 12 bit D/A (GVA-AD9762)
•160 MSPS 14 bit D/A (GVA-AD9772)
•Customer specific designs may be implemented.
The digitized data from the daughter PCB may be processed by the ACX FPGA and passed to the other FPGPs for further processing.
The processed data may also be sent to the external LVDS data port via the DPX Virtex-II FPGA. A data file may also be uploaded via a
USB or Parallel Port interface and may be imported into MatLab for additional analysis. A data file may also be downloaded to the on-
board SDRAM via two USBs interface for processing by the GVA-395.
The ACX and AC FPGAs have access to an external 256K x 18 ZBT SRAM, the DP FPGAS has access to an external 1M x 18 ZBT
SRAM, and the DPX has access to four external 1M x 18 ZBT SRAMs that can be used for temporary data storage. Each Virtex-II
FPGA also has up to 1,728,000 bits of internal Block SelectRAM. There individual 100 bit dedicated local buses connecting the ACX,
AC, DP and the DPX FPGAs. Additionally, there is a shared 43 bit local buses between the ACX, AC, DP, DPX and the EI FPGAs.
The external interface Spartan II FPGA (EI) is used to provide a +5V CMOS tolerant interface between the Virtex-II FPGAs and other
external devices. However, this FPGA could be used for additional processing as determined by the user.
Using the 48-bit external bus interface, the GVA-395 could be configured to have an off-board interface to an external processor such as
a TMS320C31 or other Digital Signal Processors. Additionally, the GVA-395 can be configured either by the Multilinx JTAG cable or
by the on-board FLASH EPROM. The on-board FLASH EPROM can be programmed through the use of the Multilinx Slave Serial
configuration connector. The Xilinx FPGAs may also access unused address space in the configuration EPROM by interfacing to the
Spartan-II configuration FPGA via either the FPGA local bus or the dedicated 32 bit Spartan-II external interface bus. For non-specific
clock requirements, an external clock source is available.
Additional features are listed below and will be explained in detail in Section 2.0.
•4 Virtex™-II FPGAs for Signal Processing
•1 Spartan™-II FPGA for External Interface
•1 Spartan™-II FPGA for Configuration Control
•3 USB interfaces
•Supports Xilinx ChipScope-ILA
•12 Interchangable I/O Daughter PCB capability
•Dedicated external communication FPGA for analog control
•Eight Digital Clock Managers per Virtex-II FPGA
•Up to 168 18x18 Multipliers per Virtex-II FPGA
•+5 V tolerant 48 bit external I/O
•32 Bit LVDS interface
•FPGA logic expansion (1.5M to 3M gates)
•Each Virtex-II FPGA has at least a dedicated 256K x 18 ZBT SRAM
•Up to 3,024,000 bits of internal Block SelectRAM™
•100 bit local bus between the each of Virtex-II FPGAs
•43 bit shared local bus between Virtex-II and Spartan-II FPGAs
•JTAG download configurable
•On-board 16M x 8 FLASH EPROM
•On-board FLASH EPROM programming
•On-board 20 Amp 1.5V Core Power supply
•Programmable A/D and D/A sample clocks
•On-board 50 MHz clock oscillator (which can be doubled by the Virtex-II DLL).
•External high stability clock Input
•Four bit DIP Switch for internal use by FPGAs

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1.1.1 GVA-395 DSP Demonstration Platform Block Diagram

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07/10/04
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2.0 GVA-395 Power Configuration
The GVA-395 Hardware Accelerator was delivered with Molex power connector. Care should be taken to insure
that the proper power levels are applied to this power connector. The power configuration is shown in Table 2.1.1.
Power Connector Pin No. Power Connector Wire Color
1 Ground Black
2 Ground Black
3 Ground Black
4 Ground Black
5 +5V Red
6 +5V Red
7 +5V Red
8 +5V Red
2.1.1 GVA-395 Power Configuration Table
The GVA-395 Hardware Accelerator comes configured for a single supply mode (+5V).
3.0 Initial GVA-395 Diagnostic Check-out
In order to verify proper operation of the GVA-395, the customer should perform the following tests upon receipt of
the unit. The GVA-395 on-board Flash EEPROM when delivered is configured with the diagnostic program for all
of the tests. Additionally, the GVA-395 is setup to configure the FPGAs for the diagnostic routine.
1. Insure that a jumper block is on the jumper block at JP5 and JP9.
2. Connect the power cable to at least a 3 A +5V regulated power supply as describe in Section 2.0.
3. Attach a 34-wire ribbon cable to J1 and J2 for the LVDS loop back test.
4. Attach a 34-wire ribbon cable to J4 and J5 for the LVTTL loop back test.
5. Apply power to the GVA-395.
6. Verify that the proper voltages are present: +5V->TP8, +3.3V->TP9, +2.5V->TP10, 1.5V->TP11.
7. The LEDS of AR3 will toggle while the FPGA are being programmed
8. Once the tests which are described in Section 16 are run, all of the LEDs (D1 thru D40) should be lite. This
indicates that the tests have been successfully completed.
9. Using a function generator, an analog signal should be connected to P1 thru P4. The same waveform may
then be viewed with either an oscilloscope or spectrum analyzer at P7 thru P10. It should be noted that the
customer should use an anti-aliasing filter such as SLP-30 (Mini-Circuits) on each input channel and a
similar smoothing filter on each output channel. Without the filters, excessive noise may be present.
10. The diagnostic tests may be re-initiated by pressing the reset button SW1.

GV-395 Virtex-II DSP Hardware Accelerator Manual
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07/10/04
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4.0 Xilinx FPGA Configuration
The three Xilinx FPGAs may be configured three ways.
4.1 JTAG Cable Configuration
To use the JTAG download cable, the jumper block must be installed on JP1 and jumper block on JP9 must be
removed. The Virtex-II FGPA at U10 will be configured first, then the Virtex-II FPGA at U12, then the Virtex-II
FPGA at U14, then the Virtex-II FPGA at U16, and finally the Spartan II FPGA at U18. Attach the JTAP Cable to
JP10 as follows: VCC ->1, GND->2, TDO -> 3, TDI -> 4, TCK ->5, TMS ->6. Pin 1 will be the pin closest to SW1.
4.2 Slave Serial Cable Configuration
To use the Slave Serial download cable, a jumper block must be installed on JP1 and JP9. The Virtex-II FGPA at
U10 will be configured first, then the Virtex-II FPGA at U12, then the Virtex-II FPGA at U14, then the Virtex-II
FPGA at U16, and finally the Spartan II FPGA at U18. Attach the Slave Serial Cable to JP5 as follows: VCC -> 1,
GND -> 2, CCLK -> 4, DONE -> 5, DIN -> 6, PROG -> 7, INIT -> 8, RST -> 9. Pin 1 will be the pin closest to
U13.
4.3 Parallel Down-Load Configuration
To use the parallel Flash EPROM (U2) to configure the Xilinx FPGAs, the jumper block at JP3 and JP9 must be
installed and the jumper block on JP2 must be removed. The EPROM file must be programmed from the bottom up.
This file must then be uploaded to the FLASH EPROM (U37) using the Slave Serial configuration mode. This is
further described in the section below. The Virtex-II FGPA at U10 will be configured first, then the Virtex-II FPGA
at U12, then the Virtex-II FPGA at U14, then the Virtex-II FPGA at U16, and finally the Spartan II FPGA at U18.
4.4 Slave Serial Programming of On-Board EEPROM (U2)
1. Install the jumper blocks on JP1, JP2 and JP9.
2. Remove the jumper blocks from JP3.
3. Using the Parallel Cable IV Programming Adapter, connect the Slave Serial cable to the JP5 of the GVA-
395 as shown in the table below.
4. Apply power to the GVA-395.
5. Press the reset button SW1.
6. LED D41 will be lited for approximately 10 seconds while the Flash Memory is being erased.
7. Wait for the LED D41 to extinguish.
8. It is necessary to use the serial cable connection for the Programming Adapter in order to use a the slower
57 Kbps serial transfer rate.
9. From the Xilinx Foundation Project Manager, select the Programming icon.
10. Select the Hardware Debugger.
11. From the Hardware Debugger, select the desire exo file to be programmed into the EEPROM. Please note
that the FPGA will also be programmed as the data is being written into the EEPROM.
12. While the data is being written into the EEPROM, the LEDs D42 thru D44 will be toggling
13. When all of the LED D41 thru D44 are lite, the program function has been completed.
14. Remove power from the GVA-395 and remove the Slave Serial cable. Install that jumper blocks are install
on JP3 and JP9 with the jumper block on JP2 is removed. When power is reapplied, the GVA-395 will
configured from the EEPROM.

GV-395 Virtex-II DSP Hardware Accelerator Manual
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Slave Serial Signal JP5 Connection
VCC 1
GND 2
CCLK 4
DONE 5
DIN 6
PROG 7
INIT 8
4.4.1.1 EEPROM Slave Serial Programming Configuration Table
5.0 Flash EEPROM Configuration FPGA (U1)
Normally, this FPGA will be configured by the serial prom (U3) which is programmed at the factory to perform the
configurations operations described in Section 4. However, this FPGA maybe reprogrammed by installing a jumper
block on JP4. The FPGA may now be reprogrammed by connecting the JTAG download cable to JP7 as follows:
VCC ->1, GND->2, TDO -> 3, TDI -> 4, TCK ->5, TMS ->6. This is not recommended but it would have no
adverse effects on the GVA-395 as long as the configuration pins for the other FPGAs are not used. Please refer to
the schematic for additional information.
6.0 On-Board System Clock Configuration
The GVA-395 uses an 50 MHz oscillator to generate the on-board system clock. which has a SG-615 form factor such as those
found in the Digi-Key catalog. The System clock is on pin AF18 for Virtex-II FPGAs and on pin 15 of the Spartan-II FPGAs. To
select the on-board oscillator as the system clock connect a jumper block between pins1 and 2 of JP8
6.1 External Clock Configuration
An exterior clock source (P1) may be selected as the system clock by installing a jumper block between pins 2 and 3
of JP8. Insure that this clock source meet the TTL minimum value (Vih = 2.4V and Vil = 0.4V) and does not exceed
7V in reference to Ground before attaching the source to P1.
7.0 Xilinx FPGA Power-On Reset and Manual Reset Push Button Switch
The power-on reset may be used for initialization purposes. There is also a manual reset push button switch (SW1)
which will reactive the reset signal. It should be noted that if the +3.3V supply voltage drops below +3.00V the
power-on reset will trigger.
Signal
Name
ACX FPGA
(U10)
Pin No.
AC FPGA
(U12)
Pin No.
DP FPGA
(U14)
Pin No.
DPX FPGA
(U16)
Pin No.
E1 FPGA
(U18)
Pin No.
RESETL AG18 AG18 AG18 AG18 18
7.1.1 Power-on Reset Interconnect Table

GV-395 Virtex-II DSP Hardware Accelerator Manual
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8.0 ACX FPGA (U10)
8.1 ACX FPGA (U10) to Daughter I/O PCB Interface.
. The data is then transferred to the Xilinx ACX FPGA (U10). The data may then be processed by the FPGA.
Signal PC1 Pin No. ACX FPGA Pin Signal PC2 Pin No. ACX FPGA Pin
AD0_DN0 1 E1 AD1_DN0 1 M1
AD0_DP0 2 D1 AD1_DP0 2 L1
AD0_DN1 3 E2 AD1_DN1 3 M2
AD0_DP1 4 D2 AD1_DP1 4 L2
AD0_DN2 5 E3 AD1_DN2 5 M3
AD0_DP2 6 D3 AD1_DP2 6 L3
AD0_DN3 7 G1 AD1_DN3 7 L4
AD0_DP3 8 F1 AD1_DP3 8 K4
AD0_DN4 9 G2 AD1_DN4 9 P2
AD0_DP4 10 F2 AD1_DP4 10 N2
AD0_DN5 11 G3 AD1_DN5 11 N4
AD0_DP5 12 F3 AD1_DP5 12 M4
AD0_DN6 13 F4 AD1_DN6 13 P3
AD0_DP6 14 E4 AD1_DP6 14 N3
AD0_DN7 15 F5 AD1_DN7 15 P5
AD0_DP7 16 G5 AD1_DP7 16 N5
AD0_DN8 17 J1 AD1_DN8 17 N6
AD0_DP8 18 H2 AD1_DP8 18 P6
AD0_DN9 19 J3 AD1_DN9 19 T2
AD0_DP9 20 H3 AD1_DP9 20 R1
AD0_DN10 21 J4 AD1_DN10 21 T3
AD0_DP10 22 H4 AD1_DP10 22 R3
AD0_DN11 23 J5 AD1_DN11 23 R4
AD0_DP11 24 H5 AD1_DP11 24 P4
AD0_CLKN 25 U1 AD1_CLKN 25 U3
ADO_CLK 26 U2 AD1_CLK 26 V4
+3.3V 27 No. Connect +3.3V 27 No. Connect
+3.3V 28 No. Connect +3.3V 28 No. Connect
+5V 29 No. Connect +5V 29 No. Connect
+5V 30 No. Connect +5V 30 No. Connect
AD0_DN12 31 E19 (GCLKP) AD1_DN12 31 K18 (GCLKP)
AD0_DP12 32 E18 (GCLKS) AD1_DP12 32 J18 (GCLKS)
AD0_DN13 33 K2 AD1_DN13 33 L6
AD0_DP13 34 J2 AD1_DP13 34 M6
AD0_DN14 35 L5 AD1_DN14 35 N7
AD0_DP14 36 K5 AD1_DP14 36 M7
AD0_DN15 37 J6 AD1_DN15 37 N8
AD0_DP15 38 K6 AD1_DP15 38 P8
DGND 39 No. Connect DGND 39 No. Connect
DGND 40 No. Connect DGND 40 No. Connect
DGND 41 No. Connect DGND 41 No. Connect
DGND 42 No. Connect DGND 42 No. Connect
DGND 43 No. Connect DGND 43 No. Connect
8.1.1.1 ACX FPGA (U10) to PC1 and PC2 Interconnection Table