Hyundai ImageQuest L50A Operating manual

Multiscanning Color Monitor
TECHNICAL SERVICE MANUAL
L50A(L50C)
http://monitor.hei.co.kr
http://hyundaiQ.com

--1--
L50A(L50C) Technical Ser ice Manual
Safety Precaution
WARNING
Service should not be attempted by anyone unfamiliar with the necessary precautions on this
monitor.
The followings are the necessary precautions to be observed before servicing.
1. When managing this monitor , cover with shield plate to avoid to scrach on LCD surface.
. When replacing a chassis in the cabinet, always be certain that all the protective devices are
put back in place, such as nonmetallic control knobs, insulating covers, shields, isolation
resistor capacitor network etc.
3. Before returning the monitor to the customer, always perform an AC leakage current check
on the exposed metallic parts of the cabinet, such as signal connectors, terminals, screw
heads, metal overlays, control shafts etc, to be sure the monitor is safe to operate without
danger of electrical shock.
General Information
1. Description
This 15" LCD color display monitor is operated in R, G, B drive mode input.
2. Operating instructions
2-1. Front
Power Switch , Menu, Select, Down, Up, DPMS (Power) LED
2-2. Rear
Input connector (AC & Signal Cable)
2-3. OSD Controls
H/V Position, Clock Phase, Brightness, Contrast, Recall,Color Control, Language, Auto
Adjust, Miscellaneous
3. Electrical Characteristic
3-1. Power Supply
AC/DC - Input Voltage : 90V~ 64V
Input Current : 1.0 A Max
Input Ferquency : 50 ~ 60Hz
- Output Voltage 1 V/5V
Output Vurrent A/ A
3-2. Video Input Signal
Level : 0.7 Vp-p analog signal(at 75 ohm termination to ground)
Polarity : Positive
3-3. Horizontal Synchronization Signal
Level : TTL High : .4V min
Low : 0.4V max
Polarity : - or +
Frequency : 31kHz ~ 60kHz
3-4. Vertical Synchronization Signal
Level : TTL High : .4V min
Low : 0.4V max
Polarity : - or +
Frequency : 56Hz ~ 75Hz

--2--
Control Description
Front View
Support Modes
LED Indicator Soft Power Switch
H Frequency
(kHz)
31.5
31.5
37.9
37.9
46.9
48.4
56.5
60.0
V Frequency
(Hz)
70.0
59.9
7 .8
60.3
75.0
60.0
70.1
75.0
H
Polarity
0
0
0
1
1
0
0
1
V
Polarity
1
0
0
1
1
0
0
1
V
Polarity
8.3
5.175
31.500
40.000
49.500
65.000
75.000
78.750
NO
1
3
4
5
6
7
8
Resolution
7 0 x 400
640 x 480
640 x 480
800 x 600
800 x 600
10 4 x 768
10 4 x 768
10 4 x 768
Refresh rate
70.087
59.940
7 .809
60.317
75.000
60.004
70.069
75.0 9

Video Input Signal
Recommended signal are shown below
•Video Signal
Video level : 0 to 700mV
Polarity : positive
Video Input : RGB separated
Analog level
Sync input : H-Sync(TTL level)
V-Sync (TTL level)
•Wa eform
Video input(R.G.B)
--3--
L50A(L50C) Technical Ser ice Manual
ACTIVE (T4)

Front Porch
(T5) Period (T1)
Sync Width (T2)
Back Porch (T3)
ACTIVE (T4)

Front Porch
(T5) Period (T1)
Sync Width (T2)
Back Porch (T3)
• H-Sync • V-Sync
0
1
3
4
51
5
53
54
55 700mV
0mV
• Signal: 56 level gray
scale
• Linear stepping:
( .73mV ~ 56 Steps)

--4--
Video Input Terminal
A 15 Pin D-sub connector is used as the input signal connector
Pin and input signals are shown in the table below.
Pin Description
D-Sub miniature connector
SIGNAL
PIN NO.
3
1
5
4
6
7
8
9
10
11
1
13
14
SEPARATE SYNC/
DDC 1/ B
RED
GREEN
BLUE
GND
RETURN
RED GROUND
GREEN GROUND
BLUE GROUND
N.C
LOGIC GROUND
GROUND
SDA
H-SYNC(TTL)
V-SYNC(VCLK)
15 SCL

Connecting with External Equipment
Cautions
Be sure to turn off the power of your computer before connecting the monitor.
--5--
L50A(L50C) Technical Ser ice Manual

Theory of Operation
1. AC/DC Adapter
Input voltage : 90 ~ 64 Vac, 50/60 Hz
Input current : Max 1A (Vin : 90Vac , 50Hz)
Inrush current : 15A peak (At 115Vac Max . Load)
30A peak (At 30Vac Max. Load)
2. DC/AC INVERTER
Input voltage : DC 1 V
Input current : .0A(Max)
Frequency(switching) : 40 - 80 KHz
On/off control voltage : 5.0V
3. DPMS MODE
Reference to DPMS files
--6--
Mode
Normal
Suspend
off
LED
10W
5W
LED
Indicator
40W
Green
Orange
Orange
Unplugged 0W
Not illuminated

--7--
L50A(L50C) Technical Ser ice Manual
On Screen Controls & LED Indicator
The menu for screen setting adjustment is located in the OSD and can be viewed in one of
five languages OSD feature andmain funcrions are as follows:
The OSD adjustments available to you are listed below.
BRIGHTNESS
Adjust the brightness of the screen.
CONTRAST
Adjust the contrast of the screen.
COLOR CONTROL
Color temperature affects the tint of the image. With lower color
temperatures the image turns reddish and with higher temperatures
bluish.
There are three color settings available: Mode 1(a warm white), Mode 2(a cool white)
or USER. With the USER setting you can set individual values for red, green and blue.
H/V POSITION
H-POSITION
Adjusts the horizontal position of the entire screen image.
V-POSITION
Adjusts the vertical position of the entire screen image.

--8--
CLOCK PHASE
PHASE
Adjust the noise of the screen image.
CLOCK
Adjust the horizontal size of the entire screen image.
AUTO ADJUST
You can adjust the shape of screen automatically at the full screen pattern.
MISCELLANEOUS
RECALL
Recall the saved color data.
OSD TIMER
You can set the displayed time of OSD Menu window on the screen by using this
adjustment.
OSD POSITION
Adjust the OSD menu's horizontal or vertical position on the screen.
LANGUAGE
You can select the language in which adjustment menus are displayed.
The following languages are available : English, French, German, Italian,
Spanish, Swedish, Finnish, Danish, P

--9--
L50A(L50C) Technical Ser ice Manual
Getting Fine Picture
Step 1. At first Display, a full screen, such as, Window's background or "H" character should
be achieved by using Editor (ex: Notepad. exe)
Step 2. Adjust the screen to the center of the Display(LCD), by using the top and bottom
display controls. (i.e.Using V-Position Adjust menu)
Step 3. Adjust the screen to the center of the Display(LCD), by using the right and left
display controls. (i.e.Using Clock and H-Position adjust menu)
Step 4. Adjust the Clock-phase until the "H" Character displays clear.
Step 5. Using the Contrast. Brightness, and Color Control menu, set the color to your
preference.
Step 6. When you finish the adjustment, you can save your settings by pressing on the menu
until the OSD screen has disappeared.
Factory Setting & EEPROM Initialization Method
Factory Setting Method
- Connect the signal cable and power cable to the LCD monitor.
- Press Power switch with pressed MENU key.(Menu key + Power key).
- Then, a User can change the factory setting value in OSD menu.
- Save changed value and Turn off the power s/w.
- Turn on the power, adjust the screen.

--10--
Specification
LCD Module
SIZE 15” Viewable diagonal
Dot Pitch 0. 97mm
Brightness
Response Time
180 cd/m (MIN), 50 cd/m (TYP)
0m- sec (Typ)
Input Signal R.G.B Analog
Connector 15 pin D-SUB Connector
SYNC
H-Freq 31.0kHz ~ 60.0kHz
V-Freq 56.0Hz ~ 75Hz
Display
Area
Color
304(H)X 8(V)mm
16. M Colors
Resolution
Video Bandwidth
User Control
&
OSD Control
Contrast,Brightness,H-V Position,
Clock Phase, Color Control, Language,
Auto Adjust, Miscellaneous
Power Management VESA DPMS Standard
Plug & Play VESA DDC 1/ B
Safety &
Regulation
EMC
Ergonomi
Safety
FCC CLASS B , CE , VCCI
TCO
cULus, CE, TUV-GS, SEMKO
Temperature
30 to 80%(Non-condensing)
5 to 90%(Non-condensing)
packed
Humidity
Operating
Operating
Storage
Storage
5 to 35 °C
- 5 to 45 °C
Weight
unpacked
Dimension(WXHXD mm)
* Specification is subject to change without notice for performance improvement.
4.4Kg
367X353X188.3mm
3.1Kg
10 4 X 768 @ 75Hz
80MHz

--11--
L50A(L50C) Technical Ser ice Manual
Critical Parts Specification
1. LCD Module
HT-15X13(LTM150XH-L01 is a a-si TFT active matrix color liquid crystal comprising
amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight.
HT-15X13(LTM150XH-L01 has a built-in backlight display area contains 10 4X768 pixels
and can display full color (16. M colors)
Display area 304(H)X 8(V)mm
Drive system a-si TFT
Display color 16. M Colors
Number of Pixel 10 4X768
Pixel arrangement RGB vertical strip
Pixel pitch 0. 97(H)X0. 97(V)mm
Weight 300:1
Viewing angle
Horizontal: 80 degree(3’ clock, 9’ clock)/45(1 ’ clock) 80 (6’ clock)
Vertical: 40 degree(1 ’ clock) ,55 degree(6’ clock)/65(3 ’ clock, 9 ’ clock)
Response time 0ms(Typr)
Luminance 50cd/m (Typ)
Signal system Digital RGB signals, Sync signals(H, V-Sync),
Dot clock(DCLK) , DE(Data Enable)
Supply voltage 3.3V
Backlight Edge light type: Four colt cathode fluorescent lamps
With in- verter
Power consumption 1.5W(TYP) without B/L

) INTERFACE CONNEXTION
-1) Electrical Interface
CN1 Interface connector : DF14H- 0P-1. 5H(HIROSE) or equivalent
User side connector : DF14- 0S-1. 5C(HIROSE)or equivalent
--12--
Pin No
1
3
4
5
6
7
8
9
10
11
1
13
14
15
16
17
18
19
0
Symbol
VDD1
VDD
VSS
VSS
RIN0-
RIN0+
VSS
RIN0-
RIN0+
VSS
RIN -
RIN +
VSS
RCLKIN-
RCLKIN+
VSS
RIN3-
RIN3+
VSS
NC
Remark
Tx pin #48
Tx pin #47
Tx pin #46
Tx pin #45
Tx pin #4
Tx pin #41
Tx pin #40
Tx pin #39
Tx pin #38
Tx pin #37
Pin No
Power Supply : +3.3V
Power Supply : +3.3V
Ground
Ground
LVDS Negative data signal (-)
LVDS Negative data signal (+)
Ground
LVDS Negative data signal (-)
LVDS Negative data signal (+)
Ground
LVDS Negative data signal (-)
LVDS Negative data signal (+)
Ground
LVDS Negative data signal (-)
LVDS Negative data signal (+)
Ground
LVDS Negative data signal (-)
LVDS Negative data signal (+)
Ground
Reserved

--13--
L50A(L50C) Technical Ser ice Manual
- ) LVDS Infcrface
LVDS Transmitter : THC63LVDM83A or equivalent.
Input
signal
R0
R1
R
R3
R4
R5
G0
G1
G
G3
G4
G5
B0
B1
B
B3
B4
B5
HSYNC
VSYNC
DE
MCLK
R6
R7
G6
G7
B6
B7
RSVD
Pin No
51
5
54
55
56
3
4
6
7
11
1
14
15
19
0
3
4
7
8
30
31
50
8
10
16
18
5
Pin No
48
47
46
45
4
41
40
39
38
37
System (Tx)
OUT 0-
OUT +
OUT1+
OUT1+
OUT -
OUT +
CLKOUT-
CLKOUT+
OUT+
OUT-
TFT-LCD (Rx)
IN0-
IN0+
IN1-
IN1+
IN -
IN +
CLKIN-
CLKIN+
IN3-
IN3+
DF14H- 0P-1. 5H
Pin No
5
6
8
9
11
1
14
15
17
18
Remark
Transmitter Interface

--14--
.
F
Fe ea at tu ur re es s
The gmZAN1 device utilizes Genesisí patented third-
generation Advanced Image Magnification technology as
well as a proven integrated ADC/PLL to provide excellent
image quality within a cost-effective SVGA / XGA LCD
monitor solution.
As a pin-compatible replacement for the gmB120, the
gmZAN1 incorporates all of the gmB120 features plus
many enhanced features; including 10-bit gamma
correction, Adaptive Contrast Enhancement (ACE)
filtering, and an enhanced OSD.
Features
•
••
•Fully integrated 135MHz 8-bit triple-ADC, PLL,
and pre-amplifier
•
••
•gmZ2 scaling algorithm featuring new Adaptive
Contrast Enhancement (ACE)
•
••
•On-chip programmable OSD engine
•
••
•Integrated PLLs
•
••
•10-bit programmable gamma correction
•
••
•Host interface with 1 or 4 data bits
•
••
•Pin-compatible with gmB120
•
••
•Integrated Analog Front End
•
••
•Integrated 8-bit triple ADC
•
••
•Up to 135MHz sampling rates
•
••
•No additional components needed
•
••
•All color depths up to 24-bits/pixel are
supported
•
••
•High-Quality Advanced Scaling
•
••
•Fully programmable zoom
•
••
•Independent horizontal / vertical zoom
•
••
•Enhanced and adaptive scaling algorithm for
optimal image quality
•
••
•Recovery Mode / Native Mode
•
••
•Input Format
•
••
•Analog RGB up to XGA 85Hz
•
••
•Output Format
•
••
•Support for 8 or 6-bit panels (with high quality
dithering)
•
••
•One or two pixel output format
•
••
•Built In High-Speed Clock Generator
•
••
•Fully programmable timing parameters
•
••
•On-chip PLLs generate clocks for the on-chip
ADC and pixel clock from a single reference
oscillator
•
••
•Auto-Configuration / Auto-Detection
•
••
•Phase and image positioning
•
••
•Input format detection
•
••
•Operating Modes
•
••
•Bypass mode with no filtering
•
••
•Multiple zoom modes:
with filtering
with adaptive (ACE) filtering
•
••
•Integrated On-Screen Display
•
••
•On-chip character RAM and ROM for better
customization
•
••
•External OSD supported for greater flexibility
•
••
•Many other font capabilities including: blinking,
overlay and transparency
Package
•160-pin PQFP
Applications
•Multi-synchronous LCD monitors
•Other fixed-resolution pixelated display devices
gmZAN1

--15--
L50A(L50C) Technical Ser ice Manual
Figure 1. gmZAN1 Pin Diagram
CVSS1
Reserved
PSCAN
Reserved Reserved
PD47 PD46
RVSS1
PD45 PD44
SRVDD1
RVDD1
PD43 PD42 PD41 PD40 PD39
SRVSS1
PD38 PD37
SRVDD2
PD36 PD35 PD34 PD33 PD32 PD31 PD30 PD29
RVSS2
PD28 PD27
RVDD2
PD26 PD25 PD24 PD23 PD22 PD21
CVDD1
OSD_DATA2 OSD_DATA1 OSD_DATA0 OSD_CLK OSD_VREF OSD_HREF CVSS4 MFB0 MFB1 MFB2 MFB3 MFB4 CVDD4 MFB5 MFB6 MFB7 MFB8 HCLK MFB9 IRQ RESETn HDATA HFS N/C ADC_RVDDA RED+ RED- ADC_RGNDA ADC_GVDDA GREEN+ GREEN- ADC_GGNDA ADC_BVDDA BLUE+ BLUE- ADC_BGNDA ADC_VDDA Reserved ADC_GNDA SUB_GNDA
OSD_DATA3
OSD_FSW
MFB11
MFB10
DVDD
DVSS
DAC_DGNDA
DAC_DVDDA
PLL_DVDDA
Reserved
PLL_DGNDA
SUB_DGNDA
SUB_SGNDA
PLL_SGNDA
Reserved
PLL_SVDDA
DAC_SVDDA
DAC_SGNDA
SVDD
SVSS
TCLK
XTAL (Reserved)
PLL_RVDDA
PLL_RGNDA
Reserved
SUB_RGNDA
Reserved
VSYNC
SYN_VDD
HSYNC/CS
SYN_VSS
Reserved
STI_TM1
STI_TM2
SCAN_IN1
Reserved
SCAN_IN2
SRVSS2
SCAN_OUT1
SCAN_OUT2
ADC_GND1
ADC_VDD1
ADC_GND2
ADC_VDD2
PPWR
PBIAS
PHS
PVS
CVSS3
PD0
PD1
PD2
PD3
PD4
PD5
RVDD3
PD6
PD7
PD8
RVSS4
Reserved
Reserved
CVDD2
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
RVSS3
PD17
PD18
PD19
PCLKB
PCLKA
PDISPE
PD20
CVSS2
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
gmZAN1 (160-Pin PQFP)
NOTE: For all power pads:
C: Core
R: Ring
S: From pad 125 to 132, S represents Sclk DDS (source clk)
D: From pad 133 to 140, D represents Dclk DDS (destination clk)
NOTE: SRVSS1, SRVSS2 are connected to core VSS and SRVDD1 and
SRVDD2 are connected to core VDD.
NOTE: The following signals have the same function but different names in
the gmB120 datasheet:
OSD-HREF is here called OSD_HREF
OSD-VREF is here called OSD_VREF
OSD-CLK is here called OSD_CLK
OSD-DATA0 is here called OSD_DATA0
OSD-DATA1 is here called OSD_DATA1
OSD-DATA2 is here called OSD_DATA2
OSD-DATA3 is here called OSD_DATA3
SYVDD is here called SYN_VDD
SYVSS is here called SYN_VSS
NOTE: when connected to a pull-down resistor, the MFB5 strapping option
(sampled at reset) enables the use of an external crystal. MFB5 has an
internal pull-up resistor, so an external oscillator is the default.
NOTE: MFB6 is a strapping option to select a host data bus width of four
when connected to a pull-down (sampled at reset). Since MFB6 has an
internal pull-up resistor, a 1-wire host bus width is the default.
Pin Out Diagram

--16--
FEATURES
8051 core, 12MHz operating frequency with double CPU clock option
0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating
1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)
Maximum 14 channels of PWM DAC
Maximum 31 I/O pins
SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment
Built-in low power reset circuit
Built-in self-test pattern generator with four free-running timings
Compliant with VESA DDC1/2B/2Bi/2B+ standard
Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data
Single master IIC interface for internal device communication
Maximum 4-channel 6-bit ADC
Watchdog timer with programmable interval
Flash-ROM program code protection selection
40-pin DIP, 42-pin SDIP or 44-pin PLCC package
GENERAL DESCRIPTIONS
The MTV312M micro-controller is an 8051 CPU core embedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC
interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
XFR
P0.0-7
P2.0-3
RD
WR
ALE
INT1
P0.0-7
P2.0-3
RD
WR
ALE
INT1
8051
CORE
P1.0-7
P3.0-2
P3.4-5
RST
X1
X2 ADC
A
D0-3
PWM DAC
DA0-13
DDC&IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
AUXRAM&
DDCRAM
HSYNC
VSYNC
HBLANK
VBLANK
H/VSYNC
CONTROL
P6.0-7
P5.0-6 AUX
I/O
P4.0-2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MTV31 M64

--17--
L50A(L50C) Technical Ser ice Manual
PIN CONNECTION
MTV312M
40 Pin
PDIP
DA2/P5.2 401 39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DA1/P5.1
DA0/P5.0
VDD3
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
HSYNC
DA3/P5.3
VSYNC
DA4/P5.4
DA8/HLFHO
DA9/HALFV
DA5/P5.5
HBLANK/P4.1
DA7/HCLAMP
DA6/P5.6
VBLANK/P4.0
RST
P6.5/DA11
P6.4/DA10
P6.6/DA12
HSCL/P3.0/Rxd
P6.0/AD0
P6.1/AD1
HSDA/P3.1/Txd
P1.7
MTV312M
44 Pin
PLCC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
P1.6
24 P1.7
P6.1/AD1 P1.5 P6.0/AD0 HSDA/P3.1/Txd P1.1 P3.2/INT0 P1.2 P1.3 P1.4
23 22 21 20 28 27 26 25
NC 6
5 4 3 2 1 44 43 42 41 40
NC
VDD3
DA0/P5.0 DA1/P5.1 DA2/P5.2
VSYNC
HSYNC
DA3/P5.3 DA4/P5.4 DA5/P5.5
19 18
RST
VDD
VSS
X2
X1
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P6.3/AD3
P6.4/DA10
HSCL/P3.0/Rxd
P6.5/DA11
P6.6/DA12
DA8/HLFHO
DA9/HALFV
HBLANK/P4.1
DA7/HCLAMP
DA6/P5.6
VBLANK/P4.0
P6.7/DA13
MTV312M
42 Pin
SDIP
DA2/P5.2
40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2221
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DA1/P5.1
DA0/P5.0
RST
VDD
VSS
VDD3
NC
NC
HSYNC
DA3/P5.3
VSYNC
DA4/P5.4
DA8/HLFHO
DA9/HALFV
DA5/P5.5
HBLANK/P4.1
DA7/HCLAMP
DA6/P5.6
VBLANK/P4.0
42
41
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P6.2/AD2/HLFHI
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
X2
X1 P6.6/DA12
P6.5/DA11
HSCL/P3.0/Rxd
HSDA/P3.1/Txd
P6.4/DA10
P6.0/AD0
P1.7
P1.6
P6.1/AD1
P1.5

--18--
PIN CONFIGURATION
A ìCMOS output pinî means it can sink and drive at least 4mA current. It is not recommended to use such
pin as input function.
A ìopen drain pinî means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as
input or output function and needs an external pull up resistor.
A ì8051 standard pinî is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA
to maintain the pin at high level. It can be used as input or output function. It needs an external pull up
resistor when driving heavy load device.
POWER CONFIGURATION
The MTV312M can work on 5V or 3.3V power supply system.
In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all
output pins can swing from 0~5V, input pins can accept 0~5V input range. And ADC conversion range is 5V.
However, X1 and X2 pins must be kept below 3.3V.
In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V,
HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins must be kept below 3.3V. And
the ADC conversion range is 3.3V.
8051Standard Pin
4mA
4mA
Output
Data Pin
CMOS Output Pin Open Drain Pin
2 OSC
period
delay
4mA 10uA
Output
Data
120uA
Pin
4mA
Input
Data
No Current
4mA
Output
Data
Pin
Input
Data
VDD
VDD3
5V
10u MTV312M in
5V System
3.3V
VDD
VDD3
MTV312M in
3.3V System

--19--
L50A(L50C) Technical Ser ice Manual
BLOCK DIAGRAM
GENERAL DESCRIPTION FEATURES
The CS5828 receives four sets of 7-bit data in
CMOS logic level and converts them into four low-
voltage differential signaling (LVDS) serial channels.
The 7-bit input data is referenced to the CKIN signal.
The RF pin selects either rising or falling edge trigger
of CKIN. Parallel to serial conversion is performed by
a 7X internal generated clock reference using on-
chip PLL using CKIN. A copy of CKIN but phase-
locked to the output serial streams, CLKOUT, is also
converted to the fifth LVDS channel. The CS5828
offers a reliable communication media using LVDS
signaling and provides low EMI dealing with wide,
high-speed TTL interfaces.
This is especially attractive for interfaces between
GUI controller and display systems such as LCD
panels for SVGA/XGA/SXGA applications.
Four 7-bit serial and one clock LVDS channels.
Compatible with ANSI TIA/EIA-644 LVDS stan-
dard.
Wide CKIN ranges from 31MHz to 85MHz.
Fully integrated on-chip PLL that provides 7X
CKIN serial shift clock.
Pin selectable for rising or falling edge trigger.
Support power-down mode.
5V/3.3V tolerant data input.
Single 3.3V supply operation.
CMOS low power consumption.
Functional compatible with DS90C385.
Available in 56-pin TSSOP package.
PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
SHIFT/LOAD_N
DIN
CLK
PHASE LOCK LOOP
R/F
CLK
7xCLK
SHIFT/LOAD_N
CONTROL LOGIC
D19,D20,D21,D22,
D27,D5,D10,D11,
RF
CKIN
SHTDN
EN
CKOP
CKON
CS5828
DIN
CLK
DIN
CLK
SHIFT/LOAD_N
SHIFT/LOAD_N
EN
Y3P
Y3N
EN
Y2P
Y2N
EN
Y1P
Y1N
EN
Y0P
Y0N
PARALLEL-IN SERIAL-OUT
7-Bit SHIFT REGISTER
DIN
CLK
SHIFT/LOAD_N
D0,D1,D2,D3,
D4,D6,D7
D8,D9,D12,D13,
D14,D15,D18
D24,D25,D26
D16,D17,D23
•
•
•
•
•
•
•
•
•
•
•
CS58 8