ICS ICS-130 User manual

DOC E10523 Rev.D
ICS-130
OPERATING MANUAL
Interactive Circuits And Systems Ltd.
November 2000
The information in this manual has been carefully checked and is believed to be reliable; however, no
responsibility is assumed for possible inaccuracies or omissions. Interactive Circuits and Systems Ltd.
reserves the right to make changes to products herein described to improve reliability, function, or design. No
patent rights are granted to any of the circuits described herein.
Extra copies of this manual are available from the factory.
ICS Ltd
5430 Canotek Road
Gloucester, Ontario
K1J 9G2 Canada
http://www.ics-ltd.com
[e-mail]
Tel: [phone]
USA: [phone]
Fax: [phone]

DOC E10523 Rev.D

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TABLE OF CONTENTS
1. INTRODUCTION 1
1.1 References 1
2. GENERAL DESCRIPTION 2
2.1 Board Specifications 4
3. DETAILED DESCRIPTION 5
3.1 ADC Section 5
3.2 Input Bandwidth and Sample Rate 6
3.3 Clock/Trigger Options 7
3.4 Data Path Selection 7
3.5 Modes of Operation 7
3.6 VMEbus Interface 8
3.7 Cascading Multiple Boards 9
3.8 FPDP Interface 10
3.9 Light-Emitting Diodes 10
4. HARDWARE PREPARATION 12
4.1 System Configuration 12
4.2 Jumper and Switch Settings 14
4.2.1 VMEbus Base Address Selection 14
4.2.2 P4 Local Bus Interface 16
5. PROGRAMMING MODEL 17
5.1 General Notes 17
5.2 SCV64 Registers 19
5.3 Performing Block Transfers 25
5.3.1 VMEbus DMA Master 25
5.3.2 VMEbus DMA Slave 26
5.4 ADC Data 26
5.5 Status Register (SR) 27
5.5.1 SR<0> -VMEbus Master IRQ 27
5.5.2 SR<1> -ADC IRQ 27
5.5.3 SR<2> -P2 IRQ 28
5.5.4 SR<3> -IRQ 28
5.5.5 SR<4> -Diag FIFO empty 28
5.6 Interrupt Mask Register (IMR) 29
5.6.1 IMR<0> -VMEbus IRQ Mask 29
5.6.2 IMR<1> -ADC IRQ Mask 29
5.6.3 IMR<2> -P2 Module IRQ Mask 29
5.7 Control Register (CR) 30
5.7.1 CR<0> -Trigger Select 30
5.7.2 CR<1> -Sampling Clock Select 30

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5.7.3 CR<2> -Diagnostic Mode Enable 31
5.7.4 CR<3> -P2 Enable 31
5.7.5 CR<4> -FPDP Enable 31
5.7.6 CR<5> -FPDP Word Width 32
5.7.7 CR<6> ADC Sampling Master Enable 32
5.7.8 CR<7> -ADC Clock Termination 33
5.7.9 CR<8> -FPDP Master Enable 33
5.7.10CR<9> -FPDP Termination 34
5.7.11 CR<11:10> -ADC Mode 34
5.7.12 CR<12> -Acquisition Mode 34
5.7.13 CR<13> -Trigger 35
5.7.14 CR<14> -Enable 35
5.8 Channel Count Register 35
5.9 Buffer Length Register 36
5.10 Acquisition Count Register 36
5.11 Decimation Count Register 37
5.12 Frame Count Register 37
5.13 ADC Clock Frequency Register 37
5.14 FPDP Clock Frequency Register 38
5.15 Arm Register 38
5.16 ADC Reset Register 38
5.17 Board Reset Register 39
5.18 Master Control Register (MCR) 39
5.18.1 MCR<09:00> -Frame Length 39
5.18.2 MCR<14:10> -FPDP board address 39
5.19 Using Diagnostic Mode 40
6. APPENDICES 42
6.1 Typical Order of Operations for Simple Acquisition 42
6.2 Programming the Internal Clock Generator and FPDP Clock 43
6.2.1 Introduction 43
6.2.2 Programming Summary 43
6.2.3 Control Register44
6.2.4 Programming Register 44
6.2.5 VCO Programming Constraints 46
6.2.6 Program Register Example 46
6.2.7 Oscillator Programming Example 47
6.3 Analog 1-16 Connector Details 49
6.4 Analog 17-32 Connector Details 49
6.5 P4 Local Bus Connector Details 51
6.6 P3 FPDP Details 53
6.6.1 FPDP Connector Pin Assigments 53
6.6.2 FPDP Signals 56

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1. INTRODUCTION
The ICS-130 is a 32-channel, 16-bit, VMEbus data acquisition card with an output rate of
1.2 MSample/sec. The board offers multiple options for generating and moving data at high
speed. This design has been optimized for applications which demand high speed,
precision and ease of integration.
ICS offers software drivers for the ICS-130 for a number of platforms (including VxWorks
and Solaris). Use of one of these drivers is strongly recommended, since they greatly
simplify control and operation of the ICS-130. This will generally save the programmer
much time since he/she is relieved of the requirement to understand the complexities of the
ICS-130 hardware model and of the Tundra Semiconductor SCV64 VMEbus interface
device. Contact ICS for further details about available drivers.
1.1 References
1. OpenBus Interface Components, SCV64 User Manual, Document No.
891078.MD301.01, Newbridge Microsystems, 1993.
2. VxWorks Device Driver Manual for the ICS-130, Document No. E10524, Interactive
Circuits and Systems Ltd., March 1998.

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2. GENERAL DESCRIPTION
Figure 1 shows a simplified block diagram of the ICS-130 board. The board uses 32 16-bit
Sigma-Delta ADCs (Analog Devices AD7723) to provide simultaneous sampling at rates of
up to 1.2 Msamples/sec. on each channel. The oversampling ratio of the Sigma-Delta ADC
can be selected as 16 or 32.
To allow fast transfer of ADC data, the ICS-130 board includes a VME64 interface capable
of in excess of 70 MByte/s (i.e. D64 bus cycles), an optional P2 interface (VSB, RaceWay,
Skychannel, etc.), and a 32-bit front panel interface. The transfer rate of the FPDP interface
is fully programmable from 1 to 50 MHz. The VME64 interface circuitry uses the Tundra
Semiconductor (formerly Newbridge) SCV64 chip to support a Multiplexed Block Transfer
(MBLT) master/slave interface. The A32/D32, and A24/D32 protocols are also supported.
ADC data is buffered either in the 4 KSample FIFO (First-In First-Out memory) when data is
read-out via the FPDP or the P2 interface, or the dual-ported memories when data is read
out via the VMEbus. The sampling clock and the trigger can be either internal or external.
The internal ADC clock is user programmable in steps of less than 250Hz at the output
rate.
The ADCs can be operated either in continuous or capture modes. In the continuous mode,
data is continuously supplied to the selected interface upon application of a trigger signal
until the acquisition is disabled. In capture mode, a fixed number of samples are acquired
upon each application of the trigger. There are two ways in which this may be done. When
using pre-trigger storage, the ICS-130 stores samples continuously before the trigger and
acquires a programmable number of samples following the trigger (to a maximum of 32,768
samples/channel if all 32 channels are active). When pre-trigger storage is not used,
conversion starts at each application of the trigger and a programmable number of samples
(again, to a maximum of 32,768) are acquired.
In capture mode without pre-trigger storage, the acquisition count and buffer length may be
programmed separately. Thus it is possible to perform multiple capture sequences at each
occurrence of the trigger, until the buffer is filled to the programmed length.
The ICS-130 board can generate VMEbus interrupts at any user programmed interval
(number of samples acquired).
All power requirements of the ICS-130 are satisfied with standard VMEbus voltages.

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32
32
32
32
32 SERIAL
ADC
32
CHANNELS
ADC
ADC
TO
PARALLEL
1MSAMPLE
1MSAMPLE
BUFFER
BUFFER
VME
INTERFACE
MULTI-BOARD
SYNCHRONIZATION
EXTERNAL
CLOCK
EXTERNAL
TRIGGER CONTROL
4KWORDS
FIFO
P2
MODULE
FIFO
FIFO
FPDP
INTERFACE
K10385-1
INTERNAL
CLOCK
32
32
Figure 1-ICS-130 Simplified Block Diagram

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2.1 Board Specifications
Analog Input
No. of Analog Input Channels: 4, 8, 16 or 32 differential
Input Impedance: 10 kOhm (each wire)
Full Scale Input: 2 Vpp diff. or 4 Vpp single-ended
Max. Input Sample Rate (Fs): 19.2 MHz
Oversampling Ratio: 16 or 32
Max. Input Signal Bandwidth: 0.383 x Fo (Flat passband)
0.478 x Fo (-3dB)
where Fo = Channel Output Rate
Fo = Fs/16 or Fs/32
Maximum Channel Output Rate: 1.2 MHz/ch. for 32 channels (16x oversampling)
Minimum Channel Output Rate: 31.25 kHz/ch. for 32 channels
Maximum Decimation: 256
Settling Time: 1293/Fs (32x oversampling)
541/Fs (16x oversampling)
Signal/(Noise+Distortion+Crosstalk): >87dB (Fs/32)
>81dB (Fs/16)
Inter-channel Cross-talk: <-80dB
On-board Storage: 2 MSample
(64 KSample/channel, all 32 chan’s active)
General
VMEbus Interface: A64/A32/A24 D64/D32 MBLT Master/Slave
Front-Panel Interface: FPDP 32-bit, 160MByte/s
Environmental: Temp: 0° to +50°C operating (at entry point of forced air,
approximately 490 LFM)
-40°to +85°C Storage
Humidity <95% non-condensing
Power: 2.2 Amps @ +5 V
0.3 Amp @ +12 V
(No daughter card modules installed)
Board Size: VME 6U (233x160mm) Single Slot Width

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3. DETAILED DESCRIPTION
3.1 ADC Section
The ICS-130 board uses 32 16-bit Sigma-Delta ADCs (Analog Devices's AD7723). The
maximum input clock for the Sigma-Delta ADC is 19.2 MHz. Thus, the maximum output rate
(16x oversampling ratio mode) is 1.2 MSamples/sec. When the internal programmable
frequency clock is used, the minimum sampling rate for the ADCs is 1.0 MHz. However, the
ADC data stream may be decimated by up to 256, making the board's effective minimum
output rate 122 Hz. Decimation is accomplished by storing one out of every N samples
where N is programmable from 1 to 256. The full scale input signal level is 2 Vpp differential
(i.e. 2 Vpp on each wire of the differential pair), with an input impedance of 10kΩto ground
on each input wire. Figure 2 shows the input buffer stage for one channel. Two 44-pin
connectors (marked P6 and P7) are provided on the front panel for applying the differential
analog input signals. The inputs may also be driven using a single-ended signal; in this
case, the full-scale input on the driven wire is 4 Vpp. The unused wire should be connected
to ground. If a long cable is used to drive the input, the best arrangement is to use a
shielded twisted pair to drive each channel input, with the undriven wire grounded at the
transmit end of the cable. This scheme takes advantage of the differential input of the
ICS-130 to remove common-mode noise picked up by the cable.
Figure 2-ICS-130 Analog Input (One Channel Only Shown)

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3.2 Input Bandwidth and Sample Rate
The AD7723 Sigma-Delta ADC chip employs a number of digital filters in series in
order to achieve a high decimation factor. The composite response of these filters
governs the input signal bandwidth. The digital filter response can be either lowpass or
bandpass as shown in Figure 3.
For the lowpass filter case, as shown in
Figure 3(a), the output rate, Fo, can be
either Fs/16 or Fs/32. Note that for the
lowpass case (which is the case for most
applications) and for a flat pass band, the
sample rate can be selected as:
Fs = 32 x BW/0.383 for BW <230 kHz
or Fs = 16 x BW/0.383 for BW <460 kHz
For the bandpass case, as shown in
Figure 3(b), the output rate must be Fs/32.
The band shown in the figure (0.308Fo to
0.383Fo) is shifted down to DC.
The choice of filter type and decimation
(oversampling) ratio may be selected using
the ADC Mode field of the ICS-130 Control
register (see section 5.7.11). Further details
on the converter characteristics are available from the manufacturer, Analog Devices, at the
following web site address:
http://products.analog.com/products/info.asp?product=AD7723
The outputs of the ADCs are combined to produce up to sixteen 32-bit words, depending
on the number of channels selected to be active, in the Channel Count register (see section
5.8). The selected data are transmitted either to the FPDP/P2 FIFO and/or to the VME
swing buffer. The output data format is:
D31 D0
Channel 1 Channel 2 Word 1
Channel 3 Channel 4 Word 2
• • • • • • •
Channel N-1Channel N •
Channel 1 Channel 2 •
• • • • • • •
FLAT RESPONSE (0.383 x Fo)
-3dB POINT (0.478 x Fo)
Fo/2 Fo = Output Rate
= Fs/16 or Fs/32
0.308 x Fo
Fo/2 Fo = Fs/16
0.383 x Fo
(a)
(b)
K10387-1
Fo/4
Figure 3 -Lowpass and Bandpass
response options

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3.3 Clock/Trigger Options
The ICS-130 offers a number of clock and trigger options. The card has an internal
sampling clock provided by a programmable oscillator giving a resolution of less than
250Hz at the output rate over the entire 1.0 MHz to 19.2 MHz range. Alternatively, an
external sampling clock applied at pin 25 of the P4 front panel connector may be used. In
this case, the clock must be at the oversampling rate (either 16x or 32x the required output
rate).
The trigger can be programmed to be internal (i.e. software controlled) or external. If using
the external trigger, the user should supply a positive-going TTL pulse on pin 23 of the P4
connector; the pulse must be at least one sample period long. The trigger is internally
synchronized to the sampling clock by the ICS-130. Acquisition starts with the first valid
data word after the application of the trigger.
Both external clock and trigger signals must conform to standard TTL levels and drive
capability. The relevant connections are listed in section 6.3.
3.4 Data Path Selection
The ICS-130 provides three basic options for reading acquired data. The destination for the
ADC data can be VMEbus, FPDP, or P2. One or more of these interfaces may be enabled
at a time.
3.5 Modes of Operation
Three modes of operation are provided in the ICS-130 design:
-capture mode without pre storage,
-capture mode with pre storage,
-and continuous mode, which has no pre storage option.
In the capture mode without pre storage, data is acquired for a programmable number of
samples following the application of each trigger. The maximum number of samples that
can be stored for all active channels is 1048576. Because the size of the memory buffer,
and the count of samples acquired are both programmable, multiple capture acquisitions
may be stored in the ICS-130 memory.
Important note: When using capture mode without pre-trigger storage, the memory
buffer length programmed must always be an integral number of acquisition counts.

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In the capture mode with pre storage, the ICS-130 memory is used as a circular buffer of
programmable length. The ICS-130 is “armed” by the user, and the control logic
continuously fills the circular buffer with fresh data samples in anticipation of the trigger
signal. When the trigger signal is recieved, the final “acquisition count” number of samples
are stored in memory, and acquisition is automatically terminated.
To select pre-trigger storage of data in Capture mode, the Arm register must be written to
as the last action of configuring the board. This will cause the board to start acquiring data.
If the Arm register is not written, pre-trigger storage will not occur.
The basic idea: When using pre-trigger storage, acquisition count and memory
buffer size may be independantly set. Data stored in the memory buffer will be
divided into two sections: data acquired before the application of the trigger, and
data acquired after the application of the trigger.
In the Continous mode of operation, acquisition begins upon application of the trigger and
continues until the board is disabled.
3.6 VMEbus Interface
The ICS-130 implements a VMEbus Master/Slave A64/D64 A32/D64 A24/D32 interface
using the Tundra Semiconductor SCV64 integrated circuit. Master BLT (Block Transfer)
and MBLT (Multiplexed Block Transfer) cycles are also supported. On power-up, default
A32 and A24 slave images are loaded by the SCV64 with base addresses determined from
on-board switches (see section 4 for details of the hardware configuration). The VMEbus
Host can configure the SCV64 internal registers by accessing the SCV64 register block
acquisition #
5
acquisition #
4
acquisition #
3
acquisition #
2
acquisition #
1
buffer length = n * acquisition count
pre-trigger data post trigger data
acquisition count
buffer length
acquisition
count

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using either of these slave images. Note that the slave base address of the SCV64 can be
reprogrammed by the host by loading appropriate values in the SCV64 VMEbus Base
Address Register.
The SCV64 can be configured to perform VMEbus Master Block Transfers by loading the
SCV64 internal registers with the appropriate VMEbus Start Address, the local (to the
ICS-130) start address, and the transfer count. After the DMAGO bit in the SCV64 Control
Register is set, the SCV64 will acquire the VMEbus and perform the requested transfer,
freeing the host for other tasks. Note that the VMEbus specification limits block transfers to
a maximum of 256 Bytes, however the ICS-130 design does not prevent transfers of larger
blocks. Transfers can be in either D64 (MBLT) or D32 (BLT) data path width. D64 transfer
rates as high as 70 MB/s can be attained. A programmable VMEbus interrupt is available to
indicate that a transfer has been completed. Programmable interrupts are also available for
the ADC Data Ready condition.
3.7 Cascading Multiple Boards
The ICS-130 provides simultaneous sampling not only on all channels on one board, but
also on all channels across multiple boards. The ICS-130's PLL clock circuitry allows
multiple board systems to have simultaneous triggering (+/-0 samples) and less than 1.5
ns board to board sampling skew.
In order to achieve multiple board synchronization, one board is designated as the "Master"
and provides clock and trigger signals to the other (“Slave”) boards in the group. As with
single boards, either internal or external clock and trigger signals may be used with multiple
board configurations. In the case of external clock and/or trigger, the user supplies the
external signal(s) to the master, which in turn distributes the clock and trigger to the slaves.
Master/slave status can be programmed in the Control Register (see 5.8). The 20 pin
header on the front panel of the ICS-130 provides access to all signals necessary for multi
card synchronization. Details of the P4 pinout are given in appendix 6.3. The term Master in
this context should not be confused with VMEbus bus mastership.
Important note: All boards to be synchronized must be located in the same VMEbus
chassis in order to avoid violation of timing requirements.

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3.8 FPDP Interface
Aconnector on the front panel of the ICS-130, designated P3, is compatible with the ICS
FPDP Interface. The ICS Front Panel Data Port (FPDP) is an industry standard
interconnection for board to board or system to system data transfer. This interface
standard has gained acceptance in the industry for use in a broad range of signal
processing applications. It is directly compatible to CSPI's SC130/P100, Mercury's
RIN-T/ROUT-T, SKY's SKYburst 160 and Ixthos' IXI2S32-F interfaces.
The FPDP is a high performance 32 bit parallel interface configured with a ribbon cable to
connect boards or systems together. The simple and well-defined physical and electrical
interface provides the basis for integrating many different types of boards and sub-systems.
The maximum clock rate of the FPDP interface is 20 MHz when using the TTL Strobe
signal, providing a sustained data rate of up to 80 MBytes/s. When using the optional
PECL-level differential Strobe signals, the interface supports clock rates up to 40 MHz for a
sustained data rate of up to 160 MB/s. The ICS-130 provides the optional PECL Strobe,
and can typically be run up to 50 MHz.
The ICS-130 FPDP interface design allows multiple boards to be connected on the same
FPDP cable. Data from all selected channels are inserted into the FPDP Data frame in the
correct time slot. It is necessary to connect a cable between the P4 Local Bus connectors of
each ICS-130 in order to ensure that all boards are correctly synchronized (see section 3.7
above). One ICS-130 is configured as the Sampling Master for this purpose, by
programming Control Register bit CR<6>, and generates the timing signals used by the
other (Slave) boards. The same board must also be configured as FPDP Master using
Control Register bit CR<8>. The board designated as Master must be at one physical end
of the FPDP and Local Bus cables.
3.9 Light-Emitting Diodes
The ICS-130 is fitted with a set of light-emitting diodes (LEDs) which indicate board
operation and error conditions. The LEDs are provided for diagnosis of major operational
problems and can only be viewed when the board is on an extender card.
The diodes are located on the component side of the board (the right hand side when the
board is installed in vertical orientation), between the VME connectors. Their position on
the board is shown in Fig. 3. There are four LEDs installed in a line. Table 3.1 describes
the ICS-130 LEDs starting from the LED closest to the P1 VME connector (i.e. the
uppermost LED when the board is installed in normal vertical orientation).
Note that the intensity of illumination of each LED will depend on the frequency of the
access to that interface. It may not be possible to detect infrequent accesses to an
interface.

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TABLE 3.1 -Light Emitting Diodes
LED Function Colour Description
1. VME Access Green Illuminated at each valid VMEbus access to
ICS130
2. P2 Access Green Illuminated at each valid P2 access to
ICS-130
3. FPDP Out Green Illuminated at each valid FPDP access to
ICS-130
4. ADC Running Green Illuminated for each ADC sample acquired

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4. HARDWARE PREPARATION
This section provides information necessary for hardware preparation of both single
board and multiple board ICS-130 systems. Figure 3 shows the position of switch and
jumper (wire link) blocks on the ICS-130.
Prior to board installation, the user should examine the VMEbus chassis where the ICS-130
board is to be installed. Some VMEbus signals are of the "daisy chain" type, i.e. they are
routed through each board in turn using one connector pin for input to a board, and another
pin for output; the signals in question are BG0IN/OUT, BG1IN/OUT, BG2IN/OUT,
BG3IN/OUT and IACKIN/IACKOUT. For slots where boards will not be installed, one of two
mechanisms is normally employed to ensure continuity for these signals. Either the user
must install a set of jumpers on the VMEbus backplane, or the connectors are of a type
which can sense the presence of a board and make or break the connection accordingly. If
the backplane in use is a jumpered type, the user should remove all jumpers for the slot
where an ICS-130 will be installed. All unused slots between slot 1 and the slot where the
ICS-130 is installed must be jumpered to ensure correct operation.
4.1 System Configuration
The ICS-130 is designed to allow simultaneous sampling across all channels on a
board, and also across all channels on multiple boards. To facilitate multiple board
clusters, timing and external clock/trigger signals are bussed on the front panel P4
Local Bus cable. In addition, if the Front Panel Data Port (FPDP) is used for data
output, multiple ICS-130 boards may be bussed on the same FPDP cable.
Two multiple board cluster configurations are possible:
•All ICS-130 boards on one Local Bus cable and on one FPDP cable
•All ICS-130 boards on one Local Bus cable, but on two or more FPDP cables
The latter case addresses the situation where a single FPDP cable would not have
sufficient throughput, or where the FPDP/R-(receiver) board has insufficent
throughtput and multiple receiving boards must be used.
For the purposes of correctly driving and terminating bussed front panel signals, there
are four possible hardware switch configurations for an ICS-130 board. These are:
•Master -the board drives timing signals and terminates received signals
•Mid-Slave -the board does not terminate or drive signals except data lines
•End-Slave -the board terminates timing signals and drives data lines
•Stand-alone Master -the board drives and terminates all signals

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P2
P1
CO
SW3
P7
P6
P4
P5
JP1JP2
JP3 1
8
1LED 1
LED 4
P3
K10385-2
Figure 3-ICS-130 Switch and Jumper Locations

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Note that the term “End Slave” refers to an ICS-130 board, not the FPDP receiving
board. These classifications are applicable to both Local Bus and FPDP operation. It is
possible therefore, for a board to be a Local Bus Mid-Slave but an FPDP Master, FPDP
End-Slave or FPDP Stand-alone Master. The Master board must be located at one end
of the cable. The End-Slave is located at the opposite end of the cable to the Master.
The Mid-Slaves are located in between the Master and End-Slave boards. In a two
board system, only Master and End-Slave configurations apply. Finally, the Stand-
Alone Master refers to a one board system. The required register settings are
determined by which of these four cases applies to the board in question. Also, switch
and register settings are affected by whether a configuration uses internal or external
clock (EXT_CLK+/-) and trigger (EXT_ACQ+/-) signals.
If the ICS-130 board/s is/are connected to one or more Digital Signal Processor (DSP)
or Array Processor boards using the FPDP, the DSP board/s should be installed in the
chassis at the End-Slave end of the FPDP cable (i.e. the ordering should be Master,
Mid-slaves, End-Slave, DSP). If FPDP is not being used, the position of the DSP
board/s in the chassis with respect to the ICS-130 boards is not important, however it is
recommended that the ICS-130 boards are installed in adjacent slots.
4.2 Jumper and Switch Settings
A number of hardware configuration jumpers (wire links) and one switch block need to be
configured on the ICS-130. Figure 3 shows the locations of the jumpers and switches on
the component side of the board. Switches and jumpers are numbered thus: SWx-y and
JPx-y, referring to position y of switch or jumper x, respectively.
4.2.1 VMEbus Base Address Selection
The VMEbus A24 and A32 Base Address is set with jumpers JP1 (8 positions) and JP3 (2
positions). JP2 is an unused jumper block available for storage of spare jumpers. The
values of these switches are loaded to SCV64 register VMEBAR at power up. This register
may be subsequently reprogrammed by the user (see section 5.2). The ICS-130 address
map occupies a 384KB (Hexadecimal 0x60000) space. In A24 mode, the user may specify
the values of A23 to A19, allowing the base address to be set to any value between
0x00080000 and 0x00F80000, in increments of 0x80000.
The default A24 base address is 0x500000. This is the setting shown in Fig. 3.

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The A24 base address is set as follows:
Jumper VME A24 Address Bit
JP1-1A23
JP1-2A22
JP1-3A21
JP1-4A20
JP1-5A19
In A32 mode, the user may specify the values of A31 to A27, allowing the base address to
be set to any value between 0x08000000 and 0xF8000000, in increments of 0x8000000.
The A32 base address is set as follows:
Switch VME A32 Address Bit
JP1-6A31
JP1-7A30
JP1-8A29
JP3-1A28
JP3-2A27
Note: An inserted jumper selects a zero in that address bit.
The VMEbus A64 base address is programmed after power up; details of the procedure for
doing this are given in section 5.2

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4.2.2 P4 Local Bus Interface
Switch block SW3 is used to connect parallel (pull-up/pull-down) resistive terminations to
the External Clock and Trigger signals, as shown in the following table. These are required
if the user chooses not to use serial terminating resistors at the signal transmitter/s. Other
functions of the P4 Local Bus can be programmed by software using the Control Register
(see section 5.7). When connecting external clock and/or trigger signals to a multiple board
FPDP configuration, it is recommended that the terminations should be enabled on the
master board only, and that the signals should be driven from the End Slave end of the
cable so that the terminations are at the far end of the cable.
SWITCH FUNCTION (When switch in "ON" or Closed Position)
SW3-1Terminate External Clock Input
SW3-2Terminate External Trigger Input