ISG LW-3-S-1394 User manual

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LW-3-S-1394 FireWireTM
Smart Digital Imaging Module
LW-3-S-1394-C – Color
Available in Color Only.
Specification and Users Guide
Revision 2.1
LightWise Camera Series

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Table of Contents:
1 LW-3-S-1394 Introduction and Specification Overview
1.1 Product Description
1.2 Key Specifications
1.3 3 MP Image Sensor
1.4 Programming and User Configuration Options
1.5 Automatic Gain and Offset Correction
1.6 On-Board Image Buffer
1.7 Digital Panning & Scaling (Zoom)
1.8 JPEG Compression
1.9 Simplified Block Diagram
2 External Signals and Connectors
2.1 External Trigger Modes
2.2 External Connectors
3 Programming Guide
3.1 Top Level Memory Map
3.2 Register Detail
4 Mechanical Information
4.1 Lens Mount
4.2 Tripod Connection
4.3 Digital Imaging Module Dimensions
4.4 Module Components
4.5 Operating Conditions
5 Firmware and FPGA Upgrade Process
Appendix A: Color Image Processing Pipeline
Appendix B: IIDC 1394-based Digital Camera Specification

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Section 1: LW-3-S-1394-C Introduction and Specification Overview
1.1 Product Description
The ISG LW-3-S-1394-C 'Smart' Digital Imaging Module provides a High Resolution
area imaging solution with outstanding flexibility. The low cost and ease of integration
into existing systems make it an excellent solution for a wide variety of applications. The
interfaces to the Imager are industry standard to provide ease of integration into target
systems. Applications include:
Automated Inspection Systems
2D Bar Code Reading
Machine Vision Systems
Encoding and Positioning
Parcel Scanning
Programmable Smart Camera Applications
Smart Surveillance
Security and Homeland Defense.

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1.2 Key Specifications
• Resolution: 2048 x 1536 Pixels
• Color only Available
• Synchronous Shutter (Rolling) with advanced Trigger/Strobe capability
• Data Rate:
o Up to 12 Frames / second full resolution
o Up to 27 Frames / second full frame (1.3 Mp)
o Up to 90 Frames / second VGA
o Scalable frame rate as a function of Region of Interest
• Data Resolution: On-Chip 10 bit A to D
• Dynamic Range >62dB
• On-Board FPN Correction
• On-Board Multiple Frame Image Buffer (SRAM)
o For up to 10 Color or 30 Monochrome Images
• Optional JPEG and M-JPEG
• Digital Panning with Flexible Region of Interest
• Standard FireWireTM (1394a) Interface (see TM note, page 23)
o Fully compliant to IEEE-1394a IIDC DCAM Specification Version 1.3
• Single 12V Supply via FireWire
• Compact Form Factor
• User Programmable Exposure Timing and Frame Rate
• Built-In Test Pattern
• I/O for Triggers and Synchronization Flexibility
• On-Board FPGA for User-Configurability
o Customized Image Processing Capability
o Customized Programmable I/O
• High Quality Digital Panning and Zoom Capabilities.

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1.2.1 ISG Color Image Processing Pipeline
The LW-3-S-1394-C Color Imaging Module utilizes the ISG Hardware Image Processing
Pipeline implemented in a XilinxTM FPGA. All color processing parameters are fully
programmable by the user. Appendix B describes the image path.
1.3 3.1 MP CMOS Image Sensor
The module utilizes a 3.1 MP CMOS image sensor. Please contact ISG for Sensor details
if needed. 2048 x 1536
1.4 Programming and User Configuration Options
The LW-3-S-1394-C offers several levels of programmability and user configurability.
These include:
- Full Parameter Control, Set-Up and Operation Control via the ISG Graphical
User Interface Software. This software is included with each unit.
- Full Parameter Control, Set-Up and Operation Control via direct access of the
module’s register set. Section 3 is the programmer's reference for this mode of
operation.
- Customization of on-board FPGA. The on-board FPGA can be customized to
include 'Smart' Camera functionality, such as specialized image processing, data feature
extraction, custom dynamic range mapping, JPEG Compression , etc. This method can
also be used to configure the external I/O signals for custom functionality. Imaging
Solutions Group is available for consulting with customers to design or enable custom
configurations via the on-board FPGA. Contact sale[email protected] for information.

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1.5 Automatic Gain and Offset Correction
The LW-3-S-1394-C will provide on-board FPN correction through gain and offset
compensation. The FPGA algorithms in conjunction with an on-board dual 8-bit DAC
perform automatic offset correction and semiautomatic gain corrections. These functions
can be selected and activated by the provided ISG Graphical User Interface (GUI)
software, or can be accessed directly via register programming.
1.6 On-Board Image Buffer
The LW-3-S-1394-C provides on-board image buffering for up to one raw or 10 JPEG
frame color or three frames raw monochrome full resolution 2048 x 1536. Combined
with the module’s flexible trigger modes, this image buffer enables capturing a sequence
of frames at the maximum frame rate of the sensor, then transferring the frames at any
available 1394 bandwidth.
1.7 Digital Panning Scaling (Zoom)
The LW-1.3-S-1394-C camera provides full frame rate smooth digital panning. This
allows a region of interest of any size to be swept through the entire active viewing area
via host computer control. A very high quality digital scaling function is also
implemented for Zoom feature capability.
1.8 JPEG Compression
As an option, with associated NRE, the LW-1.3-S-1394-C provides compression utilizing
JPEG or M-JPEG standards.

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1.9 Simplified Block Diagram
1394A (+12V in)
3.1 MP
CMOS
Sensor
With
On-
board
10-bit
ADC
Image
Conditioning and
Control FPGA
'Smart"
Algorithm Space 1394a
Controller/
Drivers/
Receivers
L
W
-3-S-1394-C
On-Board
Image Buffers
Up to 1 frames for Color
Or Up to 3 frames for
Monochrome full
resolution 2048 x 1536
Programmable I/O
(with +5V, +12V out)
Opto-
Isolators
Power Ckts.,
Regulators
Timing
Generator.

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Section 2: Connectors and Trigger Modes
Section 2.1:
ISG Camera Module Triggering Description
The ISG camera module provides a variety of triggering modes and flexibility using features
internal to the FPGA controller as well as the sensor. For a more detailed description of the
registers referenced in this document see the Programmers Reference manual.
Register Description:
Trigger Delay – A 16 bit value used to delay the start of integration from the active edge of the
input trigger. This value can be programmed in steps of 20.83us to a maximum value of 1.37s.
Strobe Advance – This 8 bit register is used to apply the strobe signal a programmed amount of
time before the start of sensor integration to allow for illumination turn on time. This value can be
programmed in steps of 5.21us to a maximum value of 1.33ms. Note: The trigger delay must be
greater then the strobe advance.
Strobe Delay – This 16 bit register is used to delay the strobe signal a programmed amount of
time after the start of sensor integration. This delay is intended for use with flash illumination
devices. This value can be programmed in steps of .65us to a maximum value of 42.7ms. Note:
The strobe delay must not exceed the integration time of the sensor. If a value is programmed for
Strobe Advance the Strobe Delay value will be ignored.
Retrigger Delay – The 16 bit value in this register is used to program the time between
integration intervals when in Retrigger Mode. This value can be programmed in steps of 5.2us to
a maximum value of 341ms.
Strobe Duration - This register is used to program the duration of the strobe pulse when strobe
duration mode is enabled. This value can be programmed in steps of 5.2us to a maximum value of
341ms. Note: The strobe output will go inactive at the end of sensor integration no mater what
the strobe duration is set to.
Trigger and Strobe Description:
The input trigger sense can be active low or high. A software trigger is also available to the
programming interface (Host Mode) as well as a trigger status bit. The strobe output is intended
to control an illumination system and can be selected to be active low or high as well as always
high or always low. The diagrams on the following pages show the trigger as active low and the
strobe as active high.

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Trigger Input
Trigger Mode A = IIDC Trigger Mode 0
Strobe Advance Shown
Strobe Output
Sensor Integration
Trigger Delay
Strobe
Advance
SensorReadout
Note: In this mode the integratin time is determined by a register setting.

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Trigger Input
Trigger Mode A = IIDC Trigger Mode 0
Strobe Delay Shown
Strobe Output
Sensor Integration
Trigger Delay
Strobe
Delay
SensorReadout
Note: In this mode the integratin time is determined by a register setting.

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Trigger Input
Trigger Mode A = IIDC Trigger Mode 0
Strobe Duration Shown
Strobe Output
Sensor Integration
Trigger Delay
SensorReadout
Note: In this mode the strobe duration is determined by the strobe duration registor. Also, the Strobe Duration mode
bit must be enabled.
Strobe Duration

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Trigger Input
Trigger Mode B = IIDC Trigger Mode 1
Strobe Output
Sensor Integration
Trigger Delay
Strobe
Advance
SensorReadout
Note: In this mode the integratin time is determined by the trigger duration.

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Trigger Input
Trigger Mode C
Strobe Output
Sensor Integration
Trigger Delay
Strobe
Advance
SensorReadout
Note: In this mode the integratin time is determined by a register setting.
Strobe
Advance
Rerigger Delay

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2.2 External Connectors
2.2.1 FirewireTM Connector: This interface is based on the industry standard 1394a
specification. Two connectors are provided to allow camera daisy chaining.
2.2.2 15-position D-SUB I/O Connector:
o Connector part number: Molex part number 83612-9020
o Thumb Screw part number: Molex MDSM – 9PE-Z10-VR25
o Recommended Cable: Molex CA 83422-9014
Pin Function Input/Output Type
1 Trigger + Optoisolated Input
2 Trigger - Optoisolated Input
3 GND
4 DC Input (Optional) Power Input
5 Strobe Open Collector Output
6 Programmable PWM Open Collector Output
7 GND
8 DC Input (Optional) Power Input
9 RS422 Trigger + Diff. TTL Input
10 RS422 Trigger - Diff. TTL Input
11 DC +5V Output Power Output
12 Programmable Output + Optoisolated Output
13 Programmable Output - Optoisolated Output
14 Reserved
15 GND
1 8
9 15
15-pin Micro-D EXT IO Connector, Front View

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RSS422 Tri
gg
er -
RS422 Tri
gg
er +
ISG Imager Module
Ext I/O Header
Opto Isolator
Input Circuit
(O
p
to Tri
gg
er)
User Interface
10V – 24 V DC, 20ma source max.
Signal rate up to 60 KHZ
Trigger +
Trigger -
DC source power (12V typical) @ 200 mA
DC Return
5V DC Out @ 250 mA
E
xternal Input Output Inter
f
ace connection
RS422 Receiver
TI SN65HVD3082ED
(Differential Trigger)
RS422 Driver
TI SN65HVD3082ED
Or equivalent
See applications example on next
page.
Up to 200
kbps
4.7K Pull-up
T
o
5
V
4.7K Pull-up
To 5V
Open
Collector
Buffer
PWM
Strobe
50 Ohm

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Applications Example: Using The RS422 Trigger Input
1) Preferred Method – RS422 Driver
The optimal way to utilize this input to trigger the camera is to drive the RS422 Receiver
in the camera with the corresponding driver device. The recommended driver is TI part
number SN65HVD3082ED. This method provides a balanced, robust differential input.
2) Alternate Method - Driving the RS422 Trigger Input with Standard
3.3 or 5 Volt CMOS/TTL Logic
Standard digital logic can be used to simulate a differential signal and trigger the camera
using the RS422 input. This can be accomplished by generating a 3.3 or 5 Volt logic
signal for RS422 Trigger +, and providing a logically inverted output of this signal for
RS422 Trigger -. The following diagram illustrates this approach:
N
on-Inverting Buffer
3.3 or 5 Volt Logic
Inverting Buffer
3.3 or 5 Volt Logic
Trigger Trigger + (to pin 9)
Trigger - (to pin 10)

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Section 3: Programming Guide
3.1 Top Level Memory Map: All addresses are offset from address 0x7000
Sensor Map 0x000 - 0x3ff B12
Sensor Interface
SICR 0x400 B15 Sensor Interface Control (Control Register1)
SISTAT 0x404 Sensor Interface Status
TRGDLY 0x408 U16 Trigger Delay
STRBDLY 0x40C U16 Strobe Delay
RTGDLY 0x410 U16 Retrigger Delay
PWM 0x414 U8 PWM Duty Cycle
STRADV 0x418 U8 Strobe Advance
STRDUR 0x41C U16 Strobe Duration
VVDLY 0x420 U4 Video Valid Delay
IBISCR 0x424 B10 Not Used
INTCNT0 0x428 U32
Not Used
INTCNT1 0x42C U32
Not Used
INTCNT2 0x430 U32
Not Used
INTCNT3 0x434 U32
Not Used
PADCNT 0x43C U32 Not Used
IBACCUM 0x440 Not Used
STATVAR 0x444 U5 Not Used
CLKCR 0x448 U5 Clock Divider/Control
SERRB 0x44C Data from serial (delayed) read
Color Image Path or Mono Image Path Control
IPCR 0x800 B14 Image Path Control
IPSTAT 0x804 B2 Image Path Status
HISTCOLSTRT 0x808 U12 Histogram Window Column Start
HISTCOLWIDTH 0x80C U12 Histogram Window Column Width
HISTROWSTRT 0x810 U11 Histogram Window Row Start
HISTROWDEPTH 0x814 U11 Histogram Window Row Depth
HISTCR 0x818 B4 Histogram Control
HISTADDR 0x81C U5 Histogram Address
HISTDATA 0x820 U26 Histogram Data
DGAIN 0x824 U4.4 Digital Gain
LUTADDR 0x8B4 U10 Look Up Table Address
LUTDATA 0x8B8 U10 Look Up Table Data

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3.2 Register Detail
Note: Some data formats are given as (S/U # of integer bits. # of fractional bits). For
example, S1.3 means the value can be either positive or negative with the first bit indicating
the sign, one integer bit and three fractional bits. U0.8 means no sign bit (positive number),
zero integer bits and eight fractional bits. Negative values must be programmed as 2’s
complement. A format of Bn means a binary format with n bits used.
Address : 400x0 (CNTL1)
Data format : B15
Default Value: 00h
15 14 13 12 11 10 9 8
Not used OUTFMT[3:0] LUTEN
7 6 5 4 3 2 1 0
IMRST TRGSNS VIDEN HTRIG STRBM[1:0] TRIGM[1:0]
TRIGM: Trigger Mode. These bits control the trigger source as well as trigger operation.
TRIGM[1:0] = 00 : Local Trigger, One Shot
TRIGM[1:0] = 01 : Local Trigger, Retriggerable
TRIGM[1:0] = 10 : Host Trigger, One Shot
TRIGM[1:0] = 11 : Host Trigger, Retriggerable
Local Trigger: Trigger is input directly to camera via external connector.
Host Trigger: Trigger is issued via 1394 interface.
One Shot: Edge on trigger input initiates one video frame.
Retriggerable: Repeats Frames as long as trigger input is active. Time between
frames controlled by RTGDLY register.
When in one-shot mode, integration time can be controlled by the FPGA, the
IBIS sensor or the trigger duration. The control for this is located in Control
Register 2. The table below shows some possible modes and register settings
using an external trigger.
Trigger Mode TRIGM[1:0] IBMODE[1:0] (Control
Reg 2)
Trigger mode A (IIDC Trigger Mode
0)
00b 10b Use FPGA register to
control integration time.
Trigger mode B (IIDC Trigger Mode
1)
00b 11b Use trigger duration to
control integration time.
Trigger mode C 01b 01b Use sensor register to
control integration time.

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STRBM : Strobe Mode. These bits control the functionality of the Strobe output to the
illumination system.
STRBM[1:0] = 00 : Active high (Activated by trigger).
STRBM[1:0] = 01 : Active Low (Activated by trigger).
STRBM[1:0] = 10 : Always high (Not activated by trigger).
STRBM[1:0] = 11 : Always low (Not activated by trigger).
HTRIG : Host trigger bit. Asserted via 1394 interface.
VIDEN : Video Enable bit. This bit is set after imager is initialized.
TRGSNS: Trigger Sense
IMRST: Imager Reset, Controls the SS_RESET pin on IBIS Sensor
OUTFMT: Output Format. These bits control the output data format.
OUTFMT[3:0] = 0000 : 8 bit data output. (default)
OUTFMT[3:0] = 0001 : 10 bit data output in 16 bit field with LSB’s padded with
0.
OUTFMT[3:0] = 0010 : 10 bit data output in 16 bit field with MSB’s padded
with 0.
OUTFMT[3:0] = 0100 : Test pattern Enable
OUTFMT[3:0] = 1000 : 10 bit data. No padding.
LUTEN: Look up Table Enable. Set this bit to ‘1’ to enable 10 bit to 10 bit data mapping
via programmable look up table. Reset this bit to ‘0’ to bypass look up table.
Address : 0x404 (STAT)
Data format : B1
Default Value: 00h
7 6 5 4 3 2 1 0
not used TSTAT
TSTAT : Trigger Status. This read only bit is high when local trigger is asserted.

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Address : 0x408 (TRGDLY)
Data format : U16
Default Value: 00h
15 14 13 12 11 10 9 8
TRGDLY(15:8)
7 6 5 4 3 2 1 0
TRGDLY(7:0)
TRGDLY : This 16 bit Value is used to program a delay from the time trigger is received to
when strobe is activated. A delay between 0 and 1.37s in 20.83us steps can be
achieved. The default value is 0.
Address : 0x40c (STBADV)
Data format : U16
Default Value: 00h
15 14 13 12 11 10 9 8
STBADV(15:8)
7 6 5 4 3 2 1 0
STBADV(7:0)
STBADV : This 8 bit Value is used to program the delay between the Strobe output
(illumination) and tart of sensor integration. The default value is 0.