JYTEK PCIe/PXIe-6302 User manual
PCIe/PXIe-6302
24 bits High-Resolution
Thermocouple Input Module
User Manual
User Manual Version: V1.9.3
Revision Date: Jan.17, 2022
Table of Contents
1.Overview.....................................................................................................................1
1.1 Introduction......................................................................................................1
1.2 Main Features.................................................................................................. 1
1.3 Abbreviations................................................................................................... 2
1.4 Learn by Example............................................................................................. 2
2.Hardware Specifications............................................................................................ 5
2.1 System Diagram................................................................................................5
2.2 Sensor Connection........................................................................................... 6
2.3 Specification..................................................................................................... 7
2.3.1 Input Characteristics............................................................................. 7
2.3.2 Timing and Trigger.................................................................................8
2.3.3 Physical and Environment.....................................................................8
2.4 Front Panel conections and Pinout Definition................................................. 9
3.Performance Test..................................................................................................... 11
3.1 Voltage Accuracy............................................................................................ 11
3.2 Temperature Accuracy................................................................................... 16
4.Software....................................................................................................................17
4.1 System Requirements.................................................................................... 17
4.2 System Software.............................................................................................17
4.3 C# Programming Language............................................................................ 18
4.4 6302 Hardware Driver....................................................................................18
4.5 Install the SeeSharpTools from JYTEK............................................................ 18
4.6 Running C# Programs in Linux........................................................................18
5.Operating 6302 Module........................................................................................... 20
5.1 Quick Start......................................................................................................20
5.2 AI Operations..................................................................................................20
5.2.1 Channel Scan Sequence...................................................................... 20
5.2.2 ADC Timing Modes.............................................................................. 22
5.2.3 Sampling Rate......................................................................................26
5.3 Cold-junction compensation.......................................................................... 28
5.4 Open thermocouple detection.......................................................................29
5.5 Trigger Source................................................................................................ 31
5.5.1 Immediate Trigger...............................................................................31
5.5.2 Software Trigger..................................................................................31
5.5.3 External Digital Trigger........................................................................31
5.6 Trigger Mode..................................................................................................34
5.6.1 Start Trigger.........................................................................................34
5.6.2 Reference Trigger................................................................................ 36
5.6.3 Retrigger..............................................................................................36
Learn by Example 5.6.2 and 5.6.3................................................................ 37
5.7 System Synchronization Interface（SSI）for PCIe Modules......................... 39
5.8 DIP Switch in PCIe-6302................................................................................. 39
6.Calibration................................................................................................................ 41
7.Using 6302 in Other Software..................................................................................42
7.1 Python............................................................................................................ 42
7.2 C++..................................................................................................................42
8.About JYTEK.............................................................................................................. 43
8.1 JYTEK China.....................................................................................................43
8.2 JYTEK Korea and JYTEK in Other Countries.................................................... 43
8.3 JYTEK Hardware Products.............................................................................. 43
8.4 JYTEK Software Platform................................................................................ 44
8.5 JYTEK Warranty and SupportServices............................................................ 44
9.Statement................................................................................................................. 45
Figure 1 JYPEDIA Information.................................................................................2
Figure 2 TB- 68CJ terminal block............................................................................ 3
Figure 3 TB-68CJ Pin Define....................................................................................4
Figure 4 6302 System Block Diagram.....................................................................5
Figure 5 Themocouple connection.........................................................................6
Figure 6 PXIe/PCIe 6302 Front Panel..................................................................... 9
Figure 7 Typical Error (30mV Input)..................................................................... 11
Figure 8 Typical Error (65mV Input)..................................................................... 11
Figure 9 Typical Noise (Level 0)............................................................................12
Figure 10 Typical Noise (Level 1)..........................................................................12
Figure 11 Typical Noise (Level 2)..........................................................................13
Figure 12 Typical Noise (Level 3)..........................................................................13
Figure 13 Typical Noise (Level 4)..........................................................................14
Figure 14 Typical Noise (Level 5)..........................................................................14
Figure 15 Typical Drift (30mV Input)....................................................................15
Figure 16 Typical Drift (60mV Input)....................................................................15
Figure 17 Typical channel scan sequence............................................................ 21
Figure 18 Random channel scan sequence..........................................................22
Figure 19 AI Continuous Raw Data Paraments.................................................... 24
Figure 20 Continuous Raw Data Acquisition........................................................25
Figure 21 Acquisition State.................................................................................. 25
Figure 22 A/D conversion and sampling.............................................................. 26
Figure 23 Terminal Block State Check..................................................................29
Figure 24 Open Thermocouple Detection............................................................30
Figure 25 Rising and falling edges of digital signals............................................. 31
Figure 26 Digital Trigger Paraments.....................................................................32
Figure 27 Digital Trigger Acquisition.................................................................... 33
Figure 28 Start Trigger mode............................................................................... 34
Figure 29 AI Continuous Paraments.....................................................................35
Figure 30 Signel Channel Continuous Acquisition................................................35
Figure 31 Reference Trigger mode.......................................................................36
Figure 32 Retrigger mode.....................................................................................37
Figure 33 Retrigger Paraments............................................................................ 38
Figure 34 Retrigger In Reference Trigger Mode...................................................38
Figure 35 Retrigger Complete State..................................................................38
Figure 36 SSI Connector in PCIe-6302..................................................................39
Figure 37 DIP Switch in PCIe-6302....................................................................... 40
Table 1 63xx on different buses............................................................................. 5
Table 2 6302 channel grouping..............................................................................6
Table 3 Input Characteristics..................................................................................8
Table 4 Timing and Trigger Specification............................................................... 8
Table 5 Physical and Environment......................................................................... 9
Table 6 Pinout defination.....................................................................................10
Table 7 Voltage Accuracy..................................................................................... 11
Table 8 Input noise...............................................................................................12
Table 9 Input Stability.......................................................................................... 15
Table 10 Temperature Accuracy.......................................................................... 16
Table 11 Measurement sensitivity.......................................................................16
Table 12 Supported Linux Versions......................................................................17
Table 13 A/D conversion time at different speed levels......................................23
Table 14 ADC Timing Modes and maximum aggregate sampling rate................27
Table 15 SSI Connector Pin Assignment for PCIe-6302........................................39
Table 16 Relationship between switch position and slot number.......................40
PCIe/PXIe-6302 | jytek.com | 1
1. Overview
This chapter presents the information how to use this manual and quick start if you
are already familiar with Microsoft Visual Studio and C# programming language.
1.1 Introduction
JYTEK PCIe/PXIe-6302 is a high-resolution temperature measurement module which
provides up to 32 channels, supports R/S/B/J/T/E/K/N/C/A type thermocouple, with
input voltage range of -78.125 mV ~ +78.125 mV and sample rate up to 800
Samples/sec.
With 24 Bits ADC chip and analog-to-digital conversion mechanism optimized for
voltage measurement, the PCIe/PXIe-6302 has an optimum voltage measurement
offset error of up to 1µV and a voltage measurement gain error of 2 ppm.
PCIe/PXIe-6302 has a very low temperature drift, with a typical bias error
temperature drift of 10 nV/°C and a maximum offset error temperature drift of 0.1
µV/°C.
1.2 Main Features
32 channels of thermocouple measurements
3 voltage ranges:±78.125 mV / ±39.06 mV / ±19.53 mV
Support R/S/B/J/T/E/K/N/C/A type thermocouple
8 cold-junction compensation channels provided by 2 TB-68CJ terminal
boxes
Onboard 128M sample FIFO buffer for analog input
DMA for analog input
24 bits resolution
Provide EMF temperature measurement value
Digital and Software Trigger
PCIe/PXIe-6302 | jytek.com | 2
1.3 Abbreviations
AI: Analog Input
ADC: Analog to Digital Conversion
PFI: Programmable Function Interface
CJ:Cold-Junction
CJC: Cold-Juntion Compensation
OTD: Open Thermocouple Detection
1.4 Learn by Example
JYTEK has added Learn by Example in this manual. We provide many sample
programs for this device. You can download a JYPEDIA excel file from our web
www.jytek.com. Open JYPEDIA and search for JY6302 in the driver sheet, select
JY6302_Examples.zip. This will lead you to download the sample program for this
device. In addition to the download information, JYPEDIA also has a lot of other
valuable information, JYTEK highly recommends you use this file to obtain
information from JYTEK.
Figure 1 JYPEDIA Information
In a Learn by Example section, the sample program is in bold style such asWinform
AI Continuous; the property name in the sample program is also in bold style such as
SamplesToAcquire; the technical names used in the manual is in italic style such as
SampleRate. You can easily relate the property names in the example program with
the manual documentation.
PCIe/PXIe-6302 | jytek.com | 3
In a Learn by Example section, the experiment is set up as follow. A PCIe/PXIe- 6302
card is plugged in a desktop computer. The PCIe/PXIe-6302 is connected to a TB-
68CJ terminal block.
Figure 2 TB- 68CJ terminal block.
The TB-68CJ has 4 terminal columns, J1 – J4 are shown below as Figure 3. In the rest
of this manual, the wire connection in each Learn by Example section will be given
by the pin numbers only.
PCIe/PXIe-6302 | jytek.com | 5
2. Hardware Specifications
The 6302 is one of the family of temperature data acquisition module which provides
different interfaces, such as PCIe, PXIe, TXI(Thuderbolt) and USB buses (coming soon).
6302 on different interfaces is shown in Table 1.
Table 1 63xx on different buses
2.1 System Diagram
Figure 4 6302 System Block Diagram
Figure 4 shows the system diagram of the 6302. The system is mainly composed of
ADC, DDR and FPGA control modules. The FPGA-based driver code provides a stable
and efficient PCIe / PXIe / USB interface. 6302 has four ADCs, which can work alone
or together depending on channel configuration. Each ADC is responsible for the
measurement of one group of 8 channels and selects one of the 8 channels through
the multiplexer at the falling edge of AD conversion clock, as shown in Figure 22.
The channel grouping is shown in Table 2.
PCIe/PXIe-6302 | jytek.com | 6
Table 2 6302 channel grouping
6302’s dedicated terminal block TB-68CJ has build-in temperature sensors for
measuring cold-juntion temperature to achieve cold-junction compensation (CJC).
* The terms "hot junction" and "cold junction" are used in this manual, which
also called "measuring junction" and "reference junction".
2.2 Sensor Connection
Figure 5 Themocouple connection
Table of contents
