KMC Controls KZM-ARM11-01 User manual

ARM11-Embedded Evaluation Board
KZM-ARM11-01
Operation Manual
Kyoto Microcomputer Co., Ltd.

2 ---- Introduction
Introduction
KMC’s KZM-ARM11-01 is a new evaluation board that has a 532 MHz ARM1136 core (i.MX31 from freescale™
semiconductor) embedded and comes with Linux 2.6. With the supplied Linux 2.6 source/binary codes and ARM11 tool chain
this evaluation board can be used immediately after purchase for many purposes ranging from development of ARM11-based
Linux applications to debugging of user product boards.
KZM-ARM11-01 is also useful for prototyping/evaluating systems based on ARM11 or Linux, development of diverse
middleware operating with Linux/ARM11, and evaluation of operation systems such as Linux, Windows CE, and ITRON.
Combined use with Kyoto Microcomputer Co.,Ltd.(KMC)’s “PARTNER-Jet” JTAG debugger and “PARTNER/Wｉｎ”
debugger, which is a Windows-compatible source-level debugger, as well as the ”exeGCC” compiler allows users to
efficiently and effectively perform their development/evaluation.
Important Notice
Thank you for purchasing this KMC product. Customers are
advised to complete user registration so that we can smoothly
perform after-sales services and provide guidance information about
future upgrade and/or new models We will also use the registered
data as a benchmark for our future development and sales efforts.
With the user registration form filled in and returned to us each
customer will be registered in our user list and authorized to receive
support services and hardware certificates.
*This manual is protected under the Copyright Law of Japan. Reproduction, reprint or modification of this manual is
prohibited without prior written permission from KMC.
*All the rights including copyright, sales and other proprietary rights of this product belong to KMC.
*Contents and specifications of this product may be subject to change without notice.
*This product has been manufactured under the best efforts of KMC. However, KMC. shall not be liable for any
damages arising from the use of this product.
*Generally, the name of each program, system, and device referred in this manual is the registered
trademark of each manufacturer.

Contents ---- 3
Contents
1 Features 5
2 Appearance 6
3 Installed Devices 7
4 Block Diagram 8
5 Memopry Map 9
6 Various Settings 11
6.1 External Power Supply DC-JACK：J4 ---------------------------------------------------------------------------------------------------------- 11
6.2 Mode Selector：RSW1 ------------------------------------------------------------------------------------------------------------------------------- 12
6.3 SJC_MOD Setting：JP11----------------------------------------------------------------------------------------------------------------------------13
6.4 Clock Source Setting：JP10 ----------------------------------------------------------------------------------------------------------------------- 13
6.5 BOOT MODE Setting：DSW1,JP11 ------------------------------------------------------------------------------------------------------------- 14
6.6 JTAG /SRST and i.MX31reset signal settings：SW2,3,JP12 ------------------------------------------------------------------------- 15
6.7 NF_DET Setting：JP1 -------------------------------------------------------------------------------------------------------------------------------- 15
6.8 USB OTG PW R Setting：JP16----------------------------------------------------------------------------------------------------------------- 15
6.9 LCD ENB Setting：JP4 ----------------------------------------------------------------------------------------------------------------------------15
6.10 Interrupt------------------------------------------------------------------------------------------------------------------------------------------------- 16
6.11 Memory ------------------------------------------------------------------------------------------------------------------------------------------------- 16
6.11.1 NOR FLASH MEMORY ----------------------------------------------------------------------------------------------------------------- 17
6.11.2 Mobile DDR MEMORY------------------------------------------------------------------------------------------------------------------- 18
7 Description of Functions 20
7.1 External Expansion Connector：CN7 (not preinstalled) ----------------------------------------------------------------------------------- 20
7.2 PCMCIA-------------------------------------------------------------------------------------------------------------------------------------------------- 20
7.3 UART1---------------------------------------------------------------------------------------------------------------------------------------------------- 21
7.4 UART2---------------------------------------------------------------------------------------------------------------------------------------------------- 21
7.5 IrDA ------------------------------------------------------------------------------------------------------------------------------------------------------- 21
7.6 USBOTG------------------------------------------------------------------------------------------------------------------------------------------------- 22
7.7 LAN-------------------------------------------------------------------------------------------------------------------------------------------------------- 22
7.8 SD/MMC ------------------------------------------------------------------------------------------------------------------------------------------------- 22
7.9 KEYPAD ------------------------------------------------------------------------------------------------------------------------------------------------- 23
7.10 AC97 ---------------------------------------------------------------------------------------------------------------------------------------------------- 23
7.11 ATA ------------------------------------------------------------------------------------------------------------------------------------------------------ 24
7.12 LCD (option) ---------------------------------------------------------------------------------------------------------------------------------------- 25
7.13 TOUCH PANEL (option) ------------------------------------------------------------------------------------------------------------------------ 25
7.14 CAMERA (option) ---------------------------------------------------------------------------------------------------------------------------------- 25
8 BOARD Controller 26
8.1 BOARD CONTROL ---------------------------------------------------------------------------------------------------------------------------------- 26

4 ---- Contents
8.1.1 control------------------------------------------------------------------------------------------------------------------------------------------- 26
8.2 NAND FLASH control ------------------------------------------------------------------------------------------------------------------------------ 31
8.3 F_UART-------------------------------------------------------------------------------------------------------------------------------------------------- 35
9 Connector Pins Assignment 37
9.1 JTAG Connector -------------------------------------------------------------------------------------------------------------------------------------- 37
9.1.1 ARM ETM Type：CN13 --------------------------------------------------------------------------------------------------------------------- 37
9.1.2 ARM 20-Pin Type (without tracing)：CN16 ---------------------------------------------------------------------------------------------- 38
9.2 External Expansion Connector：CN7 (not installed) --------------------------------------------------------------------------------------- 39
9.3 PCMCIA-------------------------------------------------------------------------------------------------------------------------------------------------- 41
9.4 USBOTG------------------------------------------------------------------------------------------------------------------------------------------------- 42
9.5 UART1---------------------------------------------------------------------------------------------------------------------------------------------------- 43
9.6 UART2---------------------------------------------------------------------------------------------------------------------------------------------------- 44
9.7 LAN RJ45----------------------------------------------------------------------------------------------------------------------------------------------- 45
9.8 SD/MMC ------------------------------------------------------------------------------------------------------------------------------------------------- 46
9.9 KEYPAD ------------------------------------------------------------------------------------------------------------------------------------------------- 47
9.10 ATA ------------------------------------------------------------------------------------------------------------------------------------------------------ 48
9.11 LCD (option) ---------------------------------------------------------------------------------------------------------------------------------------- 50
9.12 TOUCH PANEL (option) ------------------------------------------------------------------------------------------------------------------------ 51
9.13 CAMERA (option) ---------------------------------------------------------------------------------------------------------------------------------- 52
10 About the Sample Software 53
Appendices
1, Circuit Diagram
2, Dimensions

Features ---- 5
1 Features
・ High-speed RISC i.MX31: incorporates Freescale™Semiconductor MCIMX31VKN5 (ARM1136JF-S core chip) .
The core of i.MX31 is ARM1136JF-S (532 MHz) .
Built-in L2 cache in addition to L1 cache.
Vector Floating Point Unit (VFP) installed.
・ Built-in large-capacity Mobile-DDR RAM：Equivalent to HYB18M512160×2 (128 Mbytes)
・ Provided with JTAG port for connecting JTAG cable. Provided also with an ETM connector.
・ Possible to accommodate emulation memory (EMJ) .
＊ Has a dedicated connector installed for emulation memory (EMJ). This eliminates the need to connect with the
conventional ROM socket (DIP42PIN) and makes it possible to reduce the connection area and simplify the
connection method through this dedicated connector.
・ Easy connection with PARTNER-Jet.
The i.MX31 manual can be downloaded via the following links:
Freescale™Semiconductor top page: http://www.freescale.com
Manual (2006/9)
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX31&nodeId=02XPgQ82172973ZrDR

6 ---- Appearance
2 Appearance
9
5712 14
17
8411
6
6
9
13
25
23
22
26
18
20
15
27
28
16
24
10
19
10
Fig1 Appearance (top)
3
21
Fig.2 Appearance (back side)
(1) i.MX31 CPU
Built-in i.MX31 peripherals
(2) ATA
(3) PCMCIA
(4) SD/MMC
(5) UART1
(6) UART2
(7) IrDA FIR
(8) USB2.0 On-The-Go(OTG)
(9) KEYPAD
(10) LCD
(11) CAMERA
(12) AC97Audio
External devices connected to
memory bus
(13) DDR RAM
(14) NOR Flash ROM
(15) STD ROM
(16) Expansion connector
(17) LAN
(18) FPGA
(19) Rotary switch for
switching FPGA mode
External devices connected to
FPGA
(20) NAND
(21) NAND expansion
connector
(22) LED
(23) 7SEGLED
(24) 4-PIN DIP SW
Interface for debugging
(25) ARM JTAG
(26) ARM ETM
Other
(27) POWER switch
(28) DC-JACK

Installed Devices ---- 7
3 Installed Devices
CPU i.MX31 ：MCIMX31VKN5 (457PIN MPBGA)
Memory FLASH MEMORY ：S29GL512N-equivalent (64 Mbytes) 16-bit
Mobile-DDR-SDRAM ：HYB18M512160-equivalent×2 (128 Mbytes) 32-bit
NAND FLASH MEMORY ： 29F2G08AAB-equivalent (256 Mbytes) 8-bit
Standard ROM connector ：8931E-050-178S (manufacturer: KEL)
LAN LAN controller ：LAN9118
USB USBOTG controller ：USB3300
IrDA IrDA transceiver ：TFBS6711
AUDIO AC97 codec ：AD1981BL
UART RS232C driver ：MAX3237ECAI+
RS232C driver ：MAX3245ECAI+
PCMCIA PC-CARD slot ：IC14A-PL-SF-EJR (manufacturer: HIROSE) , for single slot
SD/MMC SD/MMC slot ：DM1AA-SF-PEJ (manufacturer: HIROSE)
NAND CN Expansion NAND connector ：DF12D (3.0) -40DP-0.5V (manufacturer: HIROSE)
7SEG LED ：
External expansion connector ：Double line 100-PIN with a pitch of 1.27
JTAG ：20-PIN connector, HIF3FC-20P (manufacturer: HIROSE)
ETM-compatible connector, 767054-1 (manufacturer: AMP)
KEYPAD ：4X8
Touch panel controller ：AHL-71N (manufacturer: GUNZE)
Clock 532 MHz (XTAL 26 MHz)
Board size 310×185 mm
Power supply +9V (from external source via DC-JACK)
Optional Units
LCD LCD Panel ：FT035SB320240-B1 3.5inch QVGA
Touch Panel ：H3035A-NCOFA39 (manufacturer: hantouch)
Camera Color camera ：MTV-54K0DN
HDD Hard disk ：2.5 inch, 80 G-equivalent
* Above listed components and modules may be subject without notice to replacement by other
compatible products.

8 ---- Block Diagram
4 Block Diagram
Fig.3 Block Diagram
CPU
MC9328MX31
NAND 256MByte
29F2G08AAB compatible
NAND CN
D-SUB9P Male
（DTE）
IrDA
TFBS6711-TR1
EXT
RS-232 DRIVER
MAX3245ECAI+
AC97 CODEC
AD1981BL
STEREO
MINI JACK
SSI4
KPP
UART2
SDHC1
ATA
USBOTG
SW
SW
SW
UART1
LCD
FT035SB320240-B1
RS-232 DRV
MAX3237ECAI+
CS0
PCMCIA
CS0
CS0or1
CSD0
IPU(DI)
IPU(CSI)
TOUCH PANEL
RJ45
CONTROL IC
AHL-71N(GUNZE)
USB
miniAB
USBOTG
USB3300
Keypad
4 * 8
Standerd ROM CN
max 64MByte (EMJ)
Standard ROM CN
Select CS1 when connected
NOR FLASH 64MByte
S29GL512N compatible
SDRAM 128MByte
Mobile-DDR-SDRAM
64MByte*2
HYB18M512160 compatible
LAN 10/100Mbps
LAN9118
FPGA
EP1C
CAMERA
ETM
767054-1
Debug/JTAG
2.54pitch 20P
PC-CARD
ATA-44P
2.5inch HDD
option
SD
H3035A-NCOFA39
CN5
CN7
CN7
CN27
CN28
J6
J1~3
CN13
CN16
D-SUB9P Male
（DTE）
CN6
Local MEMORY
Expansion connector
1.27picth 100PIN
CPU PERIPHERAL
Debug I/F
7SEG LED
LED *4
4-slider DIPSW
DC JACK
(9V) 5V 1.2V
1.8V
3.0V
CPU Core
QVCC, QVCC1,QVCC4
Memory
NVCC2, NVCC21, NVCC22
Peripherals
Regulator Regulator
Regulator
Regulator
Switch（POWER）

Memory Map ---- 9
5 Memory Map
The following tables show memory maps of this board. The addresses shown are physical addresses.
For details of the Internal Register Space refer to the CPU Manual.
Start Address End Address Size Name
0x0000 0000 0x0000 3FFF 16 Kbytes Secure ROM
0x0000 4000 0x0040 3FFF 4 Mbytes Reserved
0x0040 4000 0x0040 7FFF 16 Kbytes ROM
0x0040 8000 0x0FFF FFFF 252 Mbytes – 32 Kbytes Reserved
0x1000 0000 0x1FFF BFFF 256 Mbytes – 16 Kbytes Reserved for RAM aliasing
0x1FFF C000 0x1FFF FFFF 16 Kbytes RAM
0x2000 0000 0x2FFF FFFF 256 Mbytes Reserved
0x3000 0000 0x7FFF FFFF 1024 Mbytes Internal Register Space
0x8000 0000 0x87FF FFFF 128 Mbytes CSD0 DDR SDRAM
0x8800 0000 0x8FFF FFFF 128 Mbytes CSD0 DDR SDRAM aliasing
0x9000 0000 0x9FFF FFFF 256 Mbytes CSD1 Not installed.
0xA000 0000 0xA7FF FFFF 128 Mbytes CS0 16bit Flash 64 Mbytes *1
0xA800 0000 0xAFFF FFFF 128 Mbytes CS1 16bit Flash 64 Mbytes *1
0xB000 0000 0xB1FF FFFF 32 Mbytes CS2 Unavailable (shared pin with CSD0)
0xB200 0000 0xB3FF FFFF 32 Mbytes CS3 Unavailable (shared pin with CSD1)
0xB400 0000 0xB400 0FFF 4 Kbytes CS4 8-bit free space
0xB400 1000 0xB400 100F 16 bytes Board Control
0xB400 1010 0xB400 101F 16 bytes 7SEG LED
0xB400 1020 0xB400 102F 16 bytes LED
0xB400 1030 0xB400 103F 16 bytes LCD
0xB400 1040 0xB400 104F 16 bytes Reserved
0xB400 1050 0xB400 105F 16 bytes FPGA UART
0xB400 1060 0xB40F FFFF 1 Mbyte Reserved for FPGA
0xB410 0000 0xB5FF FFFF 31 Mbytes Free
0xB600 0000 0xB61F FFFF 128 Kbytes CS5 16bit LAN
0xB620 0000 0xB62F FFFF 128 Kbytes 16bit FPGA NAND Controller
0xB630 0000 0xB7FF FFFF 32 Mbytes - 256 Kbytes Free
0xB800 0000 0xB800 4FFF 20 Kbytes memory control registers
0xB800 5000 0xBFFF FFFF 128 Mbytes - 20 Kbytes Reserved
0xC000 0000 0xC3FF FFFF 64 Mbytes PCMCIA/CF
0xC400 0000 0xFFFF FFFF 960 Mbytes Reserved
Table 1 Memory Map
*1 Mapping when the standard ROM is connected will be different from this.

10 ---- Memory Map
For the memory size of the emulation memory (EMJ) refer to the Emulation Memory (EMJ) Manual.
The following memory map assumes that EMJ-64M (64 Mbytes) is connected. For a smaller-capacity memory, additional
spaces for aliasing will be secured in CS0.
With EMJ being connected
Start Address End Address Size Name
0xA000 0000 0xA3FF FFFF 64 Mbytes CS0 CS0 STD ROM 64 Mbytes
0xA400 0000 0xA7FF FFFF 64 Mbytes
CS0 (STD ROM aliasing) 64
Mbytes
0xA800 0000 0xABFF FFFF 64 Mbytes CS1 CS1 (Flash) 64 Mbytes
0xAC00 0000 0xAFFF FFFF 64 Mbytes CS1 (Flash aliasing) 64 Mbytes
Table2 Memory Map
Without EMJ being connected
Start Address End Address Size Name
0xA000 0000 0xA3FF FFFF 64 Mbytes CS0 CS0 (Flash) 64 Mbytes
0xA400 0000 0xA7FF FFFF 64 Mbytes CS0 (Flash aliasing) 64 Mbytes
0xA800 0000 0xABFF FFFF 64 Mbytes CS1 CS0 (Flash aliasing) 64 Mbytes
0xAC00 0000 0xAFFF FFFF 64 Mbytes CS0 (Flash aliasing) 64 Mbytes
Table3 Memory Map

Various Settings ---- 11
6 Various Settings
This section describes the jumper plug settings, etc. on this board. If you attempt to modify any of these settings, refer to the
Circuit Diagram in the Appendix of this document for an understanding of the jumper plug concerned.
External power supply DC-JACK J4
Mode selector rotary switch RSW1
SJC_MOD setting JP11
Clock source setting JP10
BOOT MODE DSW1,JP17
JTAG /SRST and i.MX31 reset signal settings JP12
USB OTG PWR JP16
NF_DET JP1
LCD_ENB JP4
6.1 External Power Supply DC-JACK：J4
Model No.：HEC3110-01-010, Manufacturer：HOSHIDEN
This DC-JACK connects to the external power source for the KZM series.
A +9V power will be supplied for this board via this DC-JACK.
When the power is supplied, LED1 turns on. When this happens, pressing the POWER switch (SW1) switches the
main power of the board ON.
If the POWER switch (SW1) is pressed while the board power is ON, it will turn OFF.
The power dissipation of this single board (without any optional device installed) is 1500 mA (maximum).
POWER スイッチ（SW1
）
LED2
LED1
DC-JACK
(J4)
Fig.4 CN3 External Expansion Connector 1
Power switch (SW1)

12 ---- Various Settings
6.2 Mode Selector：RSW1
This is used to switch over the modules for use depending on the selector position. It enables switching between
ATA and CAMERA. Also for UART1, the output destination can be changed. A total of five selection modes are
provided and the current switch setting can be seen from the control register.
0
RSW1
Fig.5 RSW1 (factory setting)
RSW1 0 1 2 3 4 5-F
ATA × ○× ○× ×
RS232C-1 CN5 CN5 CN5 CN7 CN7 CN5
CAMERA × × ○× ○×
Table4 RSW1

Various Settings ---- 13
6.3 SJC_MOD Setting：JP11
This is the setting for enabling the JTAG debugger unit. The factory default is short-circuited, and under regular
operations does not need to be changed.
The JTAG connector is for connecting with the PARTNER-series JTAG cable. It may be either the ETM type
(CN13) or 20-pin type (CN16) shown below. Concurrent use of both is not permitted. Only ever use either of them.
JTAG signal voltage is 3V. This product will support tracing of maximum 8 bits for the ETM type. The ETM clock
setting should be 1/4 if more than 500 MHz is used as the core clock. While JTAGICE is being used, do not use WFI
(wait for interrupt).
/SRST signal is connected to JP12 and also to POR_B (H24) of i.MX31 and RESET_IN_B (J21). The factory default
is POR_B setting. This does not have to be changed for regular operations.
DE signal is connected to JP16 and further to DE_B (C18) of i.MX31. The factory setting of JP16 is open.
Short-circuit this JP if using DE_B.
JP11
Fig.6 JP11 (factory settings)
CN16
JP12SW2 SW3
CN13
Fig.7 CN13 and 16 JTAG Connectors
6.4 Clock Source Setting：JP10
This is used to set the source of feeding clock signals to each PLL of i.MX31. The factory default is X1 (26 MHz).
This does not have to be changed under normal operations.
JP10
Fig.8 JP10, 11 (factory setting)

14 ---- Various Settings
6.5 BOOT MODE Setting：DSW1,JP11
Used to set the BOOT MODE. As the factory settings, 1,2,4=ON on DSW1 and JP17 are open-circuited.
Do not change these switch settings.
Fig 9 BOOT MODE SW, JP
value
i.MX31
SIGNAL
i.MX31
PIN
DSW 1-1 ON 0 (default) BT_MD0 F20
OFF 1
DSW 1-2 ON 0 (default) BT_MD1 C21
OFF 1
DSW 1-3 ON 0 BT_MD2 D24
OFF 1 (default)
DSW 1-4 ON 0 (default) BT_MD3 C22
OFF 1
JP17 SHORT 0 BT_MD4 D26
OPEN 1 (default)
Table 5 BOOT MODE SW, JP

Various Settings ---- 15
6.6 JTAG /SRST and i.MX31 Reset Signal Settings：SW2,3,JP12
Used to define the destination when connecting the JTAG debugger connector, /SRST. The factory default
is for connecting to the i.MX31’s POR_B.
It is configured as follows:
SW2 SW3 JP12
Fig.10 CN13, 16 JTAG Connector
JP
SW3 BUFFER
/
SRST
FPGA
CPU
SW2 BUFFER
POR_B
RESET_IN_B
Fig.11 Resetting
6.7 NF_DET Setting：JP1
Used as the test terminal for the NAND controller. The factory default is open. This does not have to be
changed for regular operations.
6.8 USB OTG PWR Setting：JP16
Connects the power supply line of USB OTG. The factory default is short-circuited. This does not have
to be changed for regular operations.
6.9 LCD ENB Setting：JP4
Used to establish ENB pin settings for the LCD. The factory default is open-circuited. This does
not have to be changed for regular operations.

16 ---- Various Settings
6.10 Interrupt
The interrupt function of this product is implemented in such a way that the ARM1136JF-S Vectored Interrupt Controller
(AVIC), which is one of the devices of i.MX31, is connected to the interrupt input port. This AVIC can accommodate a
maximum of 64 interrupt sources. Interrupts from each of i.MX31 peripherals are assigned to this AVIC, and the GPIO pins
are used for external interrupts. In this product each device is connected via GPIO to the IRQ or FIQ port of i.MX31 as shown
below. For details of each interrupt setting refer to the i.MX31 Manual.
The GPIO1_1 interrupt port for NAND, F_UART and SD is masked under the initial conditions. To make it function, set with
the registers in the FPGA Controller.
i.MX31
AVIC
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_4
GPIO1_5
nFIQ
nIRQ
Internal Peripherals
ARM1136JF-S
AVIC_IRQ
AVIC_FIQ
Fig.12 Interrupt
6.11 Memory
The External Memory Interface (EMI) of i.MX31 accommodates various types of memory devices. The dedicated built-in
controller controls these devices. Memory clock (HCLK) is generated in the CCM by dividing the clock frequency of PLL
MCU. HCLK is set to 106 MHz. Then, this clock rate will be used for setting memory access cycles. You may see “AHB
clock” in the i.MX31 Manual, however, the memory clock is always referred to as HCLK in this manual.
This product employs an NOR-type FLASH memory and Mobile DDR memory.
The setting method of each memory is described in the following.
These settings can be kept enabled while PARTNER-Jet is connected if an appropriate description has been made in
JETARM.CFG before starting the debugger. Make use of the sample settings prepared as the following file contained in the
PARTNER-Jet installation folder:
¥WJETARM¥Samples¥KZM-ARM11

Various Settings ---- 17
6.11.1 NOR FLASH MEMORY
The NOR FLASH MEMORY used in this product is linked to the CS0 address space (see the memory map) of the Wireless
External Interface Module (WEIM). The setting values related to this WEIM are shown below. With these settings the type of
memory, bus size, and control signal timing are defined. This memory does not require any special timing to set the registers
but can be accessed at any time after all the registers have been properly set. Every bus size except for ＣＳ０ can be set with
the WEIM (CSCRxL DSZ). The bus size of CS0 will vary with the BOOT mode. For more information refer to the CPU
Manual.
CSCR0U address 0xB800_2000 data 00001800
13–8 WSC Wait State Control 24
CSCR0L address 0xB800_2004 data 45450D01
31–28 OEA OE Assert 4
27–24 OEN OE Negate 5
23–20 EBWA Enable Byte W rite Assert 4
19–16 EBW N Enable Byte Write Negate 5
15–12 CSA Chip Select Assert 0
11 EBC Enable Byte Control 1
10–8 DSZ Data Port Size DSZ=101 16-bit port,
7–4 CSN Chip Select Negate 0
0 CSEN Chip Select Enable １
CSCR0A address 0xB800_2008 data 00450000
23–20 RWA Read/Write Assertion 4
19–16 RWN Read/W rite Negation 5
Set an appropriate access cycle via Wait State Control.
The time for accessing the FLASH memory is 90 ns. This is set by specifying WSC = 24XHCLK (2
28 ns). For other control signals, the half-clock-cycle (HCLK/2) setting is employed for each memory
control. See the figure shown below. “A” in the following figure refers to the cycle start position of
internal operation cycles.
HCLK
WSC=16
CSA=0
valid address
A
DDRES
S
CS
RW
OE
EB
RWA=4
A
RWN=5
CSN=3
OEA=4 OEN=5
EBWA=4 EBWN=5
Fig 13 Access Timing to CS0

18 ---- Various Settings
6.11.2 Mobile DDR MEMORY
The Mobile DDR MEMORY used for this product is linked to the CSD0 address space of the Enhanced SDRAM Controller
(ESDCTL). This product is designed to operate under HCLK of 106 MHz. The DDR memory serves as the SSTL interface
whilst the ESDCTL and Mobile DDR MEMORY are 1.8V LVCMOS. However, they will be initialized in the same manner as
the DDR memory. In addition, it is possible to set the PIN driving power for i.MX31 as follows: normal:2mA, high：6mA, and
max:8mA. This can be set with the SW_PAD_CTL Register in the IOMUXC module. Set this pin driving power before setting
up ESDCTL. From the nature of this board, pins should be set to active-high.
The SW_PAD_CTL Register affords for 32 bits for accessing, and three pins can be assigned for each address. This
assignment is made as 0：8 bits, 10:18 bits, and 20:28 bits and the 1st and 2nd bits among them are used for setting the driving
power.
Example active-high drive setting of SD29, SD30 and SD31 pins
address：0x43FA_C28c data: 0x1234_8D23
In this way set all the ESDCTL signals.
The ESDCTL-related settings include the controller-side modes, pre-charge, Auto-Refresh×８cycles, and memory-side modes.
These settings can be initialized with the registers of ESDCTL0 0xB800_1000, ESDCFG0 0xB800_1004, and ESDMISC
0xB800_1010, respectively. Setting values are that follow:
ESDCFG0 address：0xB800_1004 data: 0x0079_D72A
tMRD 2 cycles、tWR 2 cycles、tRAS 6 cycles、tRRD 2 cycles、tCAS 3 cycles
tRP 3 cycles、tRCD 3 cycles、tRC 10 cycles、tWTR 2 cycles、tXP 4 cycles
Precharge
ESDCTL0 address：0xB800_1000 data: 9210_0000
31 SDE:1 Controller Enable、30–28 SMODE:1 Precharge Command
MEMORY address：0x8000_0F00 data: 0
After setting to ESDCTL0, access the memory to issue the respective command.
Auto-Refresh
ESDCTL0 address：0xB800_1000,a2100000
31 SDE:1 Controller Enable、30–28 SMODE:2 Auto-Refresh Command
MEMORY address：0x8000_0000,0
MEMORY address：0x8000_0000,0
Auto-Refresh ×2
Load Mode Register
ESDCTL0 address：0xB800_1000,b2226080
31 SDE:1 Controller Enable、30–28 SMODE:3 Load Mode Register Command、26–24 ROW:2 13bit、
21–20 COL:2 10bit17–16 DSIZ:2 32-bit、15–13 SREFR：３ 7.81 μs、7 BL:1 Burst Length 8、
5–0 PRCT:0 Disabled
MEMORY address：0x8000_0033,0
6-4 CL:3 CAS Latency3、3 BT:0 Burst Type Sequential、2–0 BL:3 Burst Length 8
MEMORY address：0x8400_0020,0

Various Settings ---- 19
6-5 DS:1 Half Drive Strength
Normal
ESDCTL0 address：0xB800_1000,82226080
30–28 SMODE:0 Normal Read/Write
ESDMISC address：0xB800_1010,80000004
2MDDREN:1 Enable Mobile DDR SDRAM operation

20 ---- Description of Functions
7 Description of Functions
7.1 External Expansion Connector：CN7 (not preinstalled)
1.27mm-pitch Surface Installation Pad
Through this connector, signals to/from the local memory bus (WEIM) of i.MX31 are transmitted via a 3V buffer.
All these signals are rated to 3V.
CN7
Fig.14 CN3 External Expansion Connector
7.2 PCMCIA
Model No.：IC14A-PL-SF-EJR, manufacturer：HIROSE
・Host adapter interface with full compatibility with PCMCIA standard release 2.1 (PC Card-16).
・One PCMCIA socket.
・Supports hot swap capability.
・Supports detection of card presence.
・Supports five memory windows.
・Only one interrupt generated to ARM11 core.
・Possible to handle interrupts from card.
・PCMCIA controller is part of the EMI, and shares the same pins among EIM，SDRAMC，and built-in NAND Flash
controller of i.MX31.
・ATA supports disk emulation.
Fig.15 PCMCIA