LevelOne LXD970A User manual

NOVEMBER 1998
General Description Features

LXD970A Demo Board
for 10/100 and 100BASE-FX applications
LXD970 Demo Board
USER GUIDE
Revision 1.3
The LXD970A Demo Board is a versatile 10/100Mbps
Ethernet media access unit (MAU) that demonstrates all of
the integral features of the LXT970A Fast Ethernet
Transceiver.
The LXD970A provides a working platform for evaluation
of the LXT970A Fast Ethernet Transceiver in 10BASE-T
and/or 100BASE-TX/FX applications.
The LXD970A Demo Board is configured with a single
chip 10/100Mbps, IEEE 802.3u compliant, Fast Ethernet
Transceiver unit (LXD970A). The demo board is designed
to plug into a transceiver test box via a standard 40-pin MII
connector. This allows system designers to test 10Mbps
and 100Mbps link performance, auto-negotiation and
register functionality prior to board prototyping.
The LXT970A also provides an ECL-type interface for
100BASE-FX link testing.
This document describes typical Demo Board setup
procedures for a 100BASE-TX environment.
Before using the Demo Board, review the LXT970A Fast
Ethernet Transceiver data sheet for device functionality
and specifications.
• IEEE 802.3-compliant 10BASE-T and 100BASE-TX
using a single RJ45 connection.
• Quick setup, ease of use, and clear visibility of appli-
cation settings for:
- Complete system demonstration
- Individual circuit isolation
• LED indicators for major functions.
• IEEE 802.3u MII interface with extended register
capability.
• Configured for single 5V supply operation.
• Standard half duplex or full duplex operation at 10 or
100 Mbps.
• 100BASE-FX fiber optic capability (unstuffed
optional circuitry).
ENBL COL LNK TX RX
Optional
FIBER MODULE CIRCUIT
MF1 MF2 MF3 MF4MF0
TSTOPIBTST TSTON
JP7
MAN0
JP8
TEST
JP5
TD+
TD -
RD+
RD -
MDINT
GNDR
GNDT
JP6
MAN1
MAN2
JP1
JP3
JP4
MII
RJ45
TRANSFORMER

LXT970A
LEDs

LXD970A Demo Board for 10/100 and 100BASE-FX applications
2

EQUIPMENT AND SETUP
The LXD970A Demo Board includes all the components
needed for a successful evaluation. However, the
following additional equipment is recommended:
• NetCom System X-1000 transceiver test box
configured with firmware version 1.17 or newer.
• PC with Fast Ether Windows (version 1.5 or newer)
installed.
• Various lengths of Category 5 Unshielded Twisted-
Pair (UTP) cable (1, 20, 40, 60, 80, 100, 120 and 140
meters).
• For 100BASE-FX evaluation, a fiber-optic
transceiver module (HFBR-5103) and fiber-optic
cable are required.
Test Setup
Figure 1 shows a typical test setup for the basic operation
of the LXD970A. The LXD970A plugs directly into a
X1000 NetCom Transceiver TestBox via a standard40-pin
MII connector that is included on the board.
An optional test setup is shown in Figure 2 using a PC for
testing additional nodes.
Note: JP3 and JP4 must be installed on the LXD970A for
the Netcom System X-1000 transceiver test box to access
the MII management registers inside the LXT970A.
Figure 1: Basic Test Setup
Loading Test File
A disk that contains the file needed for testing is included
with the LXD970A demo board.
This file contains “Killer Packets” (100Tx4.s), that exhibit
worst case baseline wander characteristics suitable for
evaluating link performance and comparing the LXT970A
to alternative products. Some devices do not adjust well
over a range of cable distances. It is recommended to
compare LXT970A performance to similar devices over a
wide range of cable lengths.
Follow this simple procedure for loading test file into the
Netcom X-1000 test box:
• Load disk containing test pattern into computer
• Start Fast Ether Windows
• Click the “DATA PATTERN” button in the lower left
of the screen
• From the Data Pattern options presented, select
“CUSTOM”
• From the File menu, select “OPEN”, then select the
drive and directory where the test file is located. (If
you are using the disk from Level One, select
A:\100Tx4.s)
• When the test file is displayed on screen, select
“CLOSE”. This will automatically download the test
pattern to the Netcom X1000 test box
• Proceed with normal testing
Figure 2: Optional Test Setup
NETCOM
X1000
LXD970A
LXD970A
Serial
HUB
Port 1
Port 2
FAST ETHER
Windows
Terminal SW
RS232
RS232
UTP
UTP
RJ45
MII


PC
PC
NETCOM
X1000
LXD970A
LXD970A
UTP
Loop
MII
FAST ETHER
Windows
RS232


PC

LXD970 Equipment and Setup
3

Power Supply Option
The LXD970A includes a jumper (JP8), which provides a
an optional power supply source for the VCC pins; VCCA
(analog supply), VCCR (receive supply), VCCT (transmit
supply) and VCCD (digital supply). In the original factory
configuration, this jumper is shorted by a circuit trace and
all LXD970A power is supplied via theMII pin (J1). How-
ever, the circuit trace can be easily cut to provide the JP8
isolation option.
External +5V Supply for Analog
Circuitry (VCCA, VCCT and VCCR)
To provide an external +5V power supply for the
LXD970A analog circuitry, proceed as follows:
• Cut the circuit trace across JP8 pins 3 and 4
• Attach an external +5V supply to JP8 pin 3
This routes the external supply to VCCA, VCCT, and
VCCR (all circuits except VCCD and VCCIO). To restore
to factory configuration, disconnect the external power
supply and install the jumper block in JP8.
Test Points
There are 9 Test Points on the LXD970A Demo Board. Table 1 describes these.
Table 1: Test Point Descriptions
Label Ref Des Description
TD+ J3 Transmit Data Output Positive - Signals transmitted from LXD970A to TP link.
TD- J4 Transmit Data Output Negative - Signal transmitted from LXD970A to TP link.
RD+ J5 Receive Data Input Positive - Signals received from TP network.
RD- J6 Receive Data Input Negative - Signals received from TP network.
GNDA J8 Analog Ground
TSTON J9 Test Output Negative 1
TSTOP J10 Test Output Positive 1
IBTST J11 IB Test 1
MDINT J12 Management Data Interrupt 2 - Indicates status change.
1. Factory Test Only
2. 4.7kΩpull-up to VCC needed if used

LXD970A Demo Board for 10/100 and 100BASE-FX applications
4

JUMPERS
There are 7 Jumpers on the LXD970 Demo Board. Table 2 describes these jumpers and their functions.
Table 2: Jumper Descriptions
Ref Des Function
JP1 Hardware Control Interface: Provides access to voltage sensitive manual control functions. See
Tables 3, 4 and 5 for details.
JP3 MDIO: Connects the MDIO pin to the MII connector. With the trace cut and the jumper open, the
MDIO pin can be connected to an external device.
JP4 MDC: Connects the MDC pin to the MII connector. With the trace cut and the jumper open, the
MDC pin can be connected to an external device.
JP5 TEST: This jumper should not be installed for normal operation. This jumper is used to put the chip
into a test mode that is used to characterize the chip.
JP6 POWER DOWN: With the jumper installed the chip goes into a power down mode.
In power down mode the MII port (except MDIO and MDC), the twisted pair port and the LED pins
are tristated.
JP7 MII: 18-pin straight header that is connected to all the MII interface signal pins. There is a ground
test point next to C20 to ground probes to.
JP8 ANALOG VCC CONNECT: Connects MII connector power to the analog portion of the chip.
To use +5V power from MII connector:
No action required. The jumpers (pins 1 & 2 and 3 & 4) are shorted via a trace on the bottom of board.
However, if the traces are cut, the jumpers must be installed to supply power from MII to analog VCC
(VCCA).
To use alternate power supply for Analog VCC:
Cut the trace on the bottom of board across pins 3 and 4 shorting JP8. With no jumpers installed, an
external power can be connected. Provide an alternate power supply ( +5V) to pin 3 of JP8.

5

LXD970A Demo Board Hardware Control Interface
HARDWARE CONTROL INTERFACE
Multi-Function Pins
The Hardware Control Interface (JP1) provides access to the Multi-Function (MF) pins which decode 4-level supply
voltages to establish two independent settings per pin. The first setting determines chip address. The second setting
determines configuration of the LXD970A. The 4-level inputs referred to as VMF1, VMF2, VMF3 and VMF4 are shown in
Table 3.
To select an Input Level place a jumper on the appropriate pins. The 4-level input pins (VMF1, VMF2, VMF3 and VMF4)
are identical for each Multi-Function (MF) section. See Figure 3 for jumper placement.
Figure 3: Hardware Control Interface Jumper Placement
Table 3: MF Pins Input Voltage Levels
Parameter Symbol Min Max Units
Input Voltage Level 1 VMF1 Vcc - 0.5 - V
Input Voltage Level 2 VMF2 (Vcc/2) + 0.5 Vcc - 1.2 V
Input Voltage Level 3 VMF3 1.2 Vcc/2 - 0.5 V
Input Voltage Level 4 VMF4- 0.5V
1. TRSTE and MDDIS functions are not labeled on the board.
MDDIS
1
MAN0 (CFG0)
2
MAN1 (FDE)
2
MAN2 (CFG1)
2
TRSTE
1
pin 49
pin 50
pin 1
pin 2
MF0 MF1 MF2 MF3 MF4
V
MF
1
V
MF
2
V
MF
3
V
MF
4
Notes:
2. CFG1, CFG0 and FDE are pin names for the manual pins and are not labeled on the board.

LXD970A Demo Board for 10/100 and 100BASE-FX applications
6

Function/Address Settings
The multi-function pins allow the user to enable or disable the applicable functions and determine chip address according
to the input level selected. Table 4 shows the status of the function according to the (VMF) selection.
Table 4: Hardware Control Interface (JP1) Functions
Address Input Voltage Levels2
Pin Function VMF1 VMF2 VMF3 VMF4
MF0 Address Bit 0 1100
Auto-Negotiation
Sets the initial value of bit 0.12
Disabled
(0.12 = 0)
Enabled
(0.12 = 1)
Enabled
(0.12 = 1)
Disabled
(0.12 = 0)
MF1 Address Bit 1 1100
Repeater / DTE Mode
Sets the initial value of bit 19.13
DTE
(19.13 = 0)
Repeater
(19.13 = 1)
Repeater
(19.13 = 1)
DTE
(19.13 = 0)
MF2 Address Bit 2 1100
Nibble (4B) / Symbol (5B) Mode
Sets the initial value of bit 19.4
Nibble (4B)
(19.4 = 0)
Symbol (5B)
(19.4 = 1)
Symbol (5B)
(19.4 = 1)
Nibble (4B)
(19.4 = 0)
MF3 Address Bit 3 1100
Scrambler Operation
Sets the initial value of bit 19.3
Enabled
(19.3 = 0)
Bypassed
(19.3 = 1)
Bypassed
(19.3 = 1)
Enabled
(19.3 = 0)
MF4 Address Bit 4 1100
If Auto-Negotiate Enabled via MF0, MF4 works in combination with MAN2 (CFG1) to control
operating speed advertisement capabilities. See Table 5 for details.
If Auto-Negotiate Disabled
Then TX/F Mode
Sets the initial value of bit 19.2
100TX
(19.2 = 0)
100FX
(19.2 = 1)
100FX
(19.2 = 1)
100TX
(19.2 = 0)

7

LXD970A Demo Board Hardware Control Interface
Table 5: Operating Speed Advertisement Settings
MF4 Input
Voltage Levels1MAN2
(CFG1) Function
If Auto-Negotiate Enabled via MF0
VMF1, VMF4 Jumper Not Installed Advertise all capabilities, Ignore MAN1 (FDE)
VMF1, VMF4 Jumper Installed Advertise 10 Mbps only, Follow MAN1 (FDE)
VMF2, VMF3 Jumper Not Installed Advertise 100 Mbps only, Follow MAN1 (FDE)
VMF2, VMF3 Jumper Installed Advertise 10/100 Mbps, Follow MAN1 (FDE)
1. Input Voltage Levels (VMF1, VMF2, VMF3, VMF4) for MF pins.

LXD970A Demo Board for 10/100 and 100BASE-FX applications
8

Additional Jumper Functions
In addition to the MF pins, the Hardware Control Interface (JP1) contains 10 pins, (#41 - #50) that are labeled as MAN0,
MAN1, MAN2, TRSTE and MDDIS, (Note: TRSTE and MDDIS are not labeled on the demo board). MAN0 = CFG0,
MAN1 = FDE and MAN2 = CFG1. The Manual pins control the status of the applicable function by installing or removing
a jumper. See Table 6 for function status.
LED Indicators
There are 5 status LEDs on the Demo Board. Refer to Table 7 for LED descriptions.
Table 6: Additional JP1 Jumper Functions
Jumper
Label Function Status Jumper Installed Jumper Not Installed
MAN0
(CFG0) Restart Negotiation
(when Auto-Neg enabled)1Enable X
Disable X
Speed Select
(when Auto-Neg disabled)110Mbps X
100Mbps X
MAN1
(FDE) Full Duplex Enable X
Disable X
MAN2
(CFG1) Speed Advertisement Capabilities
(when Auto-Neg enabled)1When Auto-Neg enabled, MAN2 (CFG1) works in
combination with MF4 to control operating speed
advertising capabilities. See Table 5 for details
Link Test
(when Auto-Neg disabled)1Enable X
Disable X
Not Labeled
(TRSTE) Tristate (MDC and MDIO are not affected) Tristates MII Data Interface X
Normal
Operation X
Not Labeled
(MDDIS) MDIO Port Enable X
Disable X
1. Auto-negotiation is set via MF0.
Table 7: LED Descriptions
Label Ref Des Description
ENBL D1 Line Speed. Indicates 100Mbps operation
COL D2 Collision. Indicates collision
LNK D3 Link. Indicates connection
TX D4 Transmit Data. Indicates data being transmitted
RX D5 Receive Data. Indicates data being received

9

LXD970A Demo Board Hardware Control Interface
Figure 4: LXD970A Schematic

LXD970A Demo Board for 10/100 and 100BASE-FX applications
10

REVISION HISTORY
Table 8: Changes From Revision 1.2 to Revision 1.3 (11/98)
Section Page Change Text
All 1 - 9 Update Update entire document to LXD970A and LXT970A.
Loading Test File 2 Update Change killer packet test file name to (100Tx4.s).
Power Supply
Option 3 Update Delete external 3.3V supply option for VCCI/O.
Table 2
Jumper
Descriptions
4 Update Delete JP2. This jumper was removed from the demo
board.
Table 9: Changes From Revision 1.1 to Revision 1.2 (11/97)
Section Page Change Text
Loading Test File 2 Update Change killer packet test file name to (BLWANDER.S).
Table 10: Changes From Revision 1.0 to Revision 1.1 (07/97)
Section Page Change Text
Table 6 8 Update Change MDDIS function status to:
Enabled when jumper is removed .
Disabled when jumper is installed.

11

LXD970A Demo Board Notes
NOTES

EAST WEST ASIA/PACIFIC EUROPE
Eastern Area Headquarters &
Northeastern Regional Office Western Area Headquarters Asia / Pacific Area Headquarters European Area Headquarters
234 Littleton Road, Unit 1A
Westford, MA 01886
USA
Tel: [phone]
Fax: [phone]
3375 Scott Blvd., #110
Santa Clara, CA 95054
USA
Tel: [phone]
Fax: [phone]
101 Thomson Road
United Square #08-01
Singapore 307591
Thailand
Tel: [phone]
Fax: [phone]
Parc Technopolis-Bat. Zeta 3,
avenue du Canada -
Z.A. de Courtaboeuf
Les Ulis Cedex 91974
France
Tel: [phone]
Fax: [phone]
North Central
Regional Office South Central Regional Office Central Asia/Pacific Regional Office Central and Southern Europe Regional Office
One Pierce Place
Suite 500E
Itasca, IL 60143
USA
Tel: [phone]
Fax: [phone]
2340 E. Trinity Mills Road
Suite 306
Carrollton, TX 75006
USA
Tel: [phone]
Fax: [phone]
Suite 305, 4F-3, No. 75,
Hsin Tai Wu Road
Sec. 1, Hsi-Chih,
Taipei County, Taiwan
Tel: [phone]
Fax: [phone]
“Regus”
Feringastrasse 6
D-85774 Muenchen-
Unterfoerhring, Germany
Tel: [phone]
Fax: [phone]
Southeastern
Regional Office Southwestern Regional Office Northern Asia/Pacific Regional Office Northern Europe Regional Office
4020 WestChase Blvd
Suite 100
Raleigh, NC 27607
USA
Tel: [phone]
Fax: [phone]
28203 Cabot Road
Suite 300
Laguna Niguel, CA 92677
USA
Tel: [phone]
Fax: [phone]
Nishi-Shinjuku, Mizuma
Building 8F
3-3-13, Nishi-Shinjuku,
Shinjuku-Ku
Tokyo, 160-0023 Japan
Tel: [phone]
Fax: [phone]
Torshamnsgatan 35
164/40 Kista/Stockholm,
Sweden
Tel: [phone]
Fax: [phone]
Latin/South
America
9750 Goethe Road
Sacramento, CA 95827
USA
Tel: [phone]
Fax: [phone]
Revision Date Status
1.3 11/98 Change test file name to 100Tx4.s, delete JP2 and external +3.3V supply for VCC I/O.
1.2 11/97 Change test file name from: (blpktl.s and blpkt2.s) to (BLWANDER.S).
International
Corporate Headquarters
9750 Goethe Road
Sacramento, California 95827
Telephone:
(
916
)
855-5000
Fax:
(
916
)
854-1101
Web: www.level1.com 
Cop
y
ri
g
ht © 1997 Level One Communications, Inc. Specifications sub
j
ect to chan
g
e without notice.
All ri
g
hts reserved. Printed in the United States of America.
UG-T970A-R1.3-1198
This product is covered b
y
one or more of the followin
g
patents. Additional patents pendin
g
.
2002382-1; 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746;
5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,267,746; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341
The Americas