Lime Microsystems LMS6002D Instruction manual

LMS6002D Quick Starter Manual for Evaluation Board
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Lime Microsystems Limited
Surrey Tech Centre
Occam Road
The Surrey Research Park
Guildford
Surrey GU2 7YG
United Kingdom
LMS6002D Quick Start Manual
The information contained in this document is subject to change without prior
notice. Lime Microsystems assumes no responsibility for its use, nor for
infringement of patents or other rights of third parties. Lime Microsystems' standard
terms and conditions apply at all times.

LMS6002D Quick Starter Manual for Evaluation Board
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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Contents
1 Introduction................................................................................................................................ 7
2 Development System Contents.................................................................................................. 8
3 Evaluation Board Connections................................................................................................. 9
3.1 Basic Connections................................................................................................................. 9
3.2 Board Connections.............................................................................................................. 10
3.2.1. J1 –Main Power Supply Connector ..................................................................... 12
3.2.2. J2 –Third Party Baseband Board Connector........................................................ 13
3.2.3. J3 –Analogue IQ Signals ..................................................................................... 14
3.2.4. J5 –Digital I/O (I&Q) TX 12 Bit & TXIQSel and RX 12 Bit & RXIQSel ......... 15
3.2.5. J8 –Sourcing 5V Supply from Baseband Board.................................................. 16
3.2.6. J16 –USB Connector............................................................................................ 16
3.3 Hardware options: Clocking, TCXO & SPI. ...................................................................... 16
3.4 TCXO Frequency and Data Clocks Distribution................................................................ 17
3.5 Different Clocking Schemes............................................................................................... 18
3.6 TCXO Locking Options...................................................................................................... 19
3.7 SPI Control Options............................................................................................................ 20
4 Installing and Running PC Software Application ................................................................ 22
4.1 Windows XP Operating System ......................................................................................... 22
4.2 Determining Serial Port ...................................................................................................... 25
4.3 Windows 7 Operating System ............................................................................................ 26
4.3.1. Determining Serial Port ........................................................................................ 27
4.4 Turn On and SPI Check...................................................................................................... 28
4.5 Ctr6002dr2 –Software Description.................................................................................... 31
4.5.1. System Interface.................................................................................................... 31
4.5.2. Top level ............................................................................................................... 33
4.5.3. TX PLL + DSM.................................................................................................... 35
4.5.4. Rx PLL + DSM..................................................................................................... 39
4.5.5. Tx LPF.................................................................................................................. 44
4.5.6. Tx RF.................................................................................................................... 45
4.5.7. Rx LPF.................................................................................................................. 46
4.5.8. RX VGA2 ............................................................................................................. 48
4.5.9. RX FE ................................................................................................................... 49
4.5.10. ADC/DAC............................................................................................................. 51
4.5.11. Board..................................................................................................................... 54
5 Transmitter and Receiver Basic Setup .................................................................................. 56
5.1 Transmitter Setup and Basic Testing.................................................................................. 56

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
5.1.1. Top Level Setting.................................................................................................. 56
5.1.2. TX LPF & Gain Setting........................................................................................ 57
5.1.3. TX PLL Setup....................................................................................................... 58
5.2 Testing TX Output.............................................................................................................. 59
5.2.1. TX Basic Operation Checks.................................................................................. 60
5.3 Receiver Setup and Basic Testing....................................................................................... 61
5.3.1. Top Level Settings................................................................................................ 61
5.3.2. RX LPF & Gain Setting........................................................................................ 62
5.3.3. RX PLL Setup....................................................................................................... 63
5.4 Testing RX Output.............................................................................................................. 65
5.4.1. RX Basic Operation Checks ................................................................................. 65
6 LMS6002D Calibration Procedures....................................................................................... 66
6.1 TX LO Leakage Calibration ............................................................................................... 66
6.2 Transmit I/Q Balance Calibration....................................................................................... 69
6.3 Receiver DC Calibration..................................................................................................... 72
6.4 Calibration Process Summary............................................................................................. 76
7 Appendix A –Saving and Retrieving SPI Test Setups......................................................... 77
7.1 Saving a Setup..................................................................................................................... 77
7.2 Loading *.prj Files.............................................................................................................. 78
8 Appendix B –Test Systems Connections............................................................................... 80
8.1 Basic Setup.......................................................................................................................... 80
8.2 Transmitter Test System Connections................................................................................ 81
8.3 Receive Test System Connections...................................................................................... 81
9 Appendix C –Signal Generator Setup................................................................................... 82
9.1 Agilent MXG Setup............................................................................................................ 82
9.2 Downloading *.wfm Files to the Signal Generator ............................................................ 85
10 Appendix D –Common Receiver Test Issues...................................................................... 88
10.1 Verify the PLL is locked................................................................................................... 88
10.2 Is the Correct LNA Selected............................................................................................. 91
10.3 Is the Correct Rx VGA 2 Gain Selected........................................................................... 91

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Rev: 2.2
Last modified: 03/05/2012
Table of Figures
Figure 1 Development System Contents......................................................................................... 8
Figure 2 Evaluation board connection descriptions...................................................................... 10
Figure 3 Connector J1 circuit diagram.......................................................................................... 12
Figure 4 Connector J2 circuit diagram.......................................................................................... 13
Figure 5 Connector J3 circuit diagram.......................................................................................... 14
Figure 6 Connector J5 circuit diagram.......................................................................................... 15
Figure 7 Connector J8 circuit diagram.......................................................................................... 16
Figure 8 TXCO locking and SPI option components location (top side)..................................... 20
Figure 9 SPI control resistor component locations....................................................................... 21
Figure 10 Hardware wizard. ......................................................................................................... 23
Figure 11 Hardware wizard. Install driver manually................................................................... 23
Figure 12 Hardware wizard. Choose the USBDriver.inf from the folder..................................... 24
Figure 13 Check in device manager the new communication port............................................... 25
Figure 14 Device Manager. Choose the USBDriver.inf from the folder..................................... 26
Figure 15 Check in device manager the new communication port............................................... 27
Figure 16 Power supply reading................................................................................................... 28
Figure 17 Run ctr_6002dr2 program as an administrator............................................................. 28
Figure 18 GUI communication settings........................................................................................ 29
Figure 19 GUI register test. .......................................................................................................... 29
Figure 20 GUI register test log. .................................................................................................... 30
Figure 21 GUI System window. ................................................................................................... 31
Figure 22 GUI Top Level window................................................................................................ 33
Figure 23 GUI TxPLL + DSM window........................................................................................ 35
Figure 24 PLL mode..................................................................................................................... 36
Figure 25 Output Frequency –GHz.............................................................................................. 36
Figure 26 Calculated Values for Fractional Mode........................................................................ 37
Figure 27 VCO Capacitance......................................................................................................... 37
Figure 28 Current VCO and MUX/DIV selections ...................................................................... 37
Figure 29 VCO Capacitance........................................................................................................ 38
Figure 30 CP Current and Offset.................................................................................................. 38
Figure 31 Frequency versus capacitance calibration table data.................................................... 39
Figure 32 RX PLL + DSM page................................................................................................... 40
Figure 33 PLL Mode..................................................................................................................... 41
Figure 34 Setting receiver frequency - GHz................................................................................. 41
Figure 35 Calculated values for fractional mode.......................................................................... 42
Figure 36 VCO Capacitance......................................................................................................... 42
Figure 37 Current VCO and MUX/DIV selections ...................................................................... 42
Figure 38 VCO Capacitance......................................................................................................... 43
Figure 39 CP Current and Offset .................................................................................................. 43
Figure 40 Frequency vs capacitance calibration table data .......................................................... 43
Figure 41 Tx LPF page ................................................................................................................. 44

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Figure 42 Tx RF page ................................................................................................................... 45
Figure 43 Rx LPF page................................................................................................................. 46
Figure 44 Rx VGA2 page............................................................................................................. 48
Figure 45 Rx FE (Front End)........................................................................................................ 49
Figure 46 LNA Control setting..................................................................................................... 50
Figure 47 MIX Control settings.................................................................................................... 51
Figure 48 ADC/DAC page............................................................................................................ 52
Figure 49 DAC enable control timing for TX .............................................................................. 53
Figure 50 ADC enable control timing for RX.............................................................................. 53
Figure 51 ADC/DAC Reference control –default settings .......................................................... 54
Figure 52 ADC Control settings................................................................................................... 54
Figure 53 S/W control for on board ADF4002 –TCXO locking................................................. 55
Figure 54 Top Level Settings........................................................................................................ 57
Figure 55 Setting Tx LPF bandwidth............................................................................................ 57
Figure 56 Tx gain setting and PA selection.................................................................................. 58
Figure 57 Tx PLL setting.............................................................................................................. 59
Figure 58 Basic TX testing using DC offset resulting in LO leakage.......................................... 59
Figure 59 Top Level Settings........................................................................................................ 61
Figure 60 Setting Rx LPF to 7 MHz............................................................................................. 62
Figure 61 Setting Rx VGA2 gain.................................................................................................. 62
Figure 62 Rx LNA and VGA1 settings........................................................................................ 63
Figure 63 Rx PLL settings............................................................................................................ 64
Figure 64 Oscilloscope capture of 1 MHz I & Q Sine wave outputs ........................................... 65
Figure 65 Transmit Output............................................................................................................ 67
Figure 66 System Window. Use Automated Calibration.............................................................. 67
Figure 67 Transmit Output After Calibration............................................................................... 68
Figure 68 Tx RF window.............................................................................................................. 68
Figure 69 Transmit output after calibration.................................................................................. 69
Figure 71 Phase angle calibration................................................................................................. 70
Figure 70 Initial -1 MHz Image Spectrum.................................................................................... 70
Figure 72 Amplitude balance calibration...................................................................................... 71
Figure 73 Transmit EVM performance after calibration.............................................................. 71
Figure 74 Rx FE page................................................................................................................... 72
Figure 76 Rx VGA2 Tab............................................................................................................... 73
Figure 75 Rx LPF tab.................................................................................................................... 73
Figure 77 Receiver LO leakage .................................................................................................... 74
Figure 78 Rx VGA1 DC Offset Adjust in RX FE Tab................................................................ 74
Figure 79 Rx automatic DC calibration result.............................................................................. 75
Figure 80 Save Project feature...................................................................................................... 78
Figure 81 Open project ................................................................................................................. 78
Figure 82 Auto Download feature ................................................................................................ 79
Figure 83 Download Button for Previously Saved Setup............................................................. 79
Figure 84 Test system connections for receive and transmit Testing........................................... 80

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Figure 85 Transmitter test setup ................................................................................................... 81
Figure 86 Receiver test setup........................................................................................................ 81
Figure 87 Agilent N5181A/82A MXG Front Panel ..................................................................... 82
Figure 88 Rx PLL VCO capacitance ............................................................................................ 89
Figure 89 No Receive Baseband Output....................................................................................... 89
Figure 90 Non-sinusoidal baseband Output.................................................................................. 90
Figure 91 Sinusoidal Baseband Output......................................................................................... 90

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
1
Introduction
The EVB6002-5 is a general purpose evaluation board intended to allow evaluation and testing
of the LMS6002D multi-band, multi-standard RFIC transceiver. It is not intended to act as a
guide to the best layout, decoupling and matching practices when implementing the LMS6002D.
The Lime LMS6002D reference board was developed with best layout, decoupling and matching
practices to deliver optimum LMS6002D RF performance.
This document provides instructions on how to load the evaluation board software ctr6002d onto
a PC, connect the PC to the board, control the LMS6002 via the ctr6002d software and evaluate
its performance. A summary of the main steps to complete this is shown below:
Install PC ctr6002d software.
Connect power supplies and cables to the evaluation board.
Turn on and do SPI and register checks.
Continue using this document to do the following:
Hardware/Board system set up for integration with baseband platforms.
Evaluate the LMS6002D performance.

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
2
Development System Contents
Before commencing any work please ensure all of the contents listed below are contained in the
system shipped. See Figure 1 Development System Contents below:
Figure 1 Development System Contents
5V Supply cable for
LMS6002D Board
PC to USB cable
USB software stick

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3
Evaluation Board Connections
The following chapter describes in detail EVB connectors, various SPI and clocking options.
3.1 Basic Connections
The analogue differential IQ BB interfaces are connected to transmit and receive paths via the J3
connector for use with test equipment. In addition there are on board differential to single ended
drivers on each of the receiver outputs to accommodate testing with an oscilloscope. An interface
via pin header J5 is provided to the parallel digital interface on the LMS6002D. A baseband
connector via pin header J2 is also provided to be used with third party basebands.
RX IN 1 is tuned from 700 –1500 MHz to cover UMTS bands V and VIII, whilst RX IN 2 is
tuned from 1.5 –2.5 GHz to cover UMTS bands I, II and III. RX IN 3 is connected with a broad
band balun that enables it to cover all bands and require no matching. TX OUT 1 is optimized
for band I, II operation while TX OUT 2 is tuned for broadband operation by the selection of the
matching components.

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© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.2 Board Connections
Figure 2 Evaluation board connection descriptions.
.
The following table describes the high level pin assignment for each connector on the evaluation
board.