Lime Microsystems LMS6002D Instruction manual

LMS6002D Quick Starter Manual for Evaluation Board
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Lime Microsystems Limited
Surrey Tech Centre
Occam Road
The Surrey Research Park
Guildford
Surrey GU2 7YG
United Kingdom
LMS6002D Quick Start Manual
The information contained in this document is subject to change without prior
notice. Lime Microsystems assumes no responsibility for its use, nor for
infringement of patents or other rights of third parties. Lime Microsystems' standard
terms and conditions apply at all times.

LMS6002D Quick Starter Manual for Evaluation Board
2 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Contents
1 Introduction................................................................................................................................ 7
2 Development System Contents.................................................................................................. 8
3 Evaluation Board Connections................................................................................................. 9
3.1 Basic Connections................................................................................................................. 9
3.2 Board Connections.............................................................................................................. 10
3.2.1. J1 –Main Power Supply Connector ..................................................................... 12
3.2.2. J2 –Third Party Baseband Board Connector........................................................ 13
3.2.3. J3 –Analogue IQ Signals ..................................................................................... 14
3.2.4. J5 –Digital I/O (I&Q) TX 12 Bit & TXIQSel and RX 12 Bit & RXIQSel ......... 15
3.2.5. J8 –Sourcing 5V Supply from Baseband Board.................................................. 16
3.2.6. J16 –USB Connector............................................................................................ 16
3.3 Hardware options: Clocking, TCXO & SPI. ...................................................................... 16
3.4 TCXO Frequency and Data Clocks Distribution................................................................ 17
3.5 Different Clocking Schemes............................................................................................... 18
3.6 TCXO Locking Options...................................................................................................... 19
3.7 SPI Control Options............................................................................................................ 20
4 Installing and Running PC Software Application ................................................................ 22
4.1 Windows XP Operating System ......................................................................................... 22
4.2 Determining Serial Port ...................................................................................................... 25
4.3 Windows 7 Operating System ............................................................................................ 26
4.3.1. Determining Serial Port ........................................................................................ 27
4.4 Turn On and SPI Check...................................................................................................... 28
4.5 Ctr6002dr2 –Software Description.................................................................................... 31
4.5.1. System Interface.................................................................................................... 31
4.5.2. Top level ............................................................................................................... 33
4.5.3. TX PLL + DSM.................................................................................................... 35
4.5.4. Rx PLL + DSM..................................................................................................... 39
4.5.5. Tx LPF.................................................................................................................. 44
4.5.6. Tx RF.................................................................................................................... 45
4.5.7. Rx LPF.................................................................................................................. 46
4.5.8. RX VGA2 ............................................................................................................. 48
4.5.9. RX FE ................................................................................................................... 49
4.5.10. ADC/DAC............................................................................................................. 51
4.5.11. Board..................................................................................................................... 54
5 Transmitter and Receiver Basic Setup .................................................................................. 56
5.1 Transmitter Setup and Basic Testing.................................................................................. 56

LMS6002D Quick Starter Manual for Evaluation Board
3 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
5.1.1. Top Level Setting.................................................................................................. 56
5.1.2. TX LPF & Gain Setting........................................................................................ 57
5.1.3. TX PLL Setup....................................................................................................... 58
5.2 Testing TX Output.............................................................................................................. 59
5.2.1. TX Basic Operation Checks.................................................................................. 60
5.3 Receiver Setup and Basic Testing....................................................................................... 61
5.3.1. Top Level Settings................................................................................................ 61
5.3.2. RX LPF & Gain Setting........................................................................................ 62
5.3.3. RX PLL Setup....................................................................................................... 63
5.4 Testing RX Output.............................................................................................................. 65
5.4.1. RX Basic Operation Checks ................................................................................. 65
6 LMS6002D Calibration Procedures....................................................................................... 66
6.1 TX LO Leakage Calibration ............................................................................................... 66
6.2 Transmit I/Q Balance Calibration....................................................................................... 69
6.3 Receiver DC Calibration..................................................................................................... 72
6.4 Calibration Process Summary............................................................................................. 76
7 Appendix A –Saving and Retrieving SPI Test Setups......................................................... 77
7.1 Saving a Setup..................................................................................................................... 77
7.2 Loading *.prj Files.............................................................................................................. 78
8 Appendix B –Test Systems Connections............................................................................... 80
8.1 Basic Setup.......................................................................................................................... 80
8.2 Transmitter Test System Connections................................................................................ 81
8.3 Receive Test System Connections...................................................................................... 81
9 Appendix C –Signal Generator Setup................................................................................... 82
9.1 Agilent MXG Setup............................................................................................................ 82
9.2 Downloading *.wfm Files to the Signal Generator ............................................................ 85
10 Appendix D –Common Receiver Test Issues...................................................................... 88
10.1 Verify the PLL is locked................................................................................................... 88
10.2 Is the Correct LNA Selected............................................................................................. 91
10.3 Is the Correct Rx VGA 2 Gain Selected........................................................................... 91

LMS6002D Quick Starter Manual for Evaluation Board
4 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Table of Figures
Figure 1 Development System Contents......................................................................................... 8
Figure 2 Evaluation board connection descriptions...................................................................... 10
Figure 3 Connector J1 circuit diagram.......................................................................................... 12
Figure 4 Connector J2 circuit diagram.......................................................................................... 13
Figure 5 Connector J3 circuit diagram.......................................................................................... 14
Figure 6 Connector J5 circuit diagram.......................................................................................... 15
Figure 7 Connector J8 circuit diagram.......................................................................................... 16
Figure 8 TXCO locking and SPI option components location (top side)..................................... 20
Figure 9 SPI control resistor component locations....................................................................... 21
Figure 10 Hardware wizard. ......................................................................................................... 23
Figure 11 Hardware wizard. Install driver manually................................................................... 23
Figure 12 Hardware wizard. Choose the USBDriver.inf from the folder..................................... 24
Figure 13 Check in device manager the new communication port............................................... 25
Figure 14 Device Manager. Choose the USBDriver.inf from the folder..................................... 26
Figure 15 Check in device manager the new communication port............................................... 27
Figure 16 Power supply reading................................................................................................... 28
Figure 17 Run ctr_6002dr2 program as an administrator............................................................. 28
Figure 18 GUI communication settings........................................................................................ 29
Figure 19 GUI register test. .......................................................................................................... 29
Figure 20 GUI register test log. .................................................................................................... 30
Figure 21 GUI System window. ................................................................................................... 31
Figure 22 GUI Top Level window................................................................................................ 33
Figure 23 GUI TxPLL + DSM window........................................................................................ 35
Figure 24 PLL mode..................................................................................................................... 36
Figure 25 Output Frequency –GHz.............................................................................................. 36
Figure 26 Calculated Values for Fractional Mode........................................................................ 37
Figure 27 VCO Capacitance......................................................................................................... 37
Figure 28 Current VCO and MUX/DIV selections ...................................................................... 37
Figure 29 VCO Capacitance........................................................................................................ 38
Figure 30 CP Current and Offset.................................................................................................. 38
Figure 31 Frequency versus capacitance calibration table data.................................................... 39
Figure 32 RX PLL + DSM page................................................................................................... 40
Figure 33 PLL Mode..................................................................................................................... 41
Figure 34 Setting receiver frequency - GHz................................................................................. 41
Figure 35 Calculated values for fractional mode.......................................................................... 42
Figure 36 VCO Capacitance......................................................................................................... 42
Figure 37 Current VCO and MUX/DIV selections ...................................................................... 42
Figure 38 VCO Capacitance......................................................................................................... 43
Figure 39 CP Current and Offset .................................................................................................. 43
Figure 40 Frequency vs capacitance calibration table data .......................................................... 43
Figure 41 Tx LPF page ................................................................................................................. 44

LMS6002D Quick Starter Manual for Evaluation Board
5 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Figure 42 Tx RF page ................................................................................................................... 45
Figure 43 Rx LPF page................................................................................................................. 46
Figure 44 Rx VGA2 page............................................................................................................. 48
Figure 45 Rx FE (Front End)........................................................................................................ 49
Figure 46 LNA Control setting..................................................................................................... 50
Figure 47 MIX Control settings.................................................................................................... 51
Figure 48 ADC/DAC page............................................................................................................ 52
Figure 49 DAC enable control timing for TX .............................................................................. 53
Figure 50 ADC enable control timing for RX.............................................................................. 53
Figure 51 ADC/DAC Reference control –default settings .......................................................... 54
Figure 52 ADC Control settings................................................................................................... 54
Figure 53 S/W control for on board ADF4002 –TCXO locking................................................. 55
Figure 54 Top Level Settings........................................................................................................ 57
Figure 55 Setting Tx LPF bandwidth............................................................................................ 57
Figure 56 Tx gain setting and PA selection.................................................................................. 58
Figure 57 Tx PLL setting.............................................................................................................. 59
Figure 58 Basic TX testing using DC offset resulting in LO leakage.......................................... 59
Figure 59 Top Level Settings........................................................................................................ 61
Figure 60 Setting Rx LPF to 7 MHz............................................................................................. 62
Figure 61 Setting Rx VGA2 gain.................................................................................................. 62
Figure 62 Rx LNA and VGA1 settings........................................................................................ 63
Figure 63 Rx PLL settings............................................................................................................ 64
Figure 64 Oscilloscope capture of 1 MHz I & Q Sine wave outputs ........................................... 65
Figure 65 Transmit Output............................................................................................................ 67
Figure 66 System Window. Use Automated Calibration.............................................................. 67
Figure 67 Transmit Output After Calibration............................................................................... 68
Figure 68 Tx RF window.............................................................................................................. 68
Figure 69 Transmit output after calibration.................................................................................. 69
Figure 71 Phase angle calibration................................................................................................. 70
Figure 70 Initial -1 MHz Image Spectrum.................................................................................... 70
Figure 72 Amplitude balance calibration...................................................................................... 71
Figure 73 Transmit EVM performance after calibration.............................................................. 71
Figure 74 Rx FE page................................................................................................................... 72
Figure 76 Rx VGA2 Tab............................................................................................................... 73
Figure 75 Rx LPF tab.................................................................................................................... 73
Figure 77 Receiver LO leakage .................................................................................................... 74
Figure 78 Rx VGA1 DC Offset Adjust in RX FE Tab................................................................ 74
Figure 79 Rx automatic DC calibration result.............................................................................. 75
Figure 80 Save Project feature...................................................................................................... 78
Figure 81 Open project ................................................................................................................. 78
Figure 82 Auto Download feature ................................................................................................ 79
Figure 83 Download Button for Previously Saved Setup............................................................. 79
Figure 84 Test system connections for receive and transmit Testing........................................... 80

LMS6002D Quick Starter Manual for Evaluation Board
6 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Figure 85 Transmitter test setup ................................................................................................... 81
Figure 86 Receiver test setup........................................................................................................ 81
Figure 87 Agilent N5181A/82A MXG Front Panel ..................................................................... 82
Figure 88 Rx PLL VCO capacitance ............................................................................................ 89
Figure 89 No Receive Baseband Output....................................................................................... 89
Figure 90 Non-sinusoidal baseband Output.................................................................................. 90
Figure 91 Sinusoidal Baseband Output......................................................................................... 90

LMS6002D Quick Starter Manual for Evaluation Board
7 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
1
Introduction
The EVB6002-5 is a general purpose evaluation board intended to allow evaluation and testing
of the LMS6002D multi-band, multi-standard RFIC transceiver. It is not intended to act as a
guide to the best layout, decoupling and matching practices when implementing the LMS6002D.
The Lime LMS6002D reference board was developed with best layout, decoupling and matching
practices to deliver optimum LMS6002D RF performance.
This document provides instructions on how to load the evaluation board software ctr6002d onto
a PC, connect the PC to the board, control the LMS6002 via the ctr6002d software and evaluate
its performance. A summary of the main steps to complete this is shown below:
Install PC ctr6002d software.
Connect power supplies and cables to the evaluation board.
Turn on and do SPI and register checks.
Continue using this document to do the following:
Hardware/Board system set up for integration with baseband platforms.
Evaluate the LMS6002D performance.

LMS6002D Quick Starter Manual for Evaluation Board
8 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
2
Development System Contents
Before commencing any work please ensure all of the contents listed below are contained in the
system shipped. See Figure 1 Development System Contents below:
Figure 1 Development System Contents
5V Supply cable for
LMS6002D Board
PC to USB cable
USB software stick

LMS6002D Quick Starter Manual for Evaluation Board
9 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3
Evaluation Board Connections
The following chapter describes in detail EVB connectors, various SPI and clocking options.
3.1 Basic Connections
The analogue differential IQ BB interfaces are connected to transmit and receive paths via the J3
connector for use with test equipment. In addition there are on board differential to single ended
drivers on each of the receiver outputs to accommodate testing with an oscilloscope. An interface
via pin header J5 is provided to the parallel digital interface on the LMS6002D. A baseband
connector via pin header J2 is also provided to be used with third party basebands.
RX IN 1 is tuned from 700 –1500 MHz to cover UMTS bands V and VIII, whilst RX IN 2 is
tuned from 1.5 –2.5 GHz to cover UMTS bands I, II and III. RX IN 3 is connected with a broad
band balun that enables it to cover all bands and require no matching. TX OUT 1 is optimized
for band I, II operation while TX OUT 2 is tuned for broadband operation by the selection of the
matching components.

LMS6002D Quick Starter Manual for Evaluation Board
10 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.2 Board Connections
Figure 2 Evaluation board connection descriptions.
.
The following table describes the high level pin assignment for each connector on the evaluation
board.

LMS6002D Quick Starter Manual for Evaluation Board
11 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Connector
Name
Description
J1
5V Power
Supply
5V supply feed used for standalone operation (not connected to
baseband board). The board is shipped in this mode. To run the
Lime boards using the power supply from a baseband card
connect the links on connector J8 (see connector J8 for details).
J2
Baseband
Board
Connector
The SAM-QSS-RA-150 is a standard connector used to interface
the Lime board directly to a base band board. Please note:
Specific configuration settings, using 0 Ωresistors on the Lime
evaluation board may need to be changed before connection to a
baseband board, see section 3.5.
J3
Analogue IQ
Signals
Analogue IQ signals can be used via this connector. Using the
board in analogue device mode means the baseband TX and RX
signals are connected via this connector. Using the board in
digital device mode, this connector can be used as a test point to
test the ADC & DAC's, analogue section of the transceiver or
purely as a test point to monitor the signal in full operation
mode. The transmit input signals required are differential I and
Q. The Receiver signals have both single ended and differential
outputs. Single ended provided for test purposes.
J4
CLK I/O
Clock input for locking the external clock from test equipment to
the Lime on board clock. J4 connector is used to supply the on
board ADF4002 board clock PLL device with 10 MHz clock, to
lock the EVB reference clock with the measurement setup. Also,
J4 can be used as output or as external reference clock from the
LMS6002D.
J5
Digital I/O
TX 12 Bit &
Select and
RX 12 Bit &
Select
Connector used in standalone mode to input digitally 12 bit
MUXED IQ signal into the transmit chain and receive digitally
12 bit MUXED IQ signal from the Receiver. Please refer to
Lime LMS6002D data sheet for signal information.
J8
Baseband
Supply Feed
Connector used to route power supply connections for use in
standalone mode or using the power supplied from the baseband
board via connector J2. Please refer to section 3.3.5 for details on
configuration settings.
J9
TRX
Duplexer transmitter output 1 connection.
J10
TX OUT 2
Transmitter output TX2, output direct from the chip.
J11
RX IN 1
Receiver input RX1, input direct to chip.
J12
RX IN 2
Receiver input RX2, input direct to chip.

LMS6002D Quick Starter Manual for Evaluation Board
12 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
J13
RX IN 3
Receiver input RX3, input direct to chip.
J14
TX OUT 1
Transmitter output TX1, output direct from the chip.
J16
USB
USB Connector to PC.
Table 1 Evaluation board connectors
3.2.1. J1 –Main Power Supply Connector
Figure 3 Connector J1 circuit diagram.
For standard mode Pin1 or Pin2 is connected to external power supply up to +5V. Pin 3 or Pin4
is connected to ground.

LMS6002D Quick Starter Manual for Evaluation Board
13 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.2.2. J2 –Third Party Baseband Board Connector
The SAM-QSS-RA-150 is a standard connector used by third party baseband providers.
Figure 4 Connector J2 circuit diagram.
The SAM-QSS-RA-150 is a standard
connector used by third party
baseband providers.
The LMS6002D board is shipped
configured to operate using the
connector J5 in standalone mode. The
board has been fitted with several 0
Ω
resistors which act as links to
configure the board in different ways
depending on which baseband board is
being used.

LMS6002D Quick Starter Manual for Evaluation Board
14 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.2.3. J3 –Analogue IQ Signals
Figure 5 Connector J3 circuit diagram
Pins 18 and 20 of J3 connector are single ended
analogue receiver outputs.
Pins 10, 12, 14 and 16 are differential analogue
receiver outputs.
Pins 2, 4, 6 and 8 are differential analogue
transmitter inputs.
All other pins are ground connections.

LMS6002D Quick Starter Manual for Evaluation Board
15 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.2.4. J5 –Digital I/O (I&Q) TX 12 Bit & TXIQSel and RX 12 Bit & RXIQSel
Figure 6 Connector J5 circuit diagram.
The digital I/Q connector is a
digital transmit (TX) and receive
(RX) interface to the ADC/DAC of
the LMS6002D.
The SPI can be controlled within
the J5 connector.
J5 can also be used as a test
connector when the board is
connected to a third party baseband
board.

LMS6002D Quick Starter Manual for Evaluation Board
16 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.2.5. J8 –Sourcing 5V Supply from Baseband Board
Figure 7 Connector J8 circuit diagram
3.2.6. J16 –USB Connector
A type B USB connector is used to connect the PC to the evaluation board. It enables the
LMS6002D to be programmed via the 6002Dr2 test GUI software that comes with the Quick
Starter kit.
3.3 Hardware options: Clocking, TCXO & SPI.
This section describes the configurations and set up procedures for:
TCXO frequency and data clocks distribution (Section 3.4).
TCXO Locking method (Section 3.6)
SPI connection options (Section 3.7).
The default mode the board is shipped with means basic operation using an external digital I/O
source via connector J5 (digital I/O (I&Q) TX 12 Bit & Select and RX 12 Bit & Select). Various
options are available depending on the system configuration required for testing or development
work. The options are summarized below and the following sections will describe the board
modifications required to achieve these configurations. Please note these are hardware options
which are implemented via the following:
Specific components to be fitted or not fitted.
J8 is used to power up board from baseband
platform. Use jumper to power it up as shown
by connecting pins 1 & 2 and/or pins 3 & 4.

LMS6002D Quick Starter Manual for Evaluation Board
17 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.4 TCXO Frequency and Data Clocks Distribution
The LMS6002D device provides a flexible clocking scheme which enables the PLL clock, RX
clock and TX clock to be independently clocked.
The LMS6002D board is shipped with a default mode using the on board 30.72MHz clock
provided. The board can be reconfigured to allow users to provide clocking from external
devices using the two connectors J2 & J5. The most popular configurations are listed in the table
below.
Option 1
DIO default
mode
Description
PLL clock
30.72MHz TCXO
LMS6002D device PLL is fed using on board 30.72MHz
TCXO.
Rx data clock
30.72MHz output
RX data clock is provided by Lime evaluation board and is fed
to connectors J2 & J5 as outputs to enable a digital I/O card to
capture samples.
Tx data clock
30.72MHz output
TX data clock is provided by Lime evaluation board and is fed
to connectors J2 & J5 as outputs to enable a digital I/O card to
send samples.
Option 2
Description
PLL clock
30.72MHz
(TCXO ÷ 2)
LMS6002D device PLL is fed using on board TCXO 61.44MHz
clock ÷ 2.
Rx data clock
61.44MHz output
RX data clock is provided by Lime evaluation board and is fed
to connectors J2 & J5 as outputs to enable a digital I/O card to
capture samples.
Tx data clock
30.72MHz output
(TCXO ÷ 2)
TX data clock is provided by Lime evaluation board and is fed
to connectors J2 & J5 as outputs to enable a digital I/O card to
send samples.
Option 3
Description
PLL clock
30.72MHz TCXO
LMS6002D device PLL is fed using on board 30.72MHz
TCXO.
Rx data clock
30.72MHz output
RX data clock is provided by digital I/O card and is fed to
connectors J2 & J5 as inputs to enable Lime evaluation board to
capture samples.
Tx data clock
30.72MHz output
TX data clock is provided by digital I/O card and is fed to
connectors J2 & J5 as inputs to enable Lime evaluation board to
send samples.
Table 2 Baseband Clock Configurations

LMS6002D Quick Starter Manual for Evaluation Board
18 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
The board is shipped in the default mode (Option 1). To use other options please make sure that
hardware changes were applied as in the table below. Please note that NF denotes component is
not fitted.
3.5 Different Clocking Schemes
Different Clocking Schemes
Option 1
Option 2
Option 3
DIO default mode
PLL clock
30.72 MHz TCXO
30.72 MHz TCXO
30.72 MHz TCXO
Rx data clock
30.72 MHz output
61.44 MHz output
Input from digital
I/O card
Tx data clock
30.72 MHz output
30.72 MHz output
Input from digital
I/O card
Evaluation
Board
Component fit
option 1
Component fit
option 2
Component fit
option 3
R81
NF
NF
0R
R80
NF
0R
0R
R104
NF
NF
NF
R105
0R
0R
NF
R106
0R
NF
NF
R107
68R
NF
68R
R111
NF
0R
NF
R113
0R
0R
0R
R114
0R
NF
NF
R116
0R
0R
NF
R117
0R
0R
0R
R110
NF
0R
NF
R39
NF
NF
NF
R40
NF
NF
NF
R58
NF
NF
NF
U4
NF
NC7SV74
NF
R147
NF
0R
NF
R148
0R
0R
0R
X1
E5280LFT (30.72
MHz)
NF
E5280LFT (30.72)
X2
NF
E5405 (61.44)
NF
Table 3 Baseband Clocking Schemes

LMS6002D Quick Starter Manual for Evaluation Board
19 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
3.6 TCXO Locking Options
The LMS6002D board provides different options to lock the TCXO to base band or test systems.
The LMS6002D board provides three options for clock locking:
Option 1 –Lock using on board PLL device ADF4002. This is the default mode the board is
shipped with to enable the board to be locked to test equipment using an external 10MHz clock
provided by connector J4, acting as an input.
Option 2 –Manual potentiometer - RT1. RT1 shown in figure 8 allows the TCXO to be
manually tuned by altering the on board potentiometer. J4 becomes an output for the reference
clock.
Option 3 –External control via the baseband connector J2. Signal VCTRL provided by baseband
board.
The board is shipped in the default mode (Option 1). To use other options please use component
changes as in table below. Please note that NF denotes component is not fitted.
TCXO Locking method
Options
Option 1)
DEFAULT MODE
On Board PLL
Clock (ADF4002)
Option 2)
Manual
Potentiometer
Option 3)
External VCTRL
Description
Lock to 10MHz
input from test
equipment
J4=10MHz ref in
Manual Vtune
J4=TCXO out
Use external DC
voltage (from BB J2
connector VCTRL)
to control TCXO
J4=TCXO out
Component
R39
NF
0R
NF
R40
NF
NF
0R
R58
NF
NF
NF
R61
NF
NF
0R
R62
NF
NF
0R
R104
NF
0R
0R
Table 4 TCXO Locking Method
Components R39, R40 and R61 are located on the top of the interface board as shown in figure
8.

LMS6002D Quick Starter Manual for Evaluation Board
20 | P a g e
© Copyright Lime Microsystems
Rev: 2.2
Last modified: 03/05/2012
Figure 8 TXCO locking and SPI option components location (top side)
3.7 SPI Control Options
The LMS6002D board can be controlled by using the SPI connectors via J2, J6 or J16. Please
note only one SPI master can be connected to the bus at any time, hence these are mutually
exclusive.
The only option requiring hardware changes is Option 2 where the baseband connector J2 is used
to connect to a baseband board (for the TX/RX signals) when its own SPI bus and control of the
SPI by the Lime SW is desired (rather than the BB SPI). J2 must be removed from the EVB SPI
bus so that the control of the SPI is maintained by a PC running the Lime software. This is
required to ensure that the USB SPI connection via J16 does not conflict with the baseband SPI
connections via J2. Please note that NF denotes component is not fitted.