LSI DMN-8600 User manual

®
DMN-8600
DVD Recorder
System Processor
TECHNICAL
MANUAL
July 2002
Preliminary-3
LSI Logic Confidential

LSI Logic Confidential
ii Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using
production parts.
Document DB14-000198-02, Third Edition (July 2002)
This document describes the LSI Logic DMN-8600 and will remain the official ref-
erence source for all revisions/releases of this product until rescinded by an
update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, DoMiNo, and ZiVA are trademarks or
registered trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.
GS
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html

DMN-8600 DVD Recorder System Processor iii
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Preface
This book is the primary reference and technical manual for the
DMN-8600 advanced, scalable DVD recorder processor. It contains a
complete functional description for the DMN-8600 and includes complete
physical and electrical specifications for the DMN-8600.
Audience
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are
•Engineers and managers who are evaluating the processor for
possible use in a system
•Engineers who are designing the processor into a system
Organization
This document has the following chapters and appendixes:
•Chapter 1, Overview, defines DMN-8600 features and introduces its
main applications.
•Chapter 2, Application Example, describes the common user
interface shared by all DMN-8600 applications and provides a listing
of components needed to complete the design.
•Chapter 3, Internal Architecture, gives an overview of the main
modules and their external interfaces.
•Chapter 4, Functional Description, provides an extended
description to the main modules and their external interfaces.
•Chapter 5, Programmability (C-Ware), provides an overview of how
the DMN-8600 is programmed.

LSI Logic Confidential
iv Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
•Chapter 6, Signal Descriptions, describes signals within their
respective functional groups.
•Chapter 7, Memory Mapping, describes the addresses for different
configurations, including access to SDRAM and internal registers via
the Control Bus (CBus).
•Chapter 8, Host Slave Interface, gives an extended description to
the different configurations and features of the Host slave interface;
includes registers.
•Chapter 9, Secondary Bitstream Interface, gives an extended
description to the Secondary Bitstream interface; includes registers.
•Chapter 10, Host Async Master Interface, gives an extended
description to the different configurations and features of the Host
Async master interface; includes registers.
•Chapter 11, Video Interface, gives an extended description to the
video interface; includes registers.
•Chapter 12, Audio Interface, gives an extended description to the
audio interface; includes registers.
•Chapter 13, SDRAM Interface, gives an extended description to the
SDRAM interface; includes registers.
•Chapter 14, Bitstream I/O (Storage) Port, gives an extended
description to the bitstream I/O interface; includes registers.
•Chapter 15, Serial I/O Port, gives an extended description to the
serial I/O interface; includes registers.
•Chapter 16, Clock Control and Power Management, describes
clock PLLs and power modes; includes registers.
•Chapter 17, JTAG Boundary Scan, describes JTAG boundary scan
interface in accordance with IEEE 1149.1; includes cell listing.
•Chapter 18, Specifications, describes electrical characteristics as
well as AC timing; includes pin list alphabetized according to both pin
name and pin bondout location.
•Chapter A, Register Listing, is an index of the DMN-8600 registers.

LSI Logic Confidential
Preface v
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Related Publications
DoMiNo Full Feature Network Media Processor Family Preliminary
Technical Manual, Document number DB14-000197-00
DoMiNo Dual Stream Network Media Processor Family Advance Product
Datasheet, Document number TD10-1016, Rev 0.10
DMN-8600 Applications User Guide, Document number TD10-1032
(Pre-Advance)
DMN-8600 DVD Recorder System Processor Programming Guide,
Volume 1, Document number DB15-000233-01
Volume 2, Document number DB15-000246-00
DMN-8100 Advanced Multiformat A/V Processor for Video Peripheral
Applications Technical Manual, Document number DB14-000217-01
Galileo CE Development Board Preliminary User’s Guide, Document
number DB15-000229-01
Galileo Light (Galileo LT) Development Board Advance User’s Guide,
Document number DB15-000240-00
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW are marked with an overbar symbol.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

LSI Logic Confidential
vi Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 1 Revision History
Date Part No. Description
February 20, 2001 91-E5SD-SS-ADV-1 Initial 308 BGA datasheet with signal
descriptions.
May 3, 2001 TD10-1017, Rev. 0.10 Pin numbers assigned to signals and part pro-
ductized as DMN-8600.
August 15, 2001 TD10-1017, Rev. 0.20 Added register, extended interface descriptions,
and AC/DC information.
August 30, 2001 TD10-1017, Rev. 0.21 Special Edition
September 18, 2001 TD10-1017, Rev. 0.22 Special Edition - 2nd Edition
October 2, 2001 DB14-000198-00 Preliminary Edition
January 31, 2002 DB14-000198-01 Preliminary-2 Edition. Chapter 15 expanded,
etc.
July 31, 2002 DB14-000198-02 Preliminary-3 Edition. Assorted changes made.

DMN-8600 DVD Recorder System Processor vii
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Contents
Chapter 1
Overview
Chapter 2
Application Example
Chapter 3
Internal Architecture
Chapter 4
Functional Description
4.1 RISC Engine 4-1
4.2 Video Processing 4-1
4.2.1 Motion Estimation Coprocessor 4-2
4.2.2 Video DSP Coprocessor 4-2
4.3 Audio Processing 4-2
4.4 Interfaces and I/O 4-3
4.4.1 Host Interface 4-4
4.4.2 Bitstream/Storage Interface 4-5
4.4.3 IEEE 1394 Interface 4-6
4.4.4 Video Interface 4-6
4.4.5 Audio Interface 4-7
4.4.6 SDRAM Interface 4-7
4.4.7 Serial I/O Interface 4-8
4.4.8 JTAG Interface (Test Access Port) 4-9
4.5 Graphics Accelerator 4-9

LSI Logic Confidential
viii Contents
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Chapter 5
Programmability
(C-Ware)
Chapter 6
Signal Descriptions
Chapter 7
Memory Mapping 7.1 Host Interface Address Mapping 7-1
7.2 SPARC Processor Address Mapping 7-2
7.2.1 In System with an External Master Processor 7-2
7.2.2 In System with No External Master Processor 7-3
7.3 Control Bus Address Mapping 7-4
Chapter 8
Host Slave Interface
8.1 Async Slave Interface with Host DMA 8-4
8.2 Async Slave Interface Transfer Modes 8-4
8.2.1 Transfer Mode A 8-4
8.2.2 Transfer Mode B 8-5
8.3 Async Slave WRITE and READ Protocols 8-5
8.3.1 I-Mode WRITE and READ Operations 8-5
8.3.2 I-Mode Incoming Transfers 8-5
8.3.3 I-Mode Outgoing Transfers 8-6
8.3.4 M-Mode WRITE and READ Operations 8-7
8.3.5 M-Mode Incoming Transfers 8-7
8.3.6 M-Mode Outgoing Transfers 8-8
8.4 Host DMA Read/Write Protocol 8-9
8.4.1 Incoming Transfers to DMN-8600 Device 8-10
8.4.2 Outgoing Transfers from DMN-8600 Device 8-10
8.5 Power Management 8-10
8.6 Host Interface Registers 8-11
8.6.1 Host Interface Control Register 8-12
8.6.2 Version Register 8-16
8.6.3 Host DMA Data Register 8-17

LSI Logic Confidential
Contents ix
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
8.6.4 Host Data Registers 8-18
8.6.5 Host Address Register 8-20
8.7 Host DMA Registers 8-22
8.7.1 Host DMA Configuration Register (CBus Address:
0x60060) 8-22
8.7.2 Host DMA NextAddress Register (CBus Address:
0x60064) 8-24
8.7.3 Host DMA StopAddress Register (CBus Address:
0x60068) 8-24
8.7.4 Host DMA BaseAddress and LimitAddress
Registers (CBus Address: 0x6006C and 0x60070) 8-25
8.8 Master DMA Registers 8-25
8.8.1 Master DMA Configuration Register
(Cbus Addr: 0x6F000) 8-25
8.8.2 Master DMA External Address Register
(Cbus: 0x6F014) 8-27
8.8.3 Master DMA NextAddress Register
(Cbus Addr: 0x6F004) 8-28
8.8.4 Master DMA StopAddress Register
(Cbus Addr: 0x6F008) 8-28
8.8.5 Master DMA BaseAddress and LimitAddress
Registers (Cbus Address: 0x6F00C and 0x6F010) 8-28
Chapter 9
Secondary Bitstream Interface
9.1 WRREQ = 0 9-3
9.1.1 Bitstream Output – Outgoing Transfers (BRSD = 1) 9-3
9.1.2 Bitstream Input – Incoming Transfers (BSRD = 0) 9-4
9.2 WRREQ = 1 9-5
9.3 FRAME Pin Transfers 9-5
9.3.1 Outgoing FRAME Transfers 9-5
9.3.2 Incoming FRAME Transfers 9-6
9.4 FIFO and Buffer Operation 9-7
9.5 Secondary Bitstream Interface Registers 9-8
9.5.1 Secondary Bitstream Configuration Register 9-8
9.5.2 Secondary NextAddress Register (CBus Addr:
0x080824) 9-11
9.5.3 Secondary Stop Address Register

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x Contents
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
(Cbus Addr: 0x080828) 9-11
9.5.4 Secondary Base Address and Limit Address
Registers (CBus Addr: 0x08082C and 0x080830) 9-12
9.5.5 Secpacksize Register (CBus Addr: 0x080834) 9-12
9.5.6 SecPacketDelay Register (CBus Addr: 0x080838) 9-12
Chapter 10
Host Async Master Interface
10.1 No Master 10-1
10.2 Host (Slave) plus Limited Master 10-2
10.3 Master Replaces Slave 10-2
10.4 Cycle Types 10-3
10.4.1 Data Strobe Mode 10-3
10.4.2 Transfer Acknowledge Mode 10-5
10.4.3 Timing Parameters 10-7
10.4.4 Burst Transactions 10-8
10.4.5 Device-Paced Transfers 10-8
10.4.6 Multiplexed Address Cycles 10-10
10.5 Chip Select Configuration Registers 10-11
10.6 Interrupt/GPIO Configuration and Value Registers 10-15
10.7 Async Master Status/Time-Out Register 10-17
10.8 Async Master SPARC Error Address Register 10-19
Chapter 11
Video Interface 11.1 Video Output Format 11-4
11.2 Video Operation 11-5
11.2.1 Video Streams 11-5
11.2.2 ITU-R 656 Operation 11-6
11.3 Video Control Register 11-6
Chapter 12
Audio Interface 12.1 Data, Serial Clocks and FSYNC 12-2
12.1.1 MCLK 12-2
12.1.2 IEC-958 Encoder 12-2
12.2 Audio Input Control Register 12-3