LSI DMN-8600 User manual

®
DMN-8600
DVD Recorder
System Processor
TECHNICAL
MANUAL
July 2002
Preliminary-3
LSI Logic Confidential

LSI Logic Confidential
ii Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using
production parts.
Document DB14-000198-02, Third Edition (July 2002)
This document describes the LSI Logic DMN-8600 and will remain the official ref-
erence source for all revisions/releases of this product until rescinded by an
update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, DoMiNo, and ZiVA are trademarks or
registered trademarks of LSI Logic Corporation. All other brand and product
names may be trademarks of their respective companies.
GS
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html

DMN-8600 DVD Recorder System Processor iii
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Preface
This book is the primary reference and technical manual for the
DMN-8600 advanced, scalable DVD recorder processor. It contains a
complete functional description for the DMN-8600 and includes complete
physical and electrical specifications for the DMN-8600.
Audience
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are
•Engineers and managers who are evaluating the processor for
possible use in a system
•Engineers who are designing the processor into a system
Organization
This document has the following chapters and appendixes:
•Chapter 1, Overview, defines DMN-8600 features and introduces its
main applications.
•Chapter 2, Application Example, describes the common user
interface shared by all DMN-8600 applications and provides a listing
of components needed to complete the design.
•Chapter 3, Internal Architecture, gives an overview of the main
modules and their external interfaces.
•Chapter 4, Functional Description, provides an extended
description to the main modules and their external interfaces.
•Chapter 5, Programmability (C-Ware), provides an overview of how
the DMN-8600 is programmed.

LSI Logic Confidential
iv Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
•Chapter 6, Signal Descriptions, describes signals within their
respective functional groups.
•Chapter 7, Memory Mapping, describes the addresses for different
configurations, including access to SDRAM and internal registers via
the Control Bus (CBus).
•Chapter 8, Host Slave Interface, gives an extended description to
the different configurations and features of the Host slave interface;
includes registers.
•Chapter 9, Secondary Bitstream Interface, gives an extended
description to the Secondary Bitstream interface; includes registers.
•Chapter 10, Host Async Master Interface, gives an extended
description to the different configurations and features of the Host
Async master interface; includes registers.
•Chapter 11, Video Interface, gives an extended description to the
video interface; includes registers.
•Chapter 12, Audio Interface, gives an extended description to the
audio interface; includes registers.
•Chapter 13, SDRAM Interface, gives an extended description to the
SDRAM interface; includes registers.
•Chapter 14, Bitstream I/O (Storage) Port, gives an extended
description to the bitstream I/O interface; includes registers.
•Chapter 15, Serial I/O Port, gives an extended description to the
serial I/O interface; includes registers.
•Chapter 16, Clock Control and Power Management, describes
clock PLLs and power modes; includes registers.
•Chapter 17, JTAG Boundary Scan, describes JTAG boundary scan
interface in accordance with IEEE 1149.1; includes cell listing.
•Chapter 18, Specifications, describes electrical characteristics as
well as AC timing; includes pin list alphabetized according to both pin
name and pin bondout location.
•Chapter A, Register Listing, is an index of the DMN-8600 registers.

LSI Logic Confidential
Preface v
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Related Publications
DoMiNo Full Feature Network Media Processor Family Preliminary
Technical Manual, Document number DB14-000197-00
DoMiNo Dual Stream Network Media Processor Family Advance Product
Datasheet, Document number TD10-1016, Rev 0.10
DMN-8600 Applications User Guide, Document number TD10-1032
(Pre-Advance)
DMN-8600 DVD Recorder System Processor Programming Guide,
Volume 1, Document number DB15-000233-01
Volume 2, Document number DB15-000246-00
DMN-8100 Advanced Multiformat A/V Processor for Video Peripheral
Applications Technical Manual, Document number DB14-000217-01
Galileo CE Development Board Preliminary User’s Guide, Document
number DB15-000229-01
Galileo Light (Galileo LT) Development Board Advance User’s Guide,
Document number DB15-000240-00
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW are marked with an overbar symbol.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

LSI Logic Confidential
vi Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Table 1 Revision History
Date Part No. Description
February 20, 2001 91-E5SD-SS-ADV-1 Initial 308 BGA datasheet with signal
descriptions.
May 3, 2001 TD10-1017, Rev. 0.10 Pin numbers assigned to signals and part pro-
ductized as DMN-8600.
August 15, 2001 TD10-1017, Rev. 0.20 Added register, extended interface descriptions,
and AC/DC information.
August 30, 2001 TD10-1017, Rev. 0.21 Special Edition
September 18, 2001 TD10-1017, Rev. 0.22 Special Edition - 2nd Edition
October 2, 2001 DB14-000198-00 Preliminary Edition
January 31, 2002 DB14-000198-01 Preliminary-2 Edition. Chapter 15 expanded,
etc.
July 31, 2002 DB14-000198-02 Preliminary-3 Edition. Assorted changes made.

DMN-8600 DVD Recorder System Processor vii
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
LSI Logic Confidential
Contents
Chapter 1
Overview
Chapter 2
Application Example
Chapter 3
Internal Architecture
Chapter 4
Functional Description
4.1 RISC Engine 4-1
4.2 Video Processing 4-1
4.2.1 Motion Estimation Coprocessor 4-2
4.2.2 Video DSP Coprocessor 4-2
4.3 Audio Processing 4-2
4.4 Interfaces and I/O 4-3
4.4.1 Host Interface 4-4
4.4.2 Bitstream/Storage Interface 4-5
4.4.3 IEEE 1394 Interface 4-6
4.4.4 Video Interface 4-6
4.4.5 Audio Interface 4-7
4.4.6 SDRAM Interface 4-7
4.4.7 Serial I/O Interface 4-8
4.4.8 JTAG Interface (Test Access Port) 4-9
4.5 Graphics Accelerator 4-9

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Chapter 5
Programmability
(C-Ware)
Chapter 6
Signal Descriptions
Chapter 7
Memory Mapping 7.1 Host Interface Address Mapping 7-1
7.2 SPARC Processor Address Mapping 7-2
7.2.1 In System with an External Master Processor 7-2
7.2.2 In System with No External Master Processor 7-3
7.3 Control Bus Address Mapping 7-4
Chapter 8
Host Slave Interface
8.1 Async Slave Interface with Host DMA 8-4
8.2 Async Slave Interface Transfer Modes 8-4
8.2.1 Transfer Mode A 8-4
8.2.2 Transfer Mode B 8-5
8.3 Async Slave WRITE and READ Protocols 8-5
8.3.1 I-Mode WRITE and READ Operations 8-5
8.3.2 I-Mode Incoming Transfers 8-5
8.3.3 I-Mode Outgoing Transfers 8-6
8.3.4 M-Mode WRITE and READ Operations 8-7
8.3.5 M-Mode Incoming Transfers 8-7
8.3.6 M-Mode Outgoing Transfers 8-8
8.4 Host DMA Read/Write Protocol 8-9
8.4.1 Incoming Transfers to DMN-8600 Device 8-10
8.4.2 Outgoing Transfers from DMN-8600 Device 8-10
8.5 Power Management 8-10
8.6 Host Interface Registers 8-11
8.6.1 Host Interface Control Register 8-12
8.6.2 Version Register 8-16
8.6.3 Host DMA Data Register 8-17

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8.6.4 Host Data Registers 8-18
8.6.5 Host Address Register 8-20
8.7 Host DMA Registers 8-22
8.7.1 Host DMA Configuration Register (CBus Address:
0x60060) 8-22
8.7.2 Host DMA NextAddress Register (CBus Address:
0x60064) 8-24
8.7.3 Host DMA StopAddress Register (CBus Address:
0x60068) 8-24
8.7.4 Host DMA BaseAddress and LimitAddress
Registers (CBus Address: 0x6006C and 0x60070) 8-25
8.8 Master DMA Registers 8-25
8.8.1 Master DMA Configuration Register
(Cbus Addr: 0x6F000) 8-25
8.8.2 Master DMA External Address Register
(Cbus: 0x6F014) 8-27
8.8.3 Master DMA NextAddress Register
(Cbus Addr: 0x6F004) 8-28
8.8.4 Master DMA StopAddress Register
(Cbus Addr: 0x6F008) 8-28
8.8.5 Master DMA BaseAddress and LimitAddress
Registers (Cbus Address: 0x6F00C and 0x6F010) 8-28
Chapter 9
Secondary Bitstream Interface
9.1 WRREQ = 0 9-3
9.1.1 Bitstream Output – Outgoing Transfers (BRSD = 1) 9-3
9.1.2 Bitstream Input – Incoming Transfers (BSRD = 0) 9-4
9.2 WRREQ = 1 9-5
9.3 FRAME Pin Transfers 9-5
9.3.1 Outgoing FRAME Transfers 9-5
9.3.2 Incoming FRAME Transfers 9-6
9.4 FIFO and Buffer Operation 9-7
9.5 Secondary Bitstream Interface Registers 9-8
9.5.1 Secondary Bitstream Configuration Register 9-8
9.5.2 Secondary NextAddress Register (CBus Addr:
0x080824) 9-11
9.5.3 Secondary Stop Address Register

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(Cbus Addr: 0x080828) 9-11
9.5.4 Secondary Base Address and Limit Address
Registers (CBus Addr: 0x08082C and 0x080830) 9-12
9.5.5 Secpacksize Register (CBus Addr: 0x080834) 9-12
9.5.6 SecPacketDelay Register (CBus Addr: 0x080838) 9-12
Chapter 10
Host Async Master Interface
10.1 No Master 10-1
10.2 Host (Slave) plus Limited Master 10-2
10.3 Master Replaces Slave 10-2
10.4 Cycle Types 10-3
10.4.1 Data Strobe Mode 10-3
10.4.2 Transfer Acknowledge Mode 10-5
10.4.3 Timing Parameters 10-7
10.4.4 Burst Transactions 10-8
10.4.5 Device-Paced Transfers 10-8
10.4.6 Multiplexed Address Cycles 10-10
10.5 Chip Select Configuration Registers 10-11
10.6 Interrupt/GPIO Configuration and Value Registers 10-15
10.7 Async Master Status/Time-Out Register 10-17
10.8 Async Master SPARC Error Address Register 10-19
Chapter 11
Video Interface 11.1 Video Output Format 11-4
11.2 Video Operation 11-5
11.2.1 Video Streams 11-5
11.2.2 ITU-R 656 Operation 11-6
11.3 Video Control Register 11-6
Chapter 12
Audio Interface 12.1 Data, Serial Clocks and FSYNC 12-2
12.1.1 MCLK 12-2
12.1.2 IEC-958 Encoder 12-2
12.2 Audio Input Control Register 12-3

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12.3 Audio Output Control Register 12-8
12.4 Audio Status Registers 12-15
12.5 Audio Address and Length Registers 12-18
12.5.1 Audio Input DRAM Address Register 12-18
12.5.2 Audio Input Length Register 12-19
12.5.3 Audio Output DRAM Address Register 12-19
12.5.4 IEC958 Output DRAM Address Register 12-19
12.5.5 Audio Output Length Register 12-20
12.6 Audio Frame Formats 12-20
12.6.1 FRFORM 0 12-21
12.6.2 FRFORM 1 12-22
12.6.3 FRFORM 2 12-23
12.6.4 FRFORM 3 12-23
12.6.5 FRFORM 4 12-24
12.6.6 FRFORM 5 12-24
12.6.7 FRFORM 6 12-25
12.6.8 FRFORM 7 12-26
Chapter 13
SDRAM Interface 13.1 DRAM Address Map 13-6
13.2 DRAM Address Field Description 13-6
13.3 Supported Number of Simultaneous Banks 13-7
13.4 SDRAM Initialization 13-8
13.5 SDRAM Refresh 13-9
13.6 External SDRAM Configuration Register 13-10
13.7 SDRAM Control and Clock Control Registers 13-13
13.8 SDRAM Arbitration and Throttle Registers 13-14
13.9 SDRAM Timing 13-17
Chapter 14
Bitstream I/O (Storage) Port
14.1 ATAPI Interface 14-2
14.1.1 Read Cycle 14-2
14.1.2 Write Cycle 14-3
14.1.3 DMA Operation 14-3
14.2 SD Interface 14-7

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14.3 CD Interface 14-8
14.3.1 SD/CD Configuration Register 14-9
14.3.2 Valid Signal Formats 14-12
14.4 1394 Controller 14-14
Chapter 15
Serial I/O Port 15.1 SIO IR (Infrared) Interface 15-1
15.1.1 IR Transmit Functionality 15-3
15.1.2 IR Receive Functionality 15-4
15.1.3 IR Programming Guidelines 15-6
15.2 SIO SPI (Serial Peripheral Interface) 15-7
15.2.1 SPI Interface Signals 15-9
15.2.2 SPI Interface: Protocol Description 15-10
15.2.3 SPI Clocking 15-11
15.2.4 SPI Transfer: Host-Polled Mode 15-12
15.2.5 SPI Programming Examples 15-12
15.2.6 Other Applications 15-15
15.2.7 SPI Programming Guidelines 15-15
15.3 IDC Interface 15-16
15.4 SIO UART Interface 15-18
15.4.1 UART Data Frame 15-18
15.4.2 Baud Rate Generator 15-18
15.5 SIO Register Descriptions 15-19
15.5.1 Interrupt Hierarchy 15-20
15.5.2 SIO Top Level & DMA Engine Registers 15-21
15.5.3 SIO IDC Registers 15-32
15.5.4 SIO IR1 / IR2 Registers 15-49
15.5.5 SIO SPI Registers 15-63
15.5.6 SIO UART1/UART2 Registers 15-80
15.5.7 Reserved Registers (SIO UART2) 15-104
Chapter 16
Clock Control and Power Management
16.1 Clock and Power Registers 16-3
16.2 Main PLL Power Down and Wake-Up Sequence 16-12

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Chapter 17
JTAG Boundary Scan
17.1 JTAG Instruction Set 17-2
17.2 Boundary Scan Chain Cells 17-2
Chapter 18
Specifications 18.1 Electrical Specifications 18-1
18.2 AC Timing 18-4
18.2.1 Miscellaneous Timing 18-5
18.2.2 Host Master Timing 18-6
18.2.3 Host Slave Timing 18-14
18.2.4 SDRAM Interface AC Timing 18-20
18.2.5 CD Interface Timing 18-26
18.2.6 IDC Interface Timing 18-27
18.2.7 Audio Timing 18-30
18.2.8 UART Interface Timing 18-31
18.2.9 Video Interface Timing 18-32
18.2.10 IR Interface Timing 18-35
18.2.11 JTAG Interface Signal Timing 18-36
18.2.12 ATAPI AC Timing 18-38
18.2.13 SD Interface Timing 18-41
18.2.14 SPI Interface Timing 18-43
18.2.15 1394 Timing 18-44
18.2.16 SBP Interface Timing 18-47
18.3 Pin Description 18-50
18.4 Package Mechanical Specifications 18-70
18.4.1 Package Dimensions 18-70
18.4.2 Recommended Manufacturing Conditions 18-72
Chapter A
Register Listing
Customer Feedback

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Figures 2.1 System Block Diagram for a DMN-8600-Based Advanced
DVD Recorder Appliance 2-1
3.1 DMN-8600 Internal Architecture Diagram 3-2
4.1 DMN-8600 System I/O Diagram 4-3
4.2 DMN-8600 Bitstream Interface 4-6
5.1 C-Ware Architecture 5-1
6.1 DMN-8600 System Interfaces 6-2
7.1 Host Interface Address Mapping 7-2
7.2 SPARC Processor Memory Map with External Host
Processor 7-3
7.3 SPARC Processor Memory Map without External Host
Processor 7-4
8.1 Host Interface (Showing Slave Pins Only) 8-3
8.2 I-Mode WRITE 8-6
8.3 I-Mode READ 8-7
8.4 M-Mode WRITE 8-8
8.5 M-Mode READ 8-9
8.6 Host DMA Target Transfers 8-9
9.1 Secondary Bitstream Port (SBP) 9-2
9.2 Bitstream Port Outgoing Transfers with WRREQ = 0,
POL = 1 and BSRD = 1 9-3
9.3 Bitstream Port Incoming Transfers with WRREQ = 0,
POL = 1 and BSRD = 0 9-4
9.4 Outgoing FRAME Transfers 9-5
9.5 Incoming FRAME Transfers 9-6
9.6 Circular Buffer 9-7
10.1 Async Master Read and Write Cycles 10-4
10.2 Self-Paced Async Master Cycles with M_WAIT 10-6
10.3 Async Master Device-paced Transfer 10-9
10.4 Multiplexed Master Cycle 10-11
11.1 Video Input Channel Data Flow 11-1
11.2 Video Output Channel Data Flow 11-3
11.3 Output Field/Frame Format 11-5
11.4 Single Video Stream 11-6
11.5 ITU-R BT.656 Timing 11-6
12.1 Location of FRFORM 1 Status 12-22

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12.2 FRFORM 0 Audio Frame Definition 12-22
12.3 FRFORM 1 Audio Frame Output Definition 12-23
12.4 FRFORM 1 Audio Frame Input Definition 12-23
12.5 FRFORM 3 Audio Frame Definition 12-24
12.6 FRFORM 4 Audio Frame Definition 12-24
12.7 FRFORM 5 Audio Frame Definition (Right Justified) 12-25
12.8 FRFORM 6 Audio Frame Definition (Right Justified) 12-25
12.9 FRFORM 7 Audio Frame Definition (Right Justified) 12-26
13.1 16-Bit DRAM Connections Using DDR SDRAM 13-3
13.2 16-Bit DRAM Connections Using SDR SDRAM 13-4
13.3 32-Bit DRAM Connections Using SDR SRAM 13-5
13.4 32-bit DRAM Connections using DDR SRAM 13-6
14.1 ATAPI Read and Write Cycle 14-3
14.2 ATAPI DMA Read/Write Cycle 14-4
14.3 SD Interface Cycle 14-8
14.4 CD Interface Input Signal Formats 14-13
15.1 IR Interface Protocol 15-2
15.2 NCR IR Protocol 15-5
15.3 Philips RC-5 Protocol 15-6
15.4 SPI Block Diagram 15-8
15.5 32-Bit SPI Data Transfer Format 15-10
15.6 Inter-Byte Timing Relationship 15-10
15.7 IDC Interface Data Transfer Protocol 15-17
15.8 UART Data Frame 15-18
15.9 Connections Between INTR_STATUS_ADDR and
SIO_DMA_IRQ Registers 15-29
15.10 SPI Inter-Byte Blanking 15-66
16.1 Clock and Power Block Diagram 16-2
18.1 Timing Diagram for CLKI and CLKO 18-5
18.2 General-Purpose I/O Timing 18-6
18.3 Self-Paced Async Master Read Cycle in SRAM Mode 18-6
18.4 Self-Paced Async Master Write Cycle in SRAM Mode 18-7
18.5 Self-Paced Async Master Read Cycle in 68K Mode 18-7
18.6 Self-Paced Async Master Write Cycle in 68K Mode 18-8
18.7 Device-Paced Async Master Read Cycle in 68K Mode 18-8
18.8 Device-Paced Async Master Write Cycle in 68K Mode 18-9
18.9 Device-Paced Async Master Read Cycle in SRAM Mode 18-10
18.10 Device-Paced Async Master Write Cycle in SRAM Mode 18-11

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18.11 Multiplexed Address Async Master Read Cycle 18-12
18.12 I-Mode Write AC Timing Diagram 18-15
18.13 I-Mode Read AC Timing Diagram 18-16
18.14 M-Mode Write AC Timing Diagram 18-18
18.15 M-Mode Read AC Timing Diagram 18-19
18.16 SDRAM Clock LOW and HIGH Period Definition 18-21
18.17 DMN-8600 Writing to SDRAM in SDR Mode 18-22
18.18 DMN-8600 Reading from SDRAM in SDR Mode 18-23
18.19 DMN-8600 Write to SDRAM in DDR Mode 18-24
18.20 DMN-8600 Read from SDRAM in DDR Mode 18-25
18.21 CD Interface Timing 18-26
18.22 IDC Interface AC Slave Timing 18-27
18.23 IDC Interface AC Master Timing 18-29
18.24 Audio Input/Output AC Timing 18-30
18.25 UART Interface AC Timing 18-31
18.26 AC Timing for Video Input Stream at VI_CLK[0] 18-32
18.27 AC Timing of Video Output at VO_CLK 18-34
18.28 IR Interface Timing 18-35
18.29 JTAG Interface Timing Diagram 18-37
18.30 ATAPI DMA AC Timing 18-38
18.31 ATAPI PIO Read and Write Timing 18-40
18.32 SD Interface Timing 18-42
18.33 32-Bit SPI Data Transfer Format 18-43
18.34 SBP Signal Level Parameters 18-44
18.35 1394 PHY to Link Transfer Waveform at the PHY 18-45
18.36 1394 Link to PHY Transfer Waveform at the PHY 18-45
18.37 1394 Link to PHY Transfer Waveform at the Link 18-46
18.38 1394 PHY to Link Transfer Waveform at the Link 18-46
18.39 SBP Clock Timing 18-47
18.40 SBP Incoming Transfer (POL = 1, WRREQ = 0) 18-47
18.41 SBP Outgoing Transfer (POL = 1, WRREQ = 0) 18-48
18.42 SBP Incoming Transfer (POL = 0,WRREQ = 0) 18-48
18.43 SBP Outgoing Transfer (POL = 0, WRREQ = 0) 18-49
18.44 308-Pad BGA Pinout (Sheet 1 of 2) 18-66
18.45 308-Pin BGA Package Mechanical Dimensions 18-71

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Tables 1.1 DMN-8600 Features Summary 1-2
4.1 DMN-8600 Storage and Serial I/O Selection 4-4
6.1 DMN-8600 Pin Descriptions 6-3
7.1 CBus Module Address Assignments 7-5
8.1 Transfer Modes and Port Configurations 8-5
8.2 Host Register Mapping (32 bits wide) 8-11
8.3 Host Register Mapping (16 bits wide) 8-12
8.4 Auto-increment Support of Host Address Registers 8-21
9.1 Secondary Bitstream Pin Configuration 9-2
10.1 Pin Functions in Different Modes 10-3
10.2 Timing Parameters 10-7
10.3 GPIO Pin Operating Modes 10-16
12.1 Audio Frame Formats 12-20
13.1 Supported DRAM Types 13-2
15.1 IR Waveform/Register Value Relationship 15-2
15.2 Alignment of Transmit Data in SDRAM 15-7
15.3 Alignment of Receive Data in SDRAM 15-7
15.4 Priority Mode Select 15-24
15.5 Legal Target ID Values 15-25
15.6 Status Register Events 15-34
15.7 Bit-bang Mode Bit to SPI Signal Mapping 15-63
15.8 SPI Transfer Modes 15-64
15.9 CSSL Bit to Chip Select Mapping 15-67
15.10 Number of Bits Sent Depending on Programmed Values
of BSIZ and BCNT 15-71
15.11 Interrupt Identification Register Details 15-86
15.12 FCR Trigger Levels 15-87
15.13 Character Length and Stop Bits of LCR 15-89
17.1 JTAG Instruction Set 17-2
17.2 Boundary Scan Chain Cells 17-3
18.1 Absolute Maximum Ratings 18-1
18.2 Operating Conditions 18-2
18.3 DC Characteristics 18-3
18.4 Miscellaneous Timing Values 18-5
18.5 Async Host Master Timing Parameters - Master Mode
Only (Master replaces Slave) 18-12

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18.6 Async Host Master Timing Parameters - Host Slave and
Slave plus Limited Master Modes Only 18-14
18.7 I-Mode Write AC Timing Parameters 18-15
18.8 I-Mode Read AC Timing Parameters 18-17
18.9 M-Mode Write AC Timing Parameters 18-18
18.10 M-Mode Read AC Timing Parameters 18-20
18.11 Clock Signals to SDRAM Timing 18-21
18.12 DMN-8600 Write to SDRAM Parameters 18-22
18.13 DMN-8600 Read from SDRAM (SDR Mode) Parameters 18-23
18.14 DMN-8600 Write to SDRAM (DDR Mode) Parameters 18-24
18.15 DMN-8600 Read from SDRAM (DDR mode) Parameters 18-25
18.16 CD Input Timing 18-26
18.17 IDC Interface Slave Timing Parameter 18-27
18.18 IDC Interface Master Timing Parameter 18-29
18.19 Audio Input/Output AC Timing Parameters 18-30
18.20 UART Interface AC Timing 18-32
18.21 Video Input Stream AC Timing Parameters at VI_CLK[0] 18-33
18.22 Video Out Clock Source 18-33
18.23 Video Output AC Timing Parameters at VO_CLK 18-34
18.24 IR AC Timing Parameters 18-36
18.25 JTAG Interface AC Timing Values 18-37
18.26 ATAPI DMA Protocol Timing 18-38
18.27 ATAPI PIO Read and Write Timing Parameters 18-40
18.28 SD Input Timing 18-42
18.29 SPI Interface Timing Parameters 18-44
18.30 1394 AC Timing Parameters 18-44
18.31 1394 AC Timing Parameters at the PHY 18-45
18.32 1394 AC Timing Parameters at the Link 18-46
18.33 SBP Timing Parameters 18-49
18.34 DMN-8600 Pin List 18-51
18.35 308 BGA Alphabetical Pin List 18-68
18.36 Recommended Hot Air or IR Solder Reflow Conditions 18-72