Luminary Micro Stellaris Series User manual

DM-LM3SFAM-04 Copyright © 2005-2007 Luminary Micro, Inc.
Stellaris® Family
Development Board
USER’S MANUAL

2February 6, 2007
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Copyright © 2006-2007 Luminary Micro, Inc. All rights reserved. Stellaris is a registered trademark and the Luminary Micro logo is a trademark
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Luminary Micro, Inc.
108 Wild Basin, Suite 350
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Main: [phone]
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http://www.luminarymicro.com

Stellaris® Family Development Board User’s Manual
February 6, 2007 3
Revision History
This table provides a summary of the document revisions.
Date Revision Description
March 2006 00 Initial release of doc to customers.
May 2006 01 Release of DB48 daughterboard and documentation.
May 2006 02 Added missing DB48 schematics to board manual PDF.
July 2006 03 Switched DB48 Layout 1 and Layout 2 figures so most current board is first.
Added QEI text to Headers paragraph in Chapter 1.
February 2007 04 Release of revision 3 of motherboard, which adds two headers: JP34 and JP35.

4February 6, 2007

Stellaris® Family Development Board User’s Manual
February 6, 2007 5
Table of Contents
Chapter 1: Stellaris® Family Development Board ......................................................................................... 9
Features.............................................................................................................................................................. 9
Block Diagram .................................................................................................................................................. 10
Functional Description ...................................................................................................................................... 11
Daughterboard .............................................................................................................................................. 11
UART ............................................................................................................................................................ 11
Headers ........................................................................................................................................................ 11
Potentiometer................................................................................................................................................ 11
Photocell ....................................................................................................................................................... 11
User LEDs..................................................................................................................................................... 11
User Pushbutton ........................................................................................................................................... 11
JTAG Debug Connector................................................................................................................................ 12
USB Debug ................................................................................................................................................... 12
I2C EEPROM Memory.................................................................................................................................. 12
SPI Flash Memory ........................................................................................................................................ 12
Buzzer........................................................................................................................................................... 12
Real-Time Clock ........................................................................................................................................... 12
External Reset .............................................................................................................................................. 12
Prototype Area .............................................................................................................................................. 12
Peripheral Device Controller (PDC) .............................................................................................................. 12
Power Supply................................................................................................................................................ 13
Motherboard Layout...................................................................................................................................... 13
Development Board Configuration.................................................................................................................... 14
Daughterboard Installation............................................................................................................................ 14
UART ............................................................................................................................................................ 14
SPI Port (On-Board Peripherals) .................................................................................................................. 14
I2C Port ......................................................................................................................................................... 14
Buzzer........................................................................................................................................................... 14
LCD Panel, DIP Switch, LEDs, and GPIOs .................................................................................................. 14
User Pushbutton ........................................................................................................................................... 15
User LEDs..................................................................................................................................................... 15
Photocell ....................................................................................................................................................... 15
Potentiometer................................................................................................................................................ 15
JTAG Debug Connector................................................................................................................................ 15
USB Debug ................................................................................................................................................... 15
32.768-KHz Clock Oscillator ......................................................................................................................... 15
Reset Switch ................................................................................................................................................. 16
GPIO Headers .............................................................................................................................................. 16
Power............................................................................................................................................................ 16
Peripheral Device Controller (PDC).................................................................................................................. 16
Stellaris Microcontroller to PDC Interface ..................................................................................................... 17
PDC I/O......................................................................................................................................................... 17
PDC Registers .............................................................................................................................................. 18

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SPI Protocol .................................................................................................................................................. 19
Chapter 2: DB28 Daughterboard ................................................................................................................... 21
Features............................................................................................................................................................ 21
Block Diagram .................................................................................................................................................. 21
Daughterboard Interface................................................................................................................................... 21
Daughterboard Layout ...................................................................................................................................... 22
Shunt Jumper ................................................................................................................................................... 23
Development Board Signal Usage.................................................................................................................... 24
Chapter 3: DB48 Daughterboard ................................................................................................................... 27
Features............................................................................................................................................................ 27
Block Diagram .................................................................................................................................................. 27
Daughterboard Interface................................................................................................................................... 27
Daughterboard Layout ...................................................................................................................................... 28
Shunt Jumpers.................................................................................................................................................. 30
Development Board Signal Usage.................................................................................................................... 31
Appendix A: Contact Information ................................................................................................................. 35
Appendix B: Schematics................................................................................................................................ 37

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List of Figures
Figure 1-1. Stellaris® Family Development Board Block Diagram .................................................................. 10
Figure 1-2. Stellaris Family Motherboard Layout ............................................................................................ 13
Figure 1-3. PDC Timing Diagrams................................................................................................................... 20
Figure 2-1. DB28 Daughterboard Block Diagram ............................................................................................ 21
Figure 2-2. DB28 Daughterboard Layout......................................................................................................... 23
Figure 3-1. DB48 Daughterboard Block Diagram ............................................................................................ 27
Figure 3-2. DB48 Daughterboard Layout 1 (R3).............................................................................................. 29
Figure 3-3. DB48 Daughterboard Layout 2 (R2).............................................................................................. 30

8February 6, 2007
List of Tables
Table 1-1. Possible Board Power Sources..................................................................................................... 16
Table 1-2. Stellaris Microcontroller to PDC Interface ..................................................................................... 17
Table 1-3. Peripheral to PDC Interface .......................................................................................................... 17
Table 1-4. PDC Registers............................................................................................................................... 18
Table 2-1. DB28 Daughterboard Interface ..................................................................................................... 22
Table 2-2. Jumper Settings for DB28 Daughterboard .................................................................................... 23
Table 2-3. Development Board Signals Used by DB28 Daughterboard......................................................... 24
Table 3-1. DB48 Daughterboard Interface ..................................................................................................... 28
Table 3-2. Jumper Settings for DB48 Daughterboard .................................................................................... 30
Table 3-3. Development Board Signals Used by DB48 Daughterboard......................................................... 31

February 6, 2007 9
Stellaris® Family Development Board
The Stellaris® Family Development Board provides a platform for product development. Hardware
and software engineers use this board for evaluation of Stellaris™ family microcontroller features
and functionality, and for software development.
The development board includes the Stellaris motherboard and a daughterboard with a Stellaris
family microcontroller. The DB28 daughterboard is available for 28-pin SOIC devices, and the
DB48 daughterboard is available for 48-pin LQFP devices. These daughterboards are described
in Chapter 2, “DB28 Daughterboard” on page 21 and Chapter 3, “DB48 Daughterboard” on page
27.
Features
The Stellaris® Family Development Board includes the following features. Note that not all
features are implemented on all Stellaris microcontrollers.
Daughterboards enable support for multiple package/pin-out options
Two UART transceivers and DB9 male connectors
All I/O available on headers
One potentiometer and one photocell for driving the Analog-to-Digital Converter (ADC) and
comparator inputs
Eight user LEDs and one pushbutton for use with the Stellaris GPIOs
Standard ARM® 20-pin JTAG debug connector
USB 2.0 full speed interface allows JTAG/SWD debug without in-circuit emulator (ICE)
8-Kbit I2C EEPROM memory
1-Mbit SPI-based flash memory
One buzzer for PWM use
32.768-KHz oscillator for real-time clock
External reset switch and power-on reset supervisor
5-V and 3.3-V LED power indicators
User-prototype area
Peripheral Device Controller (PDC) CPLD for interface with the following:
–16 character by 2-line LCD display
–8 status LEDs
–8-position dual-inline package (DIP) switch
–24 GPIOs
CHAPTER 1

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10 February 6, 2007
Block Diagram
Figure 1-1. Stellaris® Family Development Board Block Diagram
Connectors
RESET
JTAG
3.3 V
Regulator
PDC
EEPROM
I2C Bus
PA
PB
PC
PD
PE
Port Headers
SPI Bus
Flash
UART0
UART1
User LEDs
User
Pushbutton
ADC[0/2/4/6]
C0+/C1+/C2+
GPIOX
GPIOY
GPIOZ
DIP Switch
LCD Panel LEDs
GPIOs
Buzzer
ADC[1/3/5/7]
C0-/C1-/C2-
Stellaris
Daughterboard
Motherboard
Photocell
Potentiometer
USB
Expansion
Headers

Stellaris® Family Development Board User’s Manual
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Functional Description
Daughterboard
The daughterboard contains the Stellaris microcontroller and connects to the motherboard with
four 21-pin connectors. The Stellaris PLL clock is generated from a 6-MHz crystal provided on pin
sockets for easy crystal changes. An optional SMA connector can be used to drive an external
clock source.
UART
Two UART transceivers and DB9 connectors are provided to connect with the Stellaris
microcontroller UART peripherals. The UART0 peripheral (TX, RX) is included in all Stellaris
microcontrollers; UART1 is available in all 48-pin microcontrollers except the LM3S301. On the
LM3S101, LM3S102 and LM3S301, UART1 is available for external use.
Headers
All Stellaris I/O signals are available on five 8-pin GPIO headers labeled Port A through Port E to
match the Stellaris microcontroller GPIO ports. For each port header, pin 1 is bit 0 and pin 8 is bit 7
of the corresponding Stellaris GPIO. For example, Port B pin 1 is PB0 and Port B pin 8 is PB7 of
the Stellaris microcontroller. Note that ports A and E have only six I/O signals, with the remaining
two header pins connected to ground. Jumper shunts are used to connect Stellaris signals to on-
board devices to allow connect/disconnect. Stellaris signals can be rewired with the included fly-
wires.
There are also two 20-pin expansion headers (J9 and J22). Header J9 is intended primarily as an
interface for a motor driver board, and includes all the Stellaris PWM outputs, QEI inputs, analog
comparator inputs, and three ADC inputs. Header J22 has the remaining Stellaris signals, and
includes UART, SSI, I2C, JTAG, and timer CCP input signals.
NOTE: PWM, QEI, ADC, I2C, and analog comparators are available on select Stellaris
microcontrollers.
Potentiometer
One potentiometer is included to drive selected Analog-to-Digital Converter (ADC) inputs and/or
analog comparator inputs. The voltage range is 0 to 3.0. Shunt headers are used for signal
selection.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
Photocell
One photocell is included to drive selected ADC inputs and/or analog comparator inputs. The
voltage range is 0 to 3.0. Shunt headers are used for signal selection.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
User LEDs
Eight user LEDs (ULED0-ULED7) are provided for general use. Headers are provided for
connectivity.
User Pushbutton
One user pushbutton (SW3) is provided for general use. A header is provided for connectivity.

Stellaris® Family Development Board
12 February 6, 2007
JTAG Debug Connector
A standard 20-pin connector for JTAG debug is provided. This port is also used to access the
Serial-Wire Debug (SWD) interface of the Stellaris microcontroller. When using this connector, the
USB interface cannot be used for JTAG/SWD debug (USB can still be used for providing board
power). A shunt jumper at location JP31 may be required when using this port.
USB Debug
A USB 2.0 full-speed interface provides debug capability via JTAG or SWD without the need for an
ICE. Note that use of this interface requires installation of the corresponding USB drivers. When
using this interface, the 20-pin JTAG connector cannot be used for JTAG/SWD debug. Ensure that
no shunt jumper is present at location JP31.
I2C EEPROM Memory
An 8-Kbit I2C memory is included for use with the Inter-Integrated Circuit (I2C) bus interface. A
jumper block is provided for connecting this memory.
NOTE: The I2C interface is available on select Stellaris microcontrollers.
SPI Flash Memory
A 1-Mbit SPI flash memory is included for use with the Serial Port Interface (SPI) port. A jumper
block is provided for connecting this memory.
Buzzer
A buzzer is provided for use with one of the PWM outputs.
Real-Time Clock
A 32.768-KHz crystal oscillator generates a clock signal that can be used to drive the Stellaris real-
time clock. Shunt jumpers on the daughterboard can be used to connect this clock source.
External Reset
The external reset is implemented with a reset switch SW2 connected to a reset supervisor circuit,
and provides a system reset signal.
Prototype Area
A prototype area is provided for implementing user circuits. To supply power, there are power and
ground rows. The prototype area is indicated on the board with a Luminary Micro logo (see
Figure 1-2 on page 13).
Peripheral Device Controller (PDC)
A Peripheral Device Controller (PDC) implemented with a CPLD is accessible via the SPI interface
and provides access to several devices including a 16-character by 2-line LCD display, an 8-bit
DIP switch, 8 general-purpose user LEDs, and 24 GPIOs.

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Power Supply
The Stellaris® Family Development Board requires 5 volts at 500 mA for operation, and three
options are provided for supply connection.
1. A USB connector can be used when connected to a high-power (500-mA) USB hub port.
2. A 5-V jack can be used with an external power supply.
3. A terminal block can be wired to a 5-V external bench supply.
A slide switch selects between USB power and the other two options (see Figure 1-2 on page 13).
Table 1-1 on page 16 describes how to select the power supply.
Motherboard Layout
The Stellaris™ family motherboard layout is shown in Figure 1-2. The gray squares show the
location of pin 1 for all connectors and headers. (On the board silk-screen, white arrows indicate
pin 1.) There are four ground test loops: TL1-TL4. TL5 is 5.0 V, and TL6 is 3.3 V.
NOTE: Two motherboard revisions are in production, Rev 2 and Rev 3. The revision is marked in
the lower left corner of the board, as indicated in the figure. The only functional difference
between these revisions is the addition in Rev 3 of headers JP34 and JP35 next to the
GPIOZ headers to allow source selection for signals IDX (PD7 or PB2) and FAULT (PD6
or PB3). JP34 and JP35 are highlighted in the figure with a red box.
Figure 1-2. Stellaris Family Motherboard Layout
J1
J2
J3
J4
P2P1
J17
J14
SW2
R25
JP9 JP8 JP7 JP6
JP18 JP16 JP15 JP17
J9
J22
J15
PortA PortB PortC
PortD PortE Spare GPIOX GPIOY
GPIOZ
J21
J11
JP2
JP3
JP4
JP5
JP1
JP11 JP12
JP13
JP14 SCL
SDA
WP
JP19
BZ1
JP21
JP26
JP20
J20
TL4
J18
S1
J19
POT1
R3
SW3
ULED7
SW1
LED 7 JP30
LED 0 ULED 0JP22
GND
3.3V
5.0V
3. 3V
R5
JP10
JP 31 JP 34 JP 35
REV 3
NOTE: The gray squares indicate the location of pin 1 for all connectors and headers.

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14 February 6, 2007
Development Board Configuration
NOTE: In the descriptions that follow, reference designators are used to indicate locations on the
board layout (as shown in Figure 1-2). In addition, reference designators in parenthesis
refer to parts in the schematics in Appendix B, “Schematics.
Daughterboard Installation
The daughterboard connects to the motherboard header connectors J1-J4. With no power applied
to the motherboard, place the daughterboard and align each connector of the motherboard with
the corresponding daughterboard connector. Press the daughterboard down until the
daughterboard is firmly seated, and visually inspect all four connectors to ensure proper
connection before proceeding.
UART
To connect the UART0 transceiver, connect shunt jumpers on headers JP6 and JP7. To connect
UART1, connect shunt jumpers on headers JP8 and JP9.
SPI Port (On-Board Peripherals)
To connect the Serial Peripheral Interface port, which is used to communicate with the PDC and
the on-board flash memory, connect shunt jumpers to pins 1-2 of headers JP15, JP16, JP17, and
JP18. To write-protect the SPI flash memory, place a shunt jumper on JP10.
NOTE: The Stellaris microcontroller’s SSI port can be programmed for one of three serial modes:
Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments
synchronous serial. (The mode is set with the FRF bit in the SSI Control0 (SSICR0)
register.) The Stellaris Family Development Board is designed for use with SPI mode
although MICROWIRE and TI synchronous serial modes can be used when implementing
user circuits in the prototype area. SPI mode must be set to use the board’s LCD, DIP
switch, LEDs, and GPIOX, GPIOY, and GPIOZ ports.
I2C Port
To connect the I2C port for access to the on-board EEPROM, place shunt jumpers on JP13 and
JP14. To write-protect the EEPROM memory, place a shunt jumper on JP12. Address line A2 for
the EEPROM memory can be set to 0 by placing a shunt jumper on JP11. Removing the jumper
sets A2 to 1.
NOTE: The I2C interface is available on select Stellaris microcontrollers.
Buzzer
To enable the buzzer BZ1, connect a shunt jumper to JP21. To connect the buzzer power driver to
the Stellaris microcontroller PB0 port, place a shunt jumper on JP26. To use a different port to
drive the buzzer, remove the shunt at JP26 and connect a fly-wire from the desired port to JP26-2.
LCD Panel, DIP Switch, LEDs, and GPIOs
To use the LCD panel, DIP switch, LEDs LED0-LED7 (D1-D8), and the GPIOs, the SPI port must
be connected as described above. The SPI port connects to the PDC to control these devices.
The potentiometer R25 is used to adjust the contrast of the LCD panel. The LCD panel, DIP
switch, LEDs, and GPIOs are controlled with the PDC registers (see Table 1-4 on page 18).

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February 6, 2007 15
User Pushbutton
Pushbutton SW3 is available for general use. To connect this switch to PB4, place a shunt jumper
on JP19. To use a different port, remove shunt at JP19 and connect a fly-wire from the desired port
to JP19-2.
User LEDs
User LEDs ULED0-ULED7 (D9, D10, D12, D13-D17) are available for general use. Each user
LED has an associated header for connection to a Stellaris GPIO, PDC GPIO, or external circuitry.
To connect a user LED to its associated Stellaris GPIO, place a shunt jumper on the corresponding
header (ULED0-ULED3 => PB0-PB3, ULED4-ULED7 => PD0-PD3). To use a different port,
remove the shunt jumper from the header and connect a fly-wire from the desired port to pin 2 of
the header.
Photocell
Photocell R3 can be used to provide an analog signal to drive the ADC (analog-to-digital
converter) and the analog comparator using headers JP2 (ADC0,ADC2,ADC4,ADC6) =>
(PE5,PE3,PD7,PD5), and JP3 (C0+,C1+,C2+) => (PB6,PC5,PC6). To connect the photocell to an
ADC channel, place a shunt jumper on the corresponding JP2 header. To connect the photocell to
a comparator channel, place a shunt jumper on the corresponding JP3 header.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
Potentiometer
Potentiometer R5 can be used to provide an analog signal to drive the ADC (analog-to-digital
converter) and the analog comparator using headers JP4 (ADC1,ADC3,ADC5,ADC7) =>
(PE4,PE2,PD6,PD4), and JP5 (C0-,C1-,C2-) => (PB4,PB5,PC7). To connect the potentiometer to
an ADC channel, place a shunt jumper on the corresponding JP4 header. To connect the
potentiometer to a comparator channel, place a shunt jumper on the corresponding JP5 header.
NOTE: ADC and analog comparators are available on select Stellaris microcontrollers.
JTAG Debug Connector
For JTAG debug with an external ICE, connect the ICE to connector J14 with a standard 20-pin
JTAG debug cable. To link the motherboard reset to the JTAG emulator reset, place a shunt
jumper on JP20. Depending on the ICE, a shunt jumper at location JP31 may be required if a USB
driver conflict occurs.
USB Debug
For debug with USB, connect the USB cable to the USB device connector. Ensure that no shunt
jumper is present at location JP31. Note that a corresponding USB driver must be installed on the
host computer. The USB driver selects the mode of operation by controlling the USB_MOD signal
from the FTDI part (ADBUS7). If USB_MOD is 1, JTAG mode is selected. If USB_MOD is 0, SWD
mode is selected. JTAG/SWD signals are driven to the Stellaris microcontroller when the USB
driver sets USB_DEN (ADBUS6) to 0.
32.768-KHz Clock Oscillator
An on-board 32.768-KHz oscillator can be used to drive the Stellaris real-time clock. To enable this
oscillator, remove the shunt jumper on JP1. To disable the oscillator output, place a shunt jumper
on JP1.

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Reset Switch
Reset switch SW2 generates a 140-ms (minimum) system reset signal. Powering up the board
also generates a 140-ms system reset signal. A shunt jumper can be placed on JP20 to link the
JTAG emulator reset with the system reset.
GPIO Headers
All Stellaris GPIO ports are available on 8-pin headers labeled PortA (J5), PortB (J6), PortC (J7),
PortD (J10), and PortE (J12). The 20-pin headers J9 and J22 include all the GPIOs and provide a
convenient connection for expansion to another board. The 8-pin headers labeled GPIOX (J26),
GPIOY (J27), and GPIOZ (J16) provide a connection to the GPIOs implemented in the PDC.
Power
Three options are available for board power, and only one should be connected to the board.
These are described in Table 1-1. The two power indicators light once there is power to the board.
Peripheral Device Controller (PDC)
The PDC provides access to a common set of peripherals across all Stellaris microcontrollers,
since they all include an SSI port. The Stellaris SSI port is used in SPI mode for communications
with the PDC. The PDC operates at 1 MHz.
Table 1-1. Possible Board Power Sources
Power Source Configuration
USB high-power hub (500 mA) Slide switch S1 towards the board edge. Connect a USB cable
from the USB hub to the USB-B receptacle J18. Slide switch S1
towards the board center to turn on power.
5-V (500-mA) supply with 2.5-mm plug Slide switch S1 towards the center of the board. Connect a 5-V
supply with a 2.5-mm plug to jack J19. Slide switch S1 towards
the board edge to turn on power.
5-V (500-mA) bench supply Slide switch S1 towards the center of the board. Connect a 5-V
supply with two wires to terminal block J21. Connect the 5-V
wire to J21-1 (5V) and the ground wire to J21-2 (GND). Slide
switch S1 towards the board edge to turn on power.
J21
5V GND

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February 6, 2007 17
Stellaris Microcontroller to PDC Interface
The Stellaris microcontroller connects to the PDC with a SPI port using the signals shown in
Ta b l e 1 -2 .
PDC I/O
The PDC connects to supported peripherals with the following signals:
Table 1-2. Stellaris Microcontroller to PDC Interface
Board Signal Direction Description
SPI_CLK Input SPI clock signal, 1 MHz.
SPI_SEL Input SPI select signal, set high to enable SPI transfers. Set to low for
reset of the PDC (minimum 200 nanoseconds). Note that with
SPI_SEL low the SPI flash at location U3 is selected.
SPI_MOSI Input Master output, slave input data transfer signal.
SPI_MISO Output Master input, slave output data transfer signal.
Table 1-3. Peripheral to PDC Interface
Board Signal Direction Description
L_RS Out LCD register select
L_RW Out LCD read/write
L_CEN Out LCD chip enable
L_BLIGHT Out LCD backlight
LD[7:0] InOut LCD data bus
LED[7:0] Out LED select outputs
DSW[7:0] In DIP switch inputs
GPIOX_[7:0] InOut GPIOX I/O ports
GPIOY_[7:0] InOut GPIOY I/O ports
GPIOZ_[7:0] InOut GPIOZ I/O ports

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PDC Registers
PDC registers are 8 bits, and there are three types: Read-Only (RO), Read/Write (R/W), and
Read/Write delayed (RWD). A RWD transaction requires an additional dummy transfer due to
peripheral device latency.
Table 1-4. PDC Registers
Register
Address Type Description
VERSION 0x0 R0 The VERSION register contains the version of the PDC design
programmed in the CPLD.
CSR 0x1 R/W The Command/Status (CSR) register is used to set special
configuration options and read device status. Unused bits are reserved
and should be written to 0. The following bits are defined:
Bit0 - LCBL: The LCD backlight bit controls the LCD panel backlight.
Setting this bit to 1 turns on the LCD backlight. Setting this bit to 0 turns
off the LCD backlight.
Bit7 - LCBSY: The LCD busy bit reflects the value of the LCD panel
busy flag. When this bit is 1, the LCD panel is busy processing a
command. When this bit is 0, a new command can be written to the LCD
panel.
DIPSW 0x4 R0 The DIP Switch (DIPSW) register contains the value of the debug DIP
switch at location SW1. Bit i corresponds to switch i+1. A switch in the
OFF position is read as 0. A switch in the ON position is read as 1.
LED 0x5 R/W The LED Output (LED) register controls LED0-LED7. Bit i controls
LEDi. Writing a bit to 1 turns on the corresponding LED. Writing a bit to 0
turns off the corresponding LED.
LCDCSR 0x6 RWD The LCD Command/Status (LCDCSR) register is used to write
configuration and control commands and to read status information from
the LCD panel. For more information, refer to the CFAH1602B LCD
panel data sheet (available from www.crystalfontz.com).
LCDRAM 0x7 RWD The LCD RAM (LCDRAM) register is used to write and read the LCD
display data RAM (DDRAM) and the character generator RAM
(CGRAM). For more information, refer to the CFAH1602B LCD panel
data sheet (available from www.crystalfontz.com).
GPXDAT 0x8 R/W The GPIOX Data (GPXDAT) register is used to access the general-
purpose I/O port GPIOX at location J26. Bit i corresponds with the
GPIOX_i port signal. Each bit can be configured for input or output in
the GPXDIR register.
Writing a bit to 1 sets the corresponding GPIOX port signal to 1 if the
port signal is configured as an output. Writing a bit to 0 sets the
corresponding GPIOX port signal to 0 if the port signal is configured as
an output.
Reading a bit reads the value of the corresponding GPIOX port signal. If
the GPIOX port is 0, the bit will read as 0. If the GPIOX port signal is 1,
the bit will read as 1. Note that a read of the GPXDAT register always
reads the GPIOX port signals, not the internal register.

Stellaris® Family Development Board User’s Manual
February 6, 2007 19
SPI Protocol
The SPI slave interface is enabled when SPI_SEL goes High. All SPI commands and data are
received via the SPI_MOSI input signal, with data sampled on the rising edge of the SPI clock. All
SPI output data is transmitted on the SPI_MISO output signal, with data shifted out on the falling
edge of the SPI clock. Set SPI_SEL Low for 200 nanoseconds to reset the PDC.
GPXDIR 0x9 R/W The GPIOX Direction (GPXDIR) register is used to select the data
transfer direction for the GPXDAT register. Bit i corresponds to GPXDAT
bit i. Writing a bit to 1 sets the corresponding GPXDAT bit as an output
port. Writing a bit to 0 sets the corresponding GPXDAT bit as an input
port.
GPYDAT 0xA R/W The GPIOY Data (GPYDAT) register is used to access the general-
purpose I/O port GPIOY at location J27. Bit i corresponds with the
GPIOY_i port signal. Each bit can be configured for input or output in
the GPYDIR register.
Writing a bit to 1 sets the corresponding GPIOY port signal to 1 if the
port signal is configured as an output. Writing a bit to 0 sets the
corresponding GPIOY port signal to 0 if the port signal is configured as
an output.
Reading a bit reads the value of the corresponding GPIOY port signal. If
the GPIOY port is 0, the bit will read as 0. If the GPIOY port signal is 1,
the bit will read as 1. Note that a read of the GPYDAT register always
reads the GPIOY port signals, not the internal register.
GPYDIR 0xB R/W The GPIOY Direction (GPYDIR) register is used to select the data
transfer direction for the GPYDAT register. Bit i corresponds with
GPYDAT bit i. Writing a bit to 1 sets the corresponding GPYDAT bit as
an output port. Writing a bit to 0 sets the corresponding GPYDAT bit as
an input port.
GPZDAT 0xC R/W The GPIOZ Data (GPZDAT) register is used to access the general-
purpose I/O port GPIOZ at location J16. Bit i corresponds with the
GPIOZ_i port signal. Each bit can be configured for input or output in the
GPZDIR register.
Writing a bit to 1 sets the corresponding GPIOZ port signal to 1 if the
port signal is configured as an output. Writing a bit to 0 sets the
corresponding GPIOZ port signal to 0 if the port signal is configured as
an output.
Reading a bit reads the value of the corresponding GPIOZ port signal. If
the GPIOZ port is 0, the bit will read as 0. If the GPIOZ port signal is 1,
the bit will read as 1. Note that a read of the GPZDAT register always
reads the GPIOZ port signals, not the internal register.
GPZDIR 0xD R/W The GPIOZ Direction (GPZDIR) register is used to select the data
transfer direction for the GPZDAT register. Bit i corresponds with
GPZDAT bit i. Writing a bit to 1 sets the corresponding GPZDAT bit as
an output port. Writing a bit to 0 sets the corresponding GPZDAT bit as
an input port.
Table 1-4. PDC Registers
Register
Address Type Description

Stellaris® Family Development Board
20 February 6, 2007
Every transaction is composed of at least two 8-bit SPI transfers. The first byte contains a 4-bit
address on the lower bits (bits 3:0) and a read/write (R/W) bit to indicate transfer direction on the
most significant bit (bit 7). The remaining bits (bits 6:4) are reserved and must be 0. The next byte
is driven by the Stellaris microcontroller for write transfers (R/W bit=0), and by the PDC for read
transfers (R/W bit=1). For read transfers to LCD registers, a dummy byte follows the first byte, with
a valid data byte afterwards. Timing diagrams are shown in Figure 1-3.
Figure 1-3. PDC Timing Diagrams
PDC Read Transfer
D0D1D7 D2D3D6 D5 D4
LCD Read Transfer
01723654
SPI_SEL
SPI_CLK
SPI_MOSI
SPI_MISO
Dummy Byte
PDC/LCD Write Transfer
A0A1RW A2A300 0
A0A1RW A2A300 0
A0A1RW A2A300 0
D0D1
D7 D2D3D6 D5 D4
D0D1
D7 D2D3D6 D5 D4
SPI_SEL
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_SEL
SPI_CLK
SPI_MOSI
SPI_MISO