MAI Basic Four 2000 Series User manual

Basic Four Series 2000
Desktop Computer System
BFISD 8079 A Service Manual

BFISD
8079
TABLE OF CONTENTS
Page
SECTION I INTRODUCTION
1.1 General ............................................ 1-1
1.2 System Description ................................. 1-1
1.2.1 Central Microprocessor Board (CMB) ............... 1-2
1.2.2 Memory Array Boards .............................. 1-3
1.2.3 Winchester Disk Controller Board ................. 1-4
1.2.4 4-Way Controller Board .......................... 1-4
1.2.5 Magnetic Cartridge Streamer Controller Board ..... 1-4
1.2.6 Local Area Network Controller Board .............. 1-5
1.3 Specifications ..................................... 1-5
SECTION II INSTALLATION AND OPERATION
2.1 General ............................................ 2-1
2.2 Unpacking and Inspecting the Base Unit ............. 2-1
2.3 Installing the 2000 Series Computer System ......... 2-1
2.4 Switch Settings, Jumper Placements, Cable
Connections ...................................... 2-7
2.4.1 Central Microprocessor Board ..................... 2-7
2.4.2 Memory Array PCBA ................................ 2-14
2.4.3 Winchester Disk (Single-Board) Controller ........ 2-14
2.4.4 4-Way Controller PCBA ............................ 2-17
2.5 Installing the Local Area Network (LAN) ............ 2-20
2.5.1 Installing the LANG Board ........................ 2-20
2.5.2 Installing the Tap Box ........................... 2-24
2.5.3 Installing the Repeater .......................... 2-25
2.5.3.1 Connecting Network Segments .................... 2-27
2.5.3.2 Connecting A Network Branch .................... 2—27
2.5.3.3 Connecting Power to the Repeater ............... 2-28
2.5.4 Installing the LANG Software ..................... 2-28
2.6 Use and Care of Floppy Diskette and Drive .......... 2-29
2.6.1 Diskette Insertion ............................... 2-29
2.6.2 Write Protection ................................. 2-30
SECTION III FUNCTIONAL DESCRIPTION
3.1 Introduction . . . . . . . . . . . . . . . . . . . 3-1
3.2 Central Microprocessor Board (CMB) Description. . . 3-1
3.2.1 Clock Generator . . . . . . . . . . . . . . . . . 3-3
3.2.2 Function Code Decoder . . . . . . . . . . . . . . 3-3
3.2.3 Boot PROM . . . . . . . . . . . . . . . . . . . . 3-4
3.2.4 CMB Diagnostic Hardware . . . . . . . . . . . . . 3-5
3.2.4.1 CMB Status Drivers . . . . . . . . . . . . . . 3-5
3.2.4.2 CMB Control Register. . . . . . . . . . . . . . 3-5
3.2.5 Main Memory Fault Detection Circuits. . . . . . . 3-6
3.2.5.1 Parity Error Register . . . . . . . . . . . . . 3-8
3.2.5.2 Status Register Parity Bit. . . . . . . . . . . 3-8
3.2.5.3 Parity Error Interrupt Cycle. . . . . . . . . . 3-9
iii

BFISD 8079
TABLE OF CONTENTS (continued)
Page
SECTION III FUNCTIONAL DESCRIPTION (cont'd)
3.2.6 Interrupt Logic . . . . . . . . . . . . . . . . . 3-9
3.2.6.1 Interrupt Control Logic . . . . . . . . . . . . 3-10
3.2.6.2 Interrupt Acknowledge Decoder . . . . . . . . . 3-11
3.2.7 Reset and Power Fail Detection Logic. . . . . . . 3-11
3.2.8 System I/O Bus Control Logic. . . . . . . . . . . 3-12
3.2.9 Non-Volatile RAM. . . . . . . . . . . . . . . . . 3-12
3.2.10 Data Transfer Acknowledge Generator . . . . . . . 3-14
3.2.10.1 Timing Generation . . . . . . . . . . . . . . . 3-17
3.2.10.2 Timing Selection. . . . . . . . . . . . . . . . 3-17
3.2.10.3 Bus Error Generation. . . . . . . . . . . . . . 3-18
3.2.11 Bus Arbitration Logic . . . . . . . . . . . . . . 3-19
3.2.11.1 Bus Arbitration Cycle . . . . . . . . . . . . . 3-20
3.2.11.2 Fast Bus Grant. . . . . . . . . . . . . . . . . 3-21
3.2.12 Address Space Decoding Logic. . . . . . . . . . . 3-22
3.2.12.1 READ Cycle Decoding . . . . . . . . . . . . . . 3-24
3.2.12.2 WRITE Cycle Decoding. . . . . . . . . . . . . . 3-24
3.2.12.3 Memory Select Decoding. . . . . . . . . . . . . 3-24
3.2.12.4 Local I/O Decoding. . . . . . . . . . . . . . . 3-25
3.2.13 Byte Interface Control Logic. . . . . . . . . . . 3-25
3.2.14 Memory Address Bus. . . . . . . . . . . . . . . . 3-25
3.2.14.1 Memory Array Board Selection. . . . . . . . . . 3-26
3.2.14.2 Memory Array Bus Multiplexing . . . . . . . . . 3-26
3.2.15 Dynamic Memory Support. . . . . . . . . . . . . . 3-27
3.2.15.1 Memory Timing . . . . . . . . . . . . . . . . . 3-28
3.2.15.2 Row Address Strobe. . . . . . . . . . . . . . . 3-28
3.2.15.3 Column Address Strobes. . . . . . . . . . . . . 3-28
3.2.15.4 Memory Refresh. . . . . . . . . . . . . . . . . 3-30
3.2.15.5 Refresh Address and Request Generation. . . . . 3—31
3.2.15.6 Refresh Arbitration . . . . . . . . . . . . . . 3-32
3.2.16 Memory Management Unit. . . . . . . . . . . . . . 3—33
3.2.16.1 Segmentation. . . . . . . . . . . . . . . . . . 3-33
3.2.16.2 Swapping. . . . . . . . . . . . . . . . . . . . 3-34
3.2.16.3 Other MMU Functions . . . . . . . . . . . . . . 3-34
3.2.16.4 Supervisor and User Access of the MMU . . . . . 3-36
3.2.16.5 MMU Address Translation . . . . . . . . . . . . 3-37
3.2.16.6 Segment Attributes. . . . . . . . . . . . . . . 3-38
3.2.16.7 Segment Status. . . . . . . . . . . . . . . . . 3-39
3.2.16.8 MMU Error Generation. . . . . . . . . . . . . . 3-40
3.2.17 Serial Ports. . . . . . . . . . . . . . . . . . . 3-41
3.2.17.1 Serial/Parallel Conversion. . . . . . . . . . . 3-41
3.2.17.2 Communications Protocol Selection . . . . . . . 3-44
3.2.17.3 Electrical Configuration Selection. . . . . . . 3-46
3.2.17.4 Addressing and Control. . . . . . . . . . . . . 3-48
3.2.18 Parallel Port . . . . . . . . . . . . . . . . . . 3-50
3.2.18.1 Addressing and Control. . . . . . . . . . . . . 3-50
3.2.18.2 Data Transmission to a Printer. . . . . . . . . 3-51
3.2.19 Floppy Disk Controller. . . . . . . . . . . . . . 3-51
3.2.19.1 Soft Sectoring. . . . . . . . . . . . . . . . . 3-51
3.2.19.2 Double-Density Recording. . . . . . . . . . . . 3-55
iv

BFISD 8079
TABLE OF CONTENTS (continued)
Page
SECTION III FUNCTIONAL DESCRIPTION (cont'd)
3.2.19.3 MFM Data Separation . . . . . . . . . . . . . . 3-57
3.2.19.4 Bit-Shifting. . . . . . . . . . . . . . . . . . 3-61
3.2.19.5 Floppy Drive Disk Control . . . . . . . . . . . 3-63
3.2.19.6 Buffered Data Transfer. . . . . . . . . . . . . 3-66
3.2.19.7 Floppy Disk Controller Section Control. . . . . 3-70
3.3 Memory Array Board Functional Description . . . . . 3—72
3.4 Base Unit Power Supply Functional Description . . . 3-72
SECTION IV
4.1 Introduction. . . . . . . . . . . . . . . . . . . . 4-1
4.2 Special Tools . . . . . . . . . . . . . . . . . . . 4-1
4.3 Preventative Maintenance. . . . . . . . . . . . . . 4-1
4.4 Trouble Analysis. . . . . . . . . . . . . . . . . . 4-2
SECTION V REMOVAL/REPLACEMENT
5.1 Introduction. . . . . . . . . . . . . . . . . . . . 5-1
5.2 Replacing the Central Microprocessor Board (CMB). . 5-1
5.3 Replacing the Base Unit Power Supply. . . . . . . . 5-9
5.4 Replacing the Memory Array Modules. . . . . . . . . 5-11
5.5 Replacing the 4-Way Controller Boards . . . . . . . 5-14
5.6 Replacing the Winchester Drive Controller (WDC)
Board . . . . . . . . . . . . . . . . . . . . . . 5-17
5.7 Replacing the Magnetic Cartridge Streamer
Controller (MCSC) Board . . . . . . . . . . . . . 5-18
5.8 Replacing the Winchester Drive Controller Bus
Adapter Board . . . . . . . . . . . . . . . . . . 5-22
5.9 Replacing the Local Area Network (LAN) Board. . . . 5-23
5.10 Replacing the Winchester Drive. . . . . . . . . . . 5-26
5.11 Replacing the Floppy Disk Drive . . . . . . . . . . 5-27
SECTION VI ILLUSTRATED PARTS LIST
6.1 Introduction. . . . . . . . . . . . . . . . . . . . 6-1
6.2 Index of Assemblies . . . . . . . . . . . . . . . . 6-1
SECTION VII 5.25" FLOPPY DISK DRIVE
7.1 Introduction. . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 General Description . . . . . . . . . . . . . . . 7-1
7.1.1.1 Spindle Mechanism . . . . . . . . . . . . . . . 7-1
7.1.1.2 Positioning Mechanism . . . . . . . . . . . . . 7-1
7.1.1.3 Head Load/Interlock Mechanism . . . . . . . . . 7-2
7.1.2 Functional Concepts . . . . . . . . . . . . . . . 7-2
v

BFISD 8079
TABLE OF CONTENTS (continued)
Page
SECTION VII 5.25" FLOPPY DISK DRIVE (cont'd)
7.1.2.1 Stepper Motor Control . . . . . . . . . . . . . 7-5
7.1.2.2 Drive Motor Control . . . . . . . . . . . . . . 7-6
7.1.2.3 Head Load Circuit . . . . . . . . . . . . . . . 7-6
7.1.2.4 Motion Check LED. . . . . . . . . . . . . . . . 7-6
7.1.2.5 Track 00 Detection. . . . . . . . . . . . . . . 7-6
7.1.2.6 Write Protect Detector. . . . . . . . . . . . . 7-7
7.1.2.7 Index Detector. . . . . . . . . . . . . . . . . 7-7
7.1.2.8 Ready Detector. . . . . . . . . . . . . . . . . 7-9
7.1.2.9 Read/Write Heads. . . . . . . . . . . . . . . . 7-10
7.1.2.10 Write Circuit . . . . . . . . . . . . . . . . . 7-11
7.1.2.11 Read Circuit. . . . . . . . . . . . . . . . . . 7-12
7.1.2.12 Read/Write Select Circuit . . . . . . . . . . . 7-12
7.1.2.13 Read Amplifier Circuit and Filter Work. . . . . 7-13
7.1.2.14 Active Differential Circuit and Comparator . . 7-13
7.1.2.15 Timed Main Filter and Crossover Detector . . . 7-14
7.1.2.16 DC Control Circuit. . . . . . . . . . . . . . . 7-17
7.1.2.17 Power-On Reset Circuit. . . . . . . . . . . . . 7-17
7.1.3 Equipment Specifications. . . . . . . . . . . . . 7-17
7.2 Installation and Maintenance. . . . . . . . . . . . 7-20
7.2.2 Equipment Placement . . . . . . . . . . . . . . . 7-20
7.2.3 Electrical Installation . . . . . . . . . . . . . 7-20
7.2.4 Adjustment Procedures . . . . . . . . . . . . . . 7-20
7.2.4.1 Index Burst Position Adjustment . . . . . . . . 7-21
7.2.4.2 Track Position Adjustment . . . . . . . . . . . 7-21
7.2.4.3 Track 00 Position Adjustment. . . . . . . . . . 7-22
7.2.4.4 Rotation Adjustment . . . . . . . . . . . . . . 7-23
7.2.4.5 0-1 Head Gap Adjustment . . . . . . . . . . . . 7-23
7.3 Reference Information . . . . . . . . . . . . . . . 7-24
7.3.1 Interface . . . . . . . . . . . . . . . . . . . . 7-24
7.3.1.1 Signal Interface. . . . . . . . . . . . . . . . 7-24
7.3.1.2 Input Lines . . . . . . . . . . . . . . . . . . 7-25
7.3.1.3 Output Lines. . . . . . . . . . . . . . . . . . 7-27
7.3.2 Jumper Pin. . . . . . . . . . . . . . . . . . . . 7-28
SECTION VIII 20 MEGABYTE WINCHESTER DRIVE SYSTEM
8.1 Introduction. . . . . . . . . . . . . . . . . . . . 8-1
8.1.1 General Description . . . . . . . . . . . . . . . 8-1
8.1.2 Functional Concepts . . . . . . . . . . . . . . . 8-4
8.1.3 Equipment Specifications. . . . . . . . . . . . . 8-5
8.2 Installation and Operation. . . . . . . . . . . . . 8-8
8.2.1 Unpacking. . . . . . . . . . . . . . . . . . . . . 8-8
8.2.2 Equipment Placement. . . . . . . . . . . . . . . . 8-8
8.2.3 Shipping Lock (Read/Write Heads) . . . . . . . . . 8-8
8.2.4 Step Rate Selection. . . . . . . . . . . . . . . . 8-8
8.2.5 System Installation. . . . . . . . . . . . . . . . 8-9
8.2.6 Operation. . . . . . . . . . . . . . . . . . . . . 8-9
8.3 Functional Description . . . . . . . . . . . . . . . 8-11
vi

BFISD 8079
TABLE OF CONTENTS (continued)
Page
SECTION VIII 20 MEGABYTE WINCHESTER DRIVE SYSTEM (cont'd)
8.3.1 Basic Disk Principles . . . . . . . . . . . . . . 8-11
8.3.2 Control Lines. . . . . . . . . . . . . . . . . . . 8-13
8.3.3 Winchester Drive Controller . . . . . . . . . . . 8-14
8.3.3.1 Signal Definitions . . . . . . . . . . . . . . 8-16
8.3.3.2 Detailed Description (Handshaking and Timing) . 8-19
8.3.3.3 Programming Information . . . . . . . . . . . . 8-21
8.3.3.4 Command . . . . . . . . . . . . . . . . . . . . 8-22
8.4 Maintenance . . . . . . . . . . . . . . . . . . . . 8-44
8.4.1 Diagnostics . . . . . . . . . . . . . . . . . . . 8-44
8.4.1.1 Power-Up Diagnostics . . . . . . . . . . . . . . 8-44
8.4.1.2 Operational Error Check . . . . . . . . . . . . 8-46
8.4.1.3 Fault Diagnostics . . . . . . . . . . . . . . . 8-46
8.5 Removal and Replacement Procedures . . . . . . . . . 8-48
8.5.1 Master Electronics PCBA Removal and Replacement . 8-48
8.5.2 Brack Removal and Replacement. . . . . . . . . . . 8-51
8.5.3 Motor Control PCBA Removal and Replacement . . . . 8-52
8.5.4 Preamplifier PCBA Removal and Replacement. . . . . 8-52
8.6 Parts List . . . . . . . . . . . . . . . . . . . . . 8-52
SECTION IX 50 MEGABYTE WINCHESTER DRIVE SYSTEM
9.1 Introduction . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 General Description . . . . . . . . . . . . . . . 9-1
9.1.2 Functional Concepts . . . . . . . . . . . . . . . 9-2
9.1.3 Equipment Specifications . . . . . . . . . . . . . 9-3
9.2 Installation and Operation . . . . . . . . . . . . . 9-6
9.2.1 Unpacking . . . . . . . . . . . . . . . . . . . . 9-6
9.2.2 Equipment Placement . . . . . . . . . . . . . . . 9—6
9.2.3 Shipping Lock (Read/Write Heads) . . . . . . . . 9-6
9.2.4 System Installation . . . . . . . . . . . . . . . 9-6
9.2.5 Power and Interface Cables and Connectors . . . . 9-7
9.2.6 Drive Addressing and Interface Termination . . . 9-7
9.2.7 Installation of the Winchester Drive and the
WDC PCBA . . . . . . . . . . . . . . . . . . . . 9-10
9.2.8 Operation . . . . . . . . . . . . . . . . . . . . 9-13
9.3 Functional Description . . . . . . . . . . . . . . . 9-14
9.3.1 Basic Disk Principles . . . . . . . . . . . . . . 9-14
9.3.2 Control Lines . . . . . . . . . . . . . . . . . . 9-16
9.3.3 Winchester Drive Controller . . . . . . . . . . . 9-18
9.3.3.1 Signal Definitions . . . . . . . . . . . . . . . 9-19
9.3.3.2 Detailed Description (Handshaking and Timing) . 9-22
9.3.3.3 Programming Information . . . . . . . . . . . . 9—24
9.3.3.4 Commands . . . . . . . . . . . . . . . . . . . . 9-25
SECTION X SCHEMATICS
vii/viii

BFISD 8079
LIST OF ILLUSTRATIONS
Figure Page
1-1 Model 4108 Base Unit. . . . . . . . . . . . . . . . xvi
1-2 Block Diagram of the Base Unit Hardware System. . . 1-2
1-3 The Layout of the Central Microprocessor Board. . . 1-3
2-1 Rear View of Base Unit, Showing Location of all
Connectors . . . . . . . . . . . . . . . . . . . 2-5
2-2 Location of Jumpers on Central Microprocessor
Board . . . . . . . . . . . . . . . . . . . . . . 2-8
2-3 Central Microprocessor Board Cable Part Numbers . . 2-9
2-4 Location of Address Switches on Memory Array
Module. . . . . . . . . . . . . . . . . . . . . . 2-15
2-5 Location of Jumpers on (Single-Board) Winchester
Disk Controller . . . . . . . . . . . . . . . . . 2-16
2-6 Location of Switches on 4-Way Controller PCBA . . . 2-18
2-7 Location of Switch on Magnetic Cartridge
Streamer Controller PCBA. . . . . . . . . . . . . 2-19
2-8 Location of Switches and Cable Information for
LANG PCBA . . . . . . . . . . . . . . . . . . . . 2-21
2-9 Outline of Tap Box, Showing Screw Connections . . . 2-24
2-10 Outline of Repeater Unit, Showing Screw
Connections . . . . . . . . . . . . . . . . . . . 2-26
3-1 Simplified Block Diagram, Central Microprocessor
Board . . . . . . . . . . . . . . . . . . . . . . 3-2
3-2 Timing Diagram, PDTACK- and Bus Error Generation. . 3-19
3-3 Address Space Decoding Logic. . . . . . . . . . . . 3-23
3-4 Timing Relationships for the Signals of a Dynamic
RAM Chip. . . . . . . . . . . . . . . . . . . . . 3-27
3-5 Simplified Block Diagram, Dynamic Memory Support
Subsystem . . . . . . . . . . . . . . . . . . . . 3-29
3-6 Memory Control Timing Diagram . . . . . . . . . . . 3-31
3-7 Refresh Timing Diagram. . . . . . . . . . . . . . . 3-33
3-8 Simplified Block Diagram, Memory Management Unit. . 3—35
3-9 Logical Block Diagram, MMU Status Reporting/Error
Detection . . . . . . . . . . . . . . . . . . . . 3-36
3-10 Simplified Block Diagram, CMS Serial Ports. . . . . 3-42
3-11 Simplified Block Diagram, 8530 SCC Chip . . . . . . 3-43
3-12 Simplified Block Diagram, CMB Floppy Disk
Controller. . . . . . . . . . . . . . . . . . . . 3-54
3-13 Signal Encoding and Derived Clock, Kansas City
Standard. . . . . . . . . . . . . . . . . . . . . 3-55
3-14 Maximum Data Rate Recording, Kansas City Standard . 3-56
3-15 Encoded Data for FM Recording...........3-57
3-16 Encoded Data for Modified FM (MFM) Recording. . . . 3-58
3-17 Simplified Block Diagram, Data Separator Phase
Detector Logic. . . . . . . . . . . . . . . . . . 3-59
3-18 Bit Shifting. . . . . . . . . . . . . . . . . . . . 3-61
3-19 Register Layout, WD1793 Floppy Disk Controller Chip 3-64
ix

BFISD 8079
LIST OF ILLUSTRATIONS (continued)
Figure Page
5—1 Location of Jumpers on Central Microprocessor
Board . . . . . . . . . . . . . . . . . . . . . . 5-3
5-2 Central Microprocessor Board Cable Part Numbers . . 5-4
5-3 Location of Address Switches on Memory Array
Module. . . . . . . . . . . . . . . . . . . . . . 5-13
5-4 Location of Switches on 4-Way Controller PCBA . . . 5-16
5-5 Location of Jumpers on the Winchester Drive
Controller PCBA . . . . . . . . . . . . . . . . . 5-19
5-6 Location of Switch on Magnetic Cartridge Streamer
Controller PCBA . . . . . . . . . . . . . . . . . 5-21
5-7 Location of Switches on Local Area Network
Controller PCBA . . . . . . . . . . . . . . . . . 5-24
6-1 CMB PCBA . . . . . . . . . . . . . . . . . . . . . 6-2
6-2 Memory Array PCBA . . . . . . . . . . . . . . . . . 6-8
6-3 WDC Bus Adapter PCBA. . . . . . . . . . . . . . . . 6-10
6-4 4-Way Controller PCBA . . . . . . . . . . . . . . . 6-14
6-5 MTCS Controller PCBA. . . . . . . . . . . . . . . . 6-18
6-6 LAN Controller PCBA . . . . . . . . . . . . . . . . 6-22
7-1 Spindle Mechanism . . . . . . . . . . . . . . . . . 7-2
7-2 Positioning Mechanism . . . . . . . . . . . . . . . 7-3
7-3 Head Load/Interlock Mechanism . . . . . . . . . . . 7-3
7-4 Functional Block Diagram . . . . . . . . . . . . . 7-4
7-5 Stepper Motor Control Circuit Block Diagram . . . . 7-5
7-6 Stepper Motor Timing Diagram (48 TPI) . . . . . . . 7-5
7-7 Stepper Motor Timing Diagram (96 TPI) . . . . . . . 7-5
7-8 Stepper Motor Phase Transfer Chart . . . . . . . . 7-6
7-9 Head Load Circuit . . . . . . . . . . . . . . . . . 7-7
7-10 Head Load Timing Diagram . . . . . . . . . . . . . 7-7
7-11 Track 00 Detection Circuit . . . . . . . . . . . . 7-8
7-12 Track 00 Timing Diagram (48 TPI) . . . . . . . . . 7-8
7-13 Track 00 Timing Diagram (96 TPI) . . . . . . . . . 7-8
7-14 Write Protect Detector Circuit . . . . . . . . . . 7-9
7-15 Index Detection Circuit . . . . . . . . . . . . . . 7-9
7-16 Ready Detector Timing Diagram . . . . . . . . . . . 7-10
7-17 Read/Write Head Connection . . . . . . . . . . . . 7-10
7-18 Write Start Timing Diagram . . . . . . . . . . . . 7-10
7-19 Write Circuit Block Diagram . . . . . . . . . . . . 7-11
7-20 Write Timing Diagram (FM) . . . . . . . . . . . . . 7-11
7-21 Simplified Erase Delay Circuit . . . . . . . . . . 7-12
7-22 Erase Delay Timing Diagram . . . . . . . . . . . . 7-12
7-23 Read Circuit Block Diagram . . . . . . . . . . . . 7-13
7-24 Read Start Timing Diagram . . . . . . . . . . . . . 7-13
7-25 Read/Write Select Circuit . . . . . . . . . . . . . 7-14
7-26 Read Amplifier Circuit and Filter Network . . . . . 7-14
7-27 Active Differential Circuit and Comparator . . . . 7-15
7-28 Timed Main Filter and Crossover Detector . . . . . 7-15
x