MESA Electronic 4I24M Series User manual

4I24M PARALLEL PORT MANUAL
Version 1.0
Copyright 1997 byMESA ELECTRONICS Richmond, CA. Printed in the United States ofAmerica.
All rights reserved. This document and the data disclosed herein is not to be reproduced, used,
disclosed inwholeor inpart to anyonewithout thewritten permissionofMESAELECTRONICS.
MesaElectronics
4175LakesideDrive,Suite#100
Richmond,CA94806-1950
Tel [phone] - Fax [phone]
E-Mail: [e-mail] - Website: www.mesanet.com

TABLE OF CONTENTS
HANDLING PRECAUTIONS
Staticelectricity 3........................................................................
INTRODUCTION
General 4................................................................................
CONFIGURATION
General 5................................................................................
Default jumper settings 5................................................................
Baseaddress selection 7.................................................................
Aliased address selection 7...............................................................
I/O poweroptions 9......................................................................
INSTALLATION
General 11...............................................................................
I/Oconnectororientation 11.............................................................
OPERATION
Portmapping 12.........................................................................
Connector pinout 13.....................................................................
8255LOOP 16...........................................................................
REFERENCE INFORMATION
Specifications 17.........................................................................
Warranty 18..............................................................................
Schematicdiagrams 19...................................................................
4I24M USER'S MANUAL

HANDLING PRECAUTIONS
4I24M USER'S MANUAL
STATICELECTRICITY
The CMOS integrated circuits on the 4I24M can be damaged by exposure to electrostatic
discharges. The following precautions should be taken when handling the 4I24M to prevent
possibledamage.
A.Leavethe4I24M initsantistaticbaguntilneeded.
B.Allworkshouldbeperformedatanantistaticworkstation.
C.Groundequipmentintowhich4I24M willbe installed.
D. Ground handling personnel with conductive bracelet through 1 megohm resistor to
ground.
E. Avoid wearing synthetic fabrics, particularlyNylon.

INTRODUCTION
GENERAL
The MESA 4I24 series ofcards are 96 bit parallelI/O interfaces implemented on the PC/104 bus.
The 4I24 uses4 (4I24, 4I24I) or 3(4I24M) socketed 82C55PIO chips to givefor a totalof96 I/Obits
(4I24, 4I24I) or 72 I/O bits (4I24M). 3.3K Pullup resistors are provided on all ports to simplify
interfacingto contactclosure,opto-isolators,etc.
The 4I24 includes three models with different I/O connectors. The standard 4I24 uses two 50 pin
headers for I/O connections. The 50 pin connectors each have 48 I/O bits, ground, and power. The
4I24I uses four 26 pin headers with ISO standard pinout (24 I/O bits per 26 pin connector, pin 2 =
GND,pin 26= 5V).The 4I24M hasI/O module rack compatible pinouts with three 50 pin connectors
each having 24 I/O bits with interleaved grounds. 5V power on the I/O connectors is fused on the
4I24.
All 4I24 models can use the 16 bit stack through type PC/104 bus architecture. Four layer circuit
card construction is used to minimize radiated EMI and provide optimum ground and power
integrity. AllCMOS design keeps power consumptionto aminimum. The 4I24 requires only+5V for
operation
The 4I24 base address is set with jumpers, and can be located anywhere in the 1024 byte I/O
address space of the PC/104 bus. 4I24 cards use 16 contiguous I/O address's, but where multiple
cards are used, an aliased addressing capability allows up to four 4I24 cards to share the same 10 bit
baseaddress,conservingI/Oaddressspace.
A partiallyloaded 48 bit version ofthe 4I24 and 4I24I can be provided if needed, contact MESA
for availability.
4I24M USER'S MANUAL
Page 4

CONFIGURATION
GENERAL
The 4I24M port address and I/O power connection options are set with jumpers. Each group of
jumpers willbe discussed separately byfunction. In the following discussions, when the words "up",
"down", "right", and "left" are used it is assumed that the 4I24M I/O card is oriented with its bus
connectors J1andJ2at thebottomedge ofthecard(nearest thepersondoing the configuration).
DEFAULT JUMPER SETTINGS
Factorydefault4I24Mjumperingis asfollows:
FUNCTION JUMPER(S) SETTING
4I24M power option W5 I/O conns pin 49 = gnd
4I24M ground option W1,W4,W15 I/O even pins = gnd
4I24M bit A0 option W2,W3,W14 I/O conns pin 1 = bit A0
4I24M Base address W6,W7,W8,W9 0200H
W10,W11
4I24M Aliased address W12,W13 0000H
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4I24M USER'S MANUAL

CONFIGURATION
DEFAULT JUMPER SETTINGS
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4I24M USER'S MANUAL

CONFIGURATION
BASE ADDRESS SELECTION
The I/O addresses of the three 82C55's on the 4I24M are selected byplacing shorting jumpers on
jumper blocks W6 through W11. Jumper blocks W6 through W11 have three pins and two valid
shorting jumper locations, up, and down. The position of jumpers on W6 through W11 is a binary
representation of the 4I24M base address. When a jumper is in the up position, it matches a high
addressline.
Thefollowingtable showssomeexamplebaseaddresssettings
BASE ADDRESS W6 W7 W8 W9 W10 W11
(A9) (A8) (A7) (A6) (A5) (A4)
0200H (Default) up down down down down down
0290H up down up down down up
0360H up up down up up down
ALIASED ADDRESS SELECTION
If multiple 4I24M's are used in a single system, I/O address space can be conserved by using
aliased address's. Aliasedaddresses are anartifact caused bythepartial(only10 bit) addressdecoding
used bymost PC-buscards. 4I24M cards actuallydecode A15 and A14in addition to A0 throughA9.
This makes it possibleto have up to four 4I24M's located at what appears to other cards inthe system
to be a single 16 byte block of I/O addresses. This is done by selecting the same base addresses on all
cards, but selecting differing high order (aliased) addresses.
Thealiased address usedbya4I24MisselectedviashortingjumpersW12andW13.
Note that aliased addressing only makes sense when using multiple 4I24M's in a single system,
andwhenall baseaddress'susedarethesame.
Thefollowingtable shows allfour ofthepossible aliasedaddress settings:
ALIASED ADDRESS W12 W13
(A15) (A14)
BASE + 0000H (Default) down down
BASE + 4000H down up
BASE + 8000H up down
BASE + C000H up up
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4I24M USER'S MANUAL

CONFIGURATION
BASE AND ALIASED ADDRESS JUMPERS
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4I24M USER'S MANUAL

CONFIGURATION
+5V ENABLE JUMPER
Pin 49 on all of the 4I24M I/O connectors can either be grounded or connected to system +5V
through afuse. +5V isprovided onpin49to supplypowerto I/Omoduleracks.Thisoptionisselected
by the position of the shorting jumper on jumper block W5. When the jumper is in the left hand
position, fused +5V power is routed to pin 49 on the I/O connectors. When W5 is in the right hand
position,pin49 isusedasanadditionalground.Thisisthedefault positionofthe +5V enablejumper.
Note that the +5V fuse is rated at 1Ampand can be replaced without soldering. Replacementpart
numberisLittleFuse PN250001.
PIN 1 OPTION JUMPERS
Pin 1 is used bysome8 and16 I/O module racks as anadditional5V power source, but is used as
an I/O bit by24 module racks. Jumper blocks W2,W3, and W14 allow pin 1 to be connected to either
+5V or theappropriate I/O bit.Jumper W3selects theoption for connector P1, jumper W2selects the
optionforconnectorP2,andjumperW14selectstheoptionforconnectorP3.
When W2, W3, or W14 are in the left hand position, power is routed to pin 1 of the associated
connector. This istheappropriate setting for most 8and 16module I/Oracks. Notethat power to W2,
W3, and W14 comes from power option jumper W5, which must be in the left hand position in order
tosupplypowertoI/Omoduleracks.
When W2, W3,or W14 are in theright hand position, pin 1 is an I/O bit. This is the appropriate setting
for 24 moduleI/O racks. This is also the default positionofthepin1 option jumpers.
GROUND OPTION JUMPERS
Normally all even pins of the 4I24M 50 pin I/O connectors are grounded at the 4I24M. In some
circumstances, this maycause ground noise to be conducted into the system ground. All I/O ground
linescanbedisconnected at the4I24Mifdesired.
Jumper blocks W1,W4, and W15 select whether or not the even I/O pins are grounded. Jumper W4
selects the option for connector P1, jumper W15 selects the option for connector P2, and jumper W1
selects the option for connector P3. When W1, W4, or W15 are in the left hand position, all even pins
of the associated connector willbe disconnected from ground. When W1, W4, or W15 are in the right
hand position, alleven pins ofthe associated connector will be grounded at the 4I24M. This is default
settingofthegroundoptionjumpers.
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4I24M USER'S MANUAL

CONFIGURATION
POWER OPTION JUMPERS
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4I24M USER'S MANUAL

INSTALLATION
GENERAL
Whenthe 4I24M hasbeen properlyconfigured for itsapplication, it can be inserted into a PC/104
stack. The standoffs should then be tightened to secure the 4I24M in its place. When the 4I24M is
securedinthestackthe50 pinheaderscanbepluggedinfromthesides.
I/O CONNECTOR ORIENTATION
The 50 pin connectors on the 4I24M have their pin one ends marked with a white square on the
circuit card. This corresponds with the colored stripeon typicalflat cable assemblies. Ifmore positive
polarization is desired, center polarized IDC header connectors should be used. These connectors
will not fully mate with the pins on the 4I24M ifinstalled backwards. Asuggested center polarized 50
pinIDCheaderisAMPPN1-746285-0.
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4I24M USER'S MANUAL

OPERATION
PORT MAPPING
The 4I24M has three 82C55 chips. Each 82C55 chip occupies four contiguous locations in I/O
space, for a total of twelve I/O locations, but the 4I24M decoding scheme actually uses sixteen I/O
locationsper4I24Mcard,withthelastfour locationsper card notused.
In the following table and I/O connector pinout tables the letters A, B, and C refer to individual
ports on a 8255 chip (the standard 8255 port names), while the numeric suffix 0,1, or 2 refers to the
specificchip.
The82C55portsareaddressed asfollows:
ADDRESS PORT CONNECTOR
BASE+0 A0 P3
BASE+1 B0 P3
BASE+2 C0 P3
BASE+3 Control0
BASE+4 A1 P1
BASE+5 B1 P1
BASE+6 C1 P1
BASE+7 Control1
BASE+8 A2 P2
BASE+9 B2 P2
BASE+A C2 P2
BASE+B Control2
BASE+C XXX
BASE+D XXX
BASE+E XXX
BASE+F XXX
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4I24M USER'S MANUAL

OPERATION
CONNECTOR PIN-OUT
The4I24M50pinI/Oconnectorpinoutsareasfollows:
P3 CONNECTOR
PIN SIGNAL
1 A0 bit 0 or +5V fused power (W14 option)
3 A0 bit 1
5 A0 bit 2
7 A0 bit 3
9 A0 bit 4
11 A0 bit 5
13 A0 bit 6
15 A0 bit 7
17 B0 bit 0
19 B0 bit 1
21 B0 bit 2
23 B0 bit 3
25 B0 bit 4
27 B0 bit 5
29 B0 bit 6
31 B0 bit 7
33 C0 bit 0
35 C0 bit 1
37 C0 bit 2
39 C0 bit 3
41 C0 bit 4
43 C0 bit 5
45 C0 bit 6
47 C0 bit 7
49 +5V fused power or GND (W5 option)
All even pins connected to ground or open (W1 option)
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4I24M USER'S MANUAL

OPERATION
P1 CONNECTOR
PIN SIGNAL
1 A1 bit 0 or +5V fused power (W3 option)
3 A1 bit 1
5 A1 bit 2
7 A1 bit 3
9 A1 bit 4
11 A1 bit 5
13 A1 bit 6
15 A1 bit 7
17 B1 bit 0
19 B1 bit 1
21 B1 bit 2
23 B1 bit 3
25 B1 bit 4
27 B1 bit 5
29 B1 bit 6
31 B1 bit 7
33 C1 bit 0
35 C1 bit 1
37 C1 bit 2
39 C1 bit 3
41 C1 bit 4
43 C1 bit 5
45 C1 bit 6
47 C1 bit 7
49 +5V fused power or GND (W5 option)
All even pins connected to ground or open (W4 option)
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4I24M USER'S MANUAL

OPERATION
P2 CONNECTOR
PIN SIGNAL
1 A2 bit 0 or +5V fused power (W2 option)
3 A2 bit 1
5 A2 bit 2
7 A2 bit 3
9 A2 bit 4
11 A2 bit 5
13 A2 bit 6
15 A2 bit 7
17 B2 bit 0
19 B2 bit 1
21 B2 bit 2
23 B2 bit 3
25 B2 bit 4
27 B2 bit 5
29 B2 bit 6
31 B0 bit 7
33 C2 bit 0
35 C2 bit 1
37 C2 bit 2
39 C2 bit 3
41 C2 bit 4
43 C2 bit 5
45 C2 bit 6
47 C2 bit 7
49 +5V fused power or GND (W5 option)
All even pins connected to ground or open (W15 option)
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4I24M USER'S MANUAL

OPERATION
8255LOOP
A simple test program is supplied with the 4I24M for functional testing and verification. This
programis called 8255LOOP.EXE. 8255LOOP is what'scalled a loopback test program.It works by
sending rotating bit patternsout on all24 bits of a8255 programmed for alloutputs, thenchecking to
see that the same pattern has beenreceived on a second 8255 programmed for allinputs. After this is
done, 8255LOOP reverses the roles ofthe input andoutput chipsandrepeatsthetest.
The connection between the two 8255's is done with an external cable (a loopback cable!).
8255LOOP will detect most common I/O port problems including stuck bits, shorts, and opens.
8255LOOP is not very smart about major problems like incorrect port addresses, missing loopback
cablesetc., andwillcheerfullyreport bit errorsevenifno4I24M card ispresent.
To use 8255LOOP you must have a 50 conductor flat cable with female headers on each end.
Because the 4I24M has three I/O connectors, you must run 8255LOOP with 2 different cable
arrangementsFirstconnectP3andP1togetherwiththeflatcable.Makesurethatthecableisproperly
polarized (pin1 to pin 1). Then run 8255LOOP. Next connect the loopback cable to P1 and P2, and
run8255LOOPagain.
8255LOOP is invoked with 2 hexadecimal addresses on the command line. These are the
addresses ofthetwo 8255'sthat willbe tested. Ifa 4I24M isset to itsdefault(0200H)address,andhas
a (good) loopback cable installed, thefollowing sequence of commands will do a fairly thorough test
of thecard.
(ConnectloopbackcabletoP3andP1)
8255LOOP 200 204
(connectloopbackcabletoP1andP2)
8255LOOP 204 208
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4I24M USER'S MANUAL

REFERENCE INFORMATION
SPECIFICATIONS
MIN MAX UNIT
POWER SUPPLY
Voltage 4.5 5.5 V
Supply current --- 50 mA (no ext. load)
BUS LOADING:
Input capacitance --- 15 pF
Input leakage current --- 5 uA
Output drive capability 150 --- pF
Output sink current 12 --- mA
I/O PORT LOADING:
Input logic low -.3 .8 V
Input logic high 2.0 5.5 V
Output low --- .4 V 2.5 mA sink
Output high 3.0 --- V 2.5 mA source
ENVIRONMENTAL:
Operating temperature range
-I version -40 +85 oC
-C version 0 +70 oC
Relative humidity 0 90 Percent
Non-condensing
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4I24M USER'S MANUAL

REFERENCE INFORMATION
WARRANTY
Mesa Electronics warrants the products it manufactures to be free effects in material and
workmanship under normal use and service for the period of 2 years from date of purchase. This
warranty shall not apply to products which have been subject to misuse, neglect, accident, or
abnormalconditionsofoperation.
In the event of failure of a product covered by this warranty, Mesa Electronics, will repair any
product returned to Mesa Electronics within 2 years of original purchase, provided the warrantor's
examination discloses to its satisfaction that the product was defective. The warrantor may at its
option,replacetheproductinlieuofrepair.
Withregardto anyproductreturnedwithin2yearsofpurchase,saidrepairsorreplacementwillbe
made without charge. If the failure has been caused by misuse, neglect, accident, or abnormal
conditions ofoperation, repairs willbe billed at a nominalcost.
THE FOREGOING WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES,
EXPRESS OR IMPLIED. INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS, OR ADEQUACY FOR ANY
PARTICULAR PURPOSE OR USE. MESA ELECTRONICS SHALL NOT BE LIABLE FOR
ANY SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WHETHER IN
CONTRACT,TORT,OROTHERWISE.
Ifanyfailureoccurs, thefollowingstepsshould betaken:
1. Notify Mesa Electronics, giving full details of the difficulty. On receipt of this information,
service data, or shipping instructions willbe forwarded toyou.
2. On receipt of the shipping instructions, forward the product, in its original protective
packaging, transportation prepaid to Mesa Electronics. Repairs willbe made at MesaElectronicsand
theproductreturnedtransportationprepaid.
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4I24M USER'S MANUAL

REFERENCE INFORMATION
SCHEMATICS
Page 19
4I24M USER'S MANUAL