National Instruments 6583R User manual

NI 6583R User Guide and Specifications
The NI 6583R is a single-ended and differential signaling device designed to work in conjunction with
your NI FlexRIO™FPGA module. The NI 6583 is available in two versions: one with low-voltage
differential signals (LVDS) and another with multipoint low-voltage differential signals (MLVDS). The
term, differential, in this document refers to both LVDS and MLVDS signals unless otherwise specified.
This document contains signal information and specifications for the NI 6583R, which is composed of
an NI FlexRIO FPGA module and the NI 6583. This document also contains tutorial sections that
demonstrate how to acquire data using a LabVIEW FPGA example VI and how to create and run your
own LabVIEW project with the NI 6583R.
Contents
How to Use Your NI FlexRIO Documentation Set ............................................................................. 3
Front Panel and Connector Pinouts ..................................................................................................... 4
Pin and Signal Tables .......................................................................................................................... 5
Block Diagrams ................................................................................................................................... 7
Connecting Cables and Accessories .................................................................................................... 12
Using Accessories................................................................................................................................ 12
Using Your NI 6583R with a LabVIEW FPGA Example VI.............................................................. 17
Creating a LabVIEW Project and Running a VI on an FPGA Target ................................................. 19
NI 6583 Component-Level Intellectual Property (CLIP) .................................................................... 23
Specifications....................................................................................................................................... 25
Compliance and Certifications............................................................................................................. 29
Where to Go for Support ..................................................................................................................... 30

NI 6583R User Guide and Specifications 2 ni.com
Note Before configuring your NI 6583R, you must install the appropriate software and hardware.
Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation
instructions. Figure 1 shows an example of a properly connected NI FlexRIO device.
Figure 1. NI 6583R
Note NI 6583R refers to the combination of your NI 6583 adapter module and your NI FlexRIO
FPGA module. NI 6583 refers only to your NI 6583 adapter module.
NI 6583 + NI FlexRIO FPGA Module = NI 6583R
NI 6583 NI 6583

©National Instruments Corporation 3 NI 6583R User Guide and Specifications
How to Use Your NI FlexRIO Documentation Set
Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set.
Figure 2. How to Use Your NI FlexRIO Documentation Set
Table 1. NI FlexRIO Documentation Locations and Descriptions
Document Location Description
NI FlexRIO FPGA
Module Installation
Guide and Specifications*
Available in your FPGA module
hardware kit and from the Start Menu.
Contains installation instructions for your
NI FlexRIO system and specifications for your
FPGA module.
NI Adapter Module User
Guide and Specifications*
Available in your adapter module
hardware kit and from the Start Menu.
Contains signal information, examples, and
specifications for your adapter module.
LabVIEW FPGA Module
Help*
Embedded in LabVIEW Help.Contains information about the basic functionality of
LabVIEW FPGA Module.
NI FlexRIO Help*Embedded in LabVIEW FPGA
Module Help.
Contains FPGA module, adapter module, and CLIP
configuration information.
LabVIEW Examples Available in NI Example Finder. Contains examples of how to run FPGA VIs and
Host VIs on your device.
Other useful information on ni.com
ni.com/ipnet Contains LabVIEW FPGA functions and intellectual property to share.
ni.com/flexrio Contains product information and data sheets for NI FlexRIO devices.
* These documents are also available at ni.com/manuals.
LabVIEW FPGA
Module Help
NI FlexRIO
Help
LabVIEW
Examples
INSTALL Hardware
and Software
CONNECT Signals
and Learn About
Your Adapter
Module
LEARN About
LabVIEW FPGA
Module
PROGRAM Your
NI FlexRIO System
in LabVIEW FPGA
Module
NI FlexRIO FPGA Module
Installation Guide and Specifications
NI FlexRIO Adapter Module
User Guide and Specifications
Are
You New to
LabVIEW FPGA
Module?
Yes No
No

NI 6583R User Guide and Specifications 4 ni.com
Front Panel and Connector Pinouts
Figure 3 shows the digital data and control (DDC) connector pin assignments for the NI 6583. DDC A
contains the single-ended lines and DDC B contains the differential lines.
Figure 3. NI 6583 Connector Pin Assignments
Caution Connections that exceed any of the maximum ratings of input or output signals on the
NI 6583R can damage the device and the chassis. NI is not liable for any damage resulting from such
signal connections. For the maximum input and output ratings for each signal, refer to the
Specifications section of this document.
Digital Data and Control B (DDC B)
LVDS
NI 6583
GND
PFI 1+
GND
PFI 2+
GND
PFI 3+
GND
GND
DIO 0+
GND
DIO 1+
GND
DIO 2+
GND
DIO 3+
GND
DIO 4+
GND
DIO 5+
GND
DIO 6+
GND
DIO 7+
GND
DIO 8+
GND
DIO 9+
GND
DIO 10+
GND
DIO 11+
GND
DIO 12+
GND
DIO 13+
GND
DIO 14+
GND
DIO 15+
GND
GND
GND
GND
GND
PFI 1–
PFI 2–
PFI 3– / GND
DIO 0–
DIO 1–
DIO 2–
DIO 3–
DIO 4–
DIO 5–
DIO 6–
DIO 7–
DIO 8–
DIO 9–
DIO 10–
DIO 11–
DIO 12–
DIO 13–
DIO 14–
DIO 15–
1
3
2
4
6
5
7
98
10
12
11
13
15
14
16
18
17
19
21
20
22
24
23
25
27
26
28
30
29
31
3332
34
36
35
37
39
38
40
42
41
43
4544
46
48
47
49
51
50
52
54
53
55
57
56
58
6059
61
63
62
64
66
65
67
6968
70
72
71
73
RESERVED
RESERVED
DDC CLK OUT–
DDC CLK OUT+
RESERVED
RESERVED
STROBE–
STROBE+
RESERVED
RESERVED
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
DDC CLK OUT
GND
DIO 1
PFI 3
DIO 3
GND
DIO 5
PFI 1
DIO 7
GND
DIO 9
GND
DIO 11
GND
DIO 13
GND
DIO 15
GND
DIO 17
GND
DIO 19
GND
DIO 21
GND
DIO 23
RESERVED
DIO 25
GND
DIO 27
GND
DIO 29
GND
DIO 31
GND
STROBE
GND
DIO 0
PFI 2
DIO 2
GND
DIO 4
RESERVED
DIO 6
GND
DIO 8
GND
DIO 10
GND
DIO 12
RESERVED
DIO 14
GND
DIO 16
GND
DIO 18
GND
DIO 20
GND
DIO 22
GND
DIO 24
GND
DIO 26
GND
DIO 28
GND
DIO 30
Digital Data and Control A (DDC A)
Single-ended

©National Instruments Corporation 5 NI 6583R User Guide and Specifications
Note If you design a custom cabling solution with the DDC B differential connector (779157-01)
and NI SHB12X-B12X cable (192344-01), the NI 6583 pinout is reversed at the end connector.
For example, the signal shown on pin 1 shown in Figure 3 maps to pin 73 at the end connector.
Pin and Signal Tables
Table 2 contains pin location and single-ended signal information for DDC A on the NI 6583.
Table 2. NI 6583 DDC A Connector Pins
Signal Name Pin(s) Signal Type Signal Description
DDC CLK OUT 33 Clock Terminal for the single-ended exported Sample clock.
STROBE 67 Clock External Sample clock source that can be used for source
synchronous acquisition.
DIO <0..31> 1, 3, 5, 7, 9, 11, 13, 15,
17, 19, 21, 23, 25, 27,
29, 31, 35, 37, 39, 41,
43, 45, 47, 49, 51, 53,
55, 57, 59, 61, 63, 65
Data Bidirectional single-ended digital I/O data channels
0 through 31.
PFI <1..3> 26, 30, 64 Control/Data Bidirectional single-ended digital I/O trigger channels
1 through 3.
GND 2, 4, 6, 10, 12, 14, 16,
18, 20, 22, 24, 28, 32,
34, 36, 38, 40, 42, 44,
46, 48, 50, 54, 56, 58,
62, 66, 68
Ground Ground reference for signals.
RESERVED 8, 52, 60 —These terminals are reserved for future use. Do not connect
to these pins.

NI 6583R User Guide and Specifications 6 ni.com
Table 3 contains pin location and differential signal information for DDC B on the NI 6583.
Table 3. NI 6583 DDC B Connector Pins
Signal Name Pin(s) Signal Type Signal Description
DDC CLK OUT+ 65 Clock Positive terminal for the differential exported Sample clock.
DDC CLK OUT– 66 Clock Negative terminal for the differential exported Sample clock.
STROBE+ 62 Clock Positive external Sample clock source that can be used for
dynamic acquisition.
STROBE– 63 Clock Negative external Sample clock source that can be used for
dynamic acquisition.
DIO <0..15>+ 14, 17, 20, 23, 26,
29, 32, 35, 38, 41,
44, 47, 50, 53, 56,
59
Data Positive bidirectional digital I/O data channels 0 through 15.
DIO <0..15>– 15, 18, 21, 24, 27,
30, 33, 36, 39, 42,
45, 48, 51, 54, 57,
60
Data Negative bidirectional digital I/O data channels 0 through 15
PFI <1..3>+ 2, 5, 8 Control Positive bidirectional digital I/O trigger channels 1 through 3.
PFI <1..3>– 3, 6, 9 Control Negative bidirectional digital I/O trigger channels 1 through 3.
GND 1, 4, 7, 10, 13, 16,
19, 22, 25, 28, 31,
34, 37, 40, 43, 46,
49, 52, 55, 58, 61,
64, 67, 70, 73
Ground Ground reference for signals.
RESERVED 11, 12, 68, 69, 71,
72
—These terminals are reserved for future use. Do not connect
to these pins.

©National Instruments Corporation 7 NI 6583R User Guide and Specifications
Block Diagrams
Figures 4 through 7 show the data flow through the NI 6583R. Single-ended data lines use standardized
voltage levels to interpret data as either a binary zero or a one in high-speed digital data transfers.
Differential data lines provide a low-noise, low-power, low-amplitude differential method for
high-speed digital data transfer.
Figure 4. Clock Input Signals
Figure 5. Differential Data and PFI Lines
DDC A STROBE
UserGclkLvds on
NI FlexRIO
FPGA Module
(I/O Module Clock 1)
UserGclkLvttl on
NI FlexRIO
FPGA Module
(I/O Module Clock 0)
DDC B STROBE
DDC B STROBE
100 Ω
Data from
NI FlexRIO
FPGA Module
(GPIO Output)
Direction Control
from NI FlexRIO
FPGA Module
(GPIO Direction)
Data to
NI FlexRIO
FPGA Module
(GPIO Input)
DDC B Channel
DDC B Channel
100 Ω

NI 6583R User Guide and Specifications 8 ni.com
Figure 6. Single-Ended Data and PFI Lines
Figure 7. Clock Output Signals
Data to and from
NI FlexRIO
FPGA Module
(GPIO I/O)
Direction Control
from NI FlexRIO
FPGA Module
(GPIO Direction)
DDC A Channel
50 Ω
Clock from
NI FlexRIO
FPGA Module
(GPIO Output)
Output Enable
from NI FlexRIO
FPGA Module
(GPIO Direction)
Clock from
NI Flex RIO
FPGA Module
(GPIO Output)
Output Enable
from NI FlexRIO
FPGA Module
(GPIO Direction)
DDC B CLK OUT
DDC B CLK OUT
100 Ω
DDC A CLK OUT
50 Ω

©National Instruments Corporation 9 NI 6583R User Guide and Specifications
Tables 4 and 5 list the NI 6583 connector signals and corresponding NI FlexRIO FPGA module signals
necessary for designing custom component-level IP (CLIP). The _CC suffix on the single-ended and
differential signals identifies channels that are capable of receiving a regional clock. Refer to the Block
Diagrams section of this document for more information about connecting signals from the NI 6583 to
the FPGA module.
Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals
NI 6583 NI FlexRIO FPGA Module
Connector Signal Name GPIO I/O GPIO Direction
DDC A (Single-ended I/O) DIO 0 GPIO_16_n GPIO_16
DIO 1 GPIO_2_n GPIO_2
DIO 2 GPIO_19_n GPIO_19
DIO 3 GPIO_5_n_CC GPIO_5_CC
DIO 4 GPIO_20_n GPIO_20
DIO 5 GPIO_4_n_CC GPIO_4_CC
DIO 6 GPIO_7_n_CC GPIO_7_CC
DIO 7 GPIO_3_n GPIO_3
DIO 8 GPIO_23_n_CC GPIO_23_CC
DIO 9 GPIO_6_n_CC GPIO_6_CC
DIO 10 GPIO_22_n GPIO_22
DIO 11 GPIO_21_n GPIO_21
DIO 12 GPIO_25_n_CC GPIO_25_CC
DIO 13 GPIO_10_n GPIO_10
DIO 14 GPIO_24_n_CC GPIO_24_CC
DIO 15 GPIO_9_n GPIO_9
DIO 16 GPIO_12_n GPIO_12
DIO 17 GPIO_8_n GPIO_8
DIO 18 GPIO_27_n GPIO_27
DIO 19 GPIO_28_n GPIO_28
DIO 20 GPIO_11_n GPIO_11
DIO 21 GPIO_26_n_CC GPIO_26_CC
DIO22 GPIO_30_n GPIO_30
DIO 23 GPIO_15_n GPIO_15
DIO 24 GPIO_29_n GPIO_29
DIO 25 GPIO_14_n GPIO_14

NI 6583R User Guide and Specifications 10 ni.com
Note For the DIO and PFI lines, drive the GPIO Direction high for output and low for input.
For CLK OUT, drive the GPIO Direction high for enable and low for disable.
DDC A (Single-ended I/O) DIO 26 GPIO_50_n GPIO_50
DIO 27 GPIO_13_n GPIO_13
DIO 28 GPIO_32_n GPIO_32
DIO 29 GPIO_31_n GPIO_31
DIO 30 GPIO_49_n GPIO_49
DIO 31 GPIO_33_n GPIO_33
PFI 1 GPIO_0_n GPIO_0
PFI 2 GPIO_18_n GPIO_18
PFI 3 GPIO_1_n GPIO_1
STROBE GClk_SE —
CLK OUT GPIO_17_n GPIO_17
(as enable)
Table 4. NI 6583 Single-Ended Signals and NI FlexRIO FPGA Module Signals (Continued)
NI 6583 NI FlexRIO FPGA Module
Connector Signal Name GPIO I/O GPIO Direction

©National Instruments Corporation 11 NI 6583R User Guide and Specifications
Table 5. NI 6583 Differential Signals and NI FlexRIO FPGA Module Signals
NI 6583 NI FlexRIO FPGA Module
Connector Signal Name GPIO Input GPIO Output GPIO Direction
DDC B
(Differential I/O)
DIO 0+/– GPIO_48 GPIO_47_n GPIO_48_n
DIO 1+/– GPIO_44_n GPIO_45 GPIO_45_n
DIO 2+/– GPIO_41 GPIO_40_n_CC GPIO_40_CC
DIO 3+/– GPIO_61 GPIO_60_n GPIO_60
DIO 4+/– GPIO_62 GPIO_61_n GPIO_62_n
DIO 5+/– GPIO_64 GPIO_63_n GPIO_63
DIO 6+/– GPIO_42 GPIO_42_n GPIO_41_n
DIO 7+/– GPIO_56_CC GPIO_55_n GPIO_56_n_CC
DIO 8+/– GPIO_54_n GPIO_54 GPIO_55
DIO 9+/– GPIO_39_n_CC GPIO_39_CC GPIO_38_n_CC
DIO 10+/– GPIO_58_CC GPIO_57_n_CC GPIO_57_CC
DIO 11+/– GPIO_59_CC GPIO_58_n_CC GPIO_59_n_CC
DIO 12+/– GPIO_51_n GPIO_51 GPIO_52
DIO 13+/– GPIO_36 GPIO_35_n GPIO_35
DIO 14+/– GPIO_53_n GPIO_53 GPIO_52_n
DIO 15+/– GPIO_37_CC GPIO_36_n GPIO_37_n_CC
PFI 1+/– GPIO_43_n GPIO_43 GPIO_44
PFI 2+/– GPIO_47 GPIO_46_n GPIO_46
PFI 3+/– GPIO_65_n GPIO_65 GPIO_64_n
STROBE+/– GClk_LVDS — —
CLK OUT+/– —GPIO_34_n GPIO_34
(as enable)

NI 6583R User Guide and Specifications 12 ni.com
Connecting Cables and Accessories
Use an NI SHC68-C68-D4 shielded cable (NI part number 781013-01) for connections to the DDC A
connector. The NI SHC68-C68-D4 is designed for single-ended, high-speed digital signal transmission.
The cable is shielded, with individual microcoaxial 50 Ω lines for each signal.
Use an SHB12X-B12X shielded cable (NI part number 192344-01) for connections to the DDC B
connector. This cable is designed for differential, high-speed digital signal transmission.
Caution The NI 6583R must be operated with shielded cables and shielded accessories to ensure
compliance with the Electromagnetic Compatibility (EMC) requirements defined in the
Specifications section of this document. Do not use unshielded cables or accessories unless they
are installed in a shielded enclosure with properly designed and shielded input/output ports and
connected to the NI 6583R using a shielded cable. If unshielded cables or accessories are not
properly installed and shielded, the EMC specifications for the NI 6583R are no longer guaranteed.
The following NI cables and accessories are not properly shielded for EMC-compliant use with the
NI 6583:
• NI CB-2162 single-ended digital I/O accessory
• NI SHC68-H1X38 high-speed digital flying-leads cable accessory
• NI SMA-2164 prototyping accessory for NI 656X
• NI SHB12X-H3X24 differential flying-lead/LA cable for HSDIO
Using Accessories
Note Whether you use NI cables and accessories or design your own, you should properly terminate
cables to avoid improper measurements caused by signal reflections, overshoot, and undershoot.
Single-Ended Accessories
NI recommends using the NI CB-2162 single-ended digital I/O accessory to access the signals on the
68-pin DDC A connector and to terminate the DIO channels. The NI CB-2162 also provides a platform
for circuit prototyping and DUT testing. The NI CB-2162 is specifically designed for use with
single-ended devices. For more information about the NI CB-2162, refer to the NI CB-2162 User Guide.
NI also offers the NI SMB-2163 breakout box for National Instruments single-ended digital waveform
generator/analyzers. The NI SMB-2163 offers coaxial SMB connectors for each channel on the DDC A
connector, providing an easy way to connect to other devices for testing and debugging. For more
information about the NI SMB-2163, refer to the NI SMB-2163 User Guide.

©National Instruments Corporation 13 NI 6583R User Guide and Specifications
Figures 8 and 9 show how to connect the single-ended DDC A connector and the NI CB-2162 and
NI SMB-2163, respectively, using the NI SHC68-C68-D4 cable.
Figure 8. Connecting the NI CB-2162 Accessory
Figure 9. Connecting the NI SMB-2163 Accessory
1 PXI/PXI Express Chassiswith NI 6583R
2NISHC68-C68-D4 Cable
3NI CB-2162 Accessory
1 PXI/PXI Express Chassiswith NI 6583R
2NISMB-2163Accessory
3NI SHC68-C68-D4 Cable
NI PXI-6551
50MHz Digital I/O
DIG I TA L DATA & CON T R O L
ACCESS ACTIVE
1
3
2
J15
J5
J6
NI PXI-1042
DIG I TA L DATA & CO N T R O L
2
3
NIPXI-6551
50MHz Digital I/O
DIGITALDATA& CONTROL
ACCESS ACTIVE
1
NI PXI-1042
DIGITALDATA& CONTROL

NI 6583R User Guide and Specifications 14 ni.com
The NI SHC68-H1X38 cable is a single-ended cable that breaks out each single-ended signal into
two 0.1 inch header receptacles, one receptacle each for the signal and ground. The NI SHC68-H1X38
cable provides an easy way to connect NI single-ended high-speed digital signals to various types of
devices and circuits for interfacing, testing, or analysis.
This cable offers connectivity similar to that found on a typical logic analyzer, so you can use it in logic
analyzer-type applications. Unlike a typical logic analyzer, however, this cable also allows for
simultaneous pattern generation and acquisition so that you can use it in stimulus/response applications as
well. The following figure shows the single-ended digital flying lead cable.
Figure 10. Single-Ended Flying Lead Cable Parts Locator Diagram
1Lead Pairs2 Removable Sleeving 368-Pin DDC A Connector
1
2
3

©National Instruments Corporation 15 NI 6583R User Guide and Specifications
Differential Accessories
The NI SMA-2164 test fixture is a breakout box for differential signals. This fixture provides an easy
way to connect to other devices for testing and debugging. For more information about using the
NI SMA-2164, refer to the NI SMA-2164 User Guide.
Figure 11 shows how to connect the differential DDC B connector to the NI SMA-2164 using the
NI SHB12X-B12X cable.
Figure 11. Connecting the NI SMA-2164 Accessory
1 PXI/PXI Express Chassiswith an NI 6583R
2NISHB12-B12X Cable
3NI SMA-2164
NI PXI-6561
100MHz LVDS DIO
DIGITALDATA& CONTROL
ACCESS ACTIVE
1
2
NI PXI-1042
3
STROBE
CLK_LVPECL
+
+
IO_3
+
–
IO_7
IO_10
I
IO_6
IO_11
IO_13
MADEIN U.S.A.
IO_15
ASSY19253 3A- 01
+ –
+
–
+
+
+
–
–
+
–
–
–
–
IO_12
–
–
+
+
–
+
IO_4
IO_5
IO_8
IO_2
IO_9
–
+
–
+
+
–
IO_1
+
–
–
+
+
PFI_3
CLK_LVDS
+
PFI_2
+
–
+ –
PFI_1
VOS
VOS
VOS
VOS
VOS
VOS
VOS
VOS
VOS
VOS
VOS
IO_0
VOS
VOS
–
+
S/N
–
VOS
VOS
–
VOS
VOS
VOS
VOS
VOS
VOS
61 70
40 49 19 31 10
73
64 67
52 55
58
43 46 34 37 22 25 28 13 16
1
4 7
1
VOS
NI SMA-2164
DIFFERENTIAL
DIGITAL I/O ACCESSORY
FOR PATENTS:NI.COM/PATENTS
© COPYRIGHT 2005
DIGITALDATA& CONTROL

NI 6583R User Guide and Specifications 16 ni.com
A flying lead cable, the NI SHB12X-H3X24, is also available for differential signals. This cable offers
connectivity similar to that found on a typical logic analyzer, so you can use it in logic analyzer-type
applications. This cable is shown in Figure 12.
Figure 12. NI SHB12X-H3X24 Flying Lead Cable
Creating a Custom Accessory
Many common applications may require you to create a custom accessory to easily access the signals of
your device under test (DUT). If you are creating a custom accessory to use with a device with a VHDCI
DDC connector, you can purchase the mating connector for the VHDCI cable from NI. For more
information about creating these custom accessories, refer to the Interfacing to the NI Digital Waveform
Generator/Analyzer using the VHDCI Connector application note, available by entering rdinwa in the
text field at ni.com/info. If you are designing a custom accessory to use with a device that uses an
InfiniBand connector, you can also purchase this connector.
Note If you design a custom cabling solution with the DDC B differential connector (779157-01)
and SHB12X-B12X shielded cable (192344-01), the NI 6583 pinout is reversed at the end connector.
For example, the signal shown on pin 1 maps to pin 73 at the end connector. Refer to Front Panel
and Connector Pinouts section in this document for more pinout information.
1 Leads(1 × 3Header Receptacle)
2 DDC B Connector
3Removeable Sleeving
1
23

©National Instruments Corporation 17 NI 6583R User Guide and Specifications
Using Your NI 6583R with a LabVIEW FPGA Example VI
Note You must install the software before doing this example. Refer to the NI FlexRIO FPGA
Module Installation Guide and Specifications for more information about installing your software.
The NI FlexRIO Adapter Module Support installation software includes a variety of example projects
to help get you started creating your LabVIEW FPGA program. This section demonstrates how to use
an existing LabVIEW FPGA example project to generate and acquire samples with the NI 6583R.
This example requires the NI SHC68-C68-D4 and the NI SHB12X-B12X shielded cables and the
appropriate accessories for your device. Refer to the Using Accessories section of this document for
more information about accessories.
Note The examples available for your device are dependent on the version of the software and driver
you are using. For information about which software versions are compatible with your device, visit
ni.com/info and enter rdsoftwareversion as the Info Code.
Each NI 6583 example project includes the following items:
• A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware
• A VI that runs on Windows that interacts with the LabVIEW FPGA VI
Note In the LabVIEW FPGA Module software, NI FlexRIO adapter modules are referred to as
IO Modules.
Complete the following steps to run an example VI that generates a waveform on the even channels of
your device and then acquires that waveform on the odd channels of your device.
Hardware Configuration
1. For single-ended acquisition and generation, connect one end of the NI SHC68-C68-D4 shielded
cable to DDC A on the NI 6583 front panel and one end to a single-ended accessory device. For
differential acquisition and generation, connect one end of the NI SHB12X-B12X shielded cable
to DDC B on the NI 6583 front panel and one end to a differential accessory device. Refer to the
Using Accessories section of this document for more information about appropriate accessories for
your device.
2. On your accessory devices, connect the first eight even channels (DIO <0..14>) to the first eight
odd channels (DIO <1..15>).
Software Configuration
1. Launch LabVIEW.
2. In the Getting Started window, click Find Examples to display the NI Example Finder.
3. In the NI Example Finder window, select Hardware Input and Output»FlexRIO»
IO Modules»NI 6583.
4. Select NI 6583 Finite Acquisition and Generation - Simple.lvproj.
5. In the Project Explorer window, open NI 6583 Acquisition and Generation Simple (Host).vi
under My Computer. The host VI opens. The VI uses the NI PXI-7952R as the FPGA target.
If you are not using an NI PXI-7952R, complete the following steps to change the FPGA target.
Note All example projects are configured for RIO0. If your device is not RIO0, you must update
the target device name by right-clicking your device in the Project Explorer window, selecting
Properties, and entering the correct target device name in the Resource box.

NI 6583R User Guide and Specifications 18 ni.com
a. Select Window»Show Block Diagram to open the VI block diagram.
b. On the block diagram, right-click the Open FPGA VI Reference (NI PXI-7952R) function and
select Configure Open FPGA VI Reference.
c. In the Configure Open FPGA VI Reference window, click the Browse Project button in the
Open VI section.
d. In the Select VI window that opens, expand the tree view for your device, select the VI under
your device and click OK.
e. Click OK in the Configure Open FPGA VI Reference window.
f. Save the VI.
6. On the front panel, select appropriate values in the Num Samples, Generation Mode, Generation
Constant, and DDC A Voltage Level controls.
7. Click the Run button to run the VI. The NI 6583R generates a waveform on the even channels of
your device and then acquires that waveform on the odd channels of your device. The front panel
of the host VI displays both the generated and acquired waveforms, as shown in Figure 13. Use the
DDC A and DDC B tabs on the left side of the front panel to toggle between connectors. If the
generated and acquired waveforms match, then the DDC xVerified? indicator illuminates.
Figure 13. NI 6583 Acquisition and Generation Simple (Host) VI Front Panel
8. Close the VI.

©National Instruments Corporation 19 NI 6583R User Guide and Specifications
Creating a LabVIEW Project and Running a VI on an FPGA Target
This section demonstrates how to create a LabVIEW project, an FPGA VI, and a host VI that acquires
and generates single-ended data on the NI 6583R. This exercise also demonstrates how to compile the
FPGA VI on your target and run a VI on the host machine.
Note Disconnect all signals from the NI 6583R connectors before running this VI.
Creating a Project
1. Launch LabVIEW, or if LabVIEW is already running, select File»New.
2. In the New dialog box, select Project»Empty Project. Click OK. The new project opens in the
Project Explorer window.
3. Save the project as Static RW with Voltage.lvproj.
Creating an FPGA Target VI
1. In the Project Explorer window, right-click My Computer and select New»Targets and
Devices.
2. In the Add Targets and Devices on My Computer window, select the Existing Target or Device
button and expand the FPGA Target. The target is displayed.
3. Select your device and click OK. The target and target properties are loaded into the project tree.
4. In the Project Explorer window, right-click the FPGA target and select New»VI. A blank VI
opens.
5. Select Window»Show Block Diagram to open the block diagram window.
6. In the Project Explorer window, select FPGA Target (RIOx, PXI-79xxR).
7. Right-click IO Module and select Properties. In the General category, select
National Instruments: NI 6583, and you can see the available component-level IP (CLIP) for the
NI 6583 in the Component Level IP pane. If the category information is dimmed, select the Enable
IO Module checkbox.
Note For more information about CLIP items for the NI 6583, refer to the NI 6583
Component-Level Intellectual Property (CLIP) section of this document.
8. Select NI 6583 Basic Connector to use the connector-based CLIP. Click OK.
9. In the Project Explorer window, expand the IO Module (NI 6583 : NI 6583 Basic Connector)
tree view.
10. Select SE_Data_Dir, SE_Data_Rd,SE_Data_Wr, Voltage_Family,Set_Voltage_Family,
and Set_Voltage_Done, and drag them onto the block diagram.
Tip If you hold down the <Ctrl> key, you can select multiple options at one time.
11. Add a While Loop around all six data nodes, as shown in Figure 14.
12. Wire a False constant to the stop condition of the While Loop.
13. Wire indicators from the output terminals of the IO Module\SE_Data_Rd and
IO Module\Set_Voltage_Done nodes.
14. Wire controls from the input terminals of the IO Module\Set_Voltage_Family,
IO Module\SE_Data_Dir,and IO Module\SE_Data_Wr nodes.
15. On the Functions palette, choose Select a VI.
16. In the Select the VI to Open window, navigate to Program Files\National Instruments\
<LabVIEW
x >\examples\FlexRIO\IO Modules\NI 6583\FiniteAcqGenSimple.

NI 6583R User Guide and Specifications 20 ni.com
17. Select NI 6583 Voltage Level. Click OK to drag and place the file on your block diagram.
18. Right-click the Voltage Level control and select Change to Control.
19. Wire the Voltage Level control to the IO Module\Voltage_Family node, as shown in Figure 14.
20. Add a case structure around the IO Module\SE_Data_Dir,IO Module\SE_Data_Rd,and
IO Module\SE_Data_Wr nodes driven by IO Module\Set_Voltage_Done to prevent input
and output access while the voltage is changing.
Your block diagram should now resemble the block diagram in Figure 14.
Figure 14. Static RW with Voltage (FPGA).vi Block Diagram
21. Save the VI as Static RW with Voltage (FPGA).vi.
22. Close the VI.
23. In the Project Explorer window under My Computer, expand the tree view for your device,
right-click the Static RW with Voltage (FPGA).vi and select Compile to compile the files for
your target.
The Generating Intermediate Files window opens and displays the compilation progress.
The LabVIEW FPGA Compile Server window opens and runs. The compilation takes several
minutes.
24. When the compilation finishes, click the Stop Server button.
25. Click OK in the Successful Compile Report window. Close the VI without saving changes.