North Atlantic 68C3 User manual

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 1 of 330
68C3 3U Open VPX
MULTI-FUNCTION I/O CARD
OPERATIONS MANUAL

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 2 of 330
MODEL
68C3
3U, OPENVPX, MULTI-FUNCTION I/O CARD
Features
Multiple functions on a single slot, 3U, OpenVPX card
OpenVPX Slot Profile: SLT3-PAY-2F2T-14.2.5
User can specify three different function modules
Automatic background BIT testing continually checks
and reports the health of each channel
Control via Dual Gig-E interfaces
sRIO (1x) or PCIe (x1) options
Front and/or Rear I/O
Conduction or Convection cooled versions
Commercial and Rugged applications
Software Support Kit and Drivers are available
Description
The 68C3 is a single slot, 3U, OpenVPX (0.8” pitch) multi-function I/O
and serial communications card. Gigabit Ethernet (Gig-E) and High
Speed PCI Express (PCIe) or Serial RapidIO (sRIO) control interface
selections enable users to confidently take advantage of the OpenVPX
form-factor, offering higher speed switched fabric communication
options.
The motherboard contains three independent module slots, each of
which can be populated with a function-specific module, and can now
be controlled by the Gig-E and/or sRIO or PCIe. This enhanced
motherboard using multiple DSPs enables higher processing power
and dedicated pre-processing and control for each module function.
This unique design eliminates the need formultiple, specialized, single-
function cards by providing a single-board solution fora broad assortment
of programmable, multi-channel signal interface I/O modules such as:
Digital(TTL/CMOS, Differential, Discrete, Relay); Analog(A/D, D/A, RTD,
Strain Gage, Isolated Power Supply); Positional/Motion Control
(Synchro/Resolver/ LVDT/RVDT Measurement/ Simulation, AC
Reference, Encoder/Counter).
In addition, the 68C3 incorporates communication modules such as
RS-232/422/423(188C)/485, MIL-STD-1553, CANBus and ARINC
429/575. This approach increases packaging density, saves enclosure
slots and reduces power consumption. Additional enhancements
include FIFO data buffering for A/D, D/A, S/D and LVDT functions.
(Please see all available functions on the following page.)
NAI’s flexible, leading-edge, fully programmable and continuous background built-in-test (BIT) feature is always enabled and
continually checks the health of each channel. If a fault is detected, it is immediately reported and the specific channel is
identified with no downtime for troubleshooting. Testing is totally transparent to the user, requires no external programming, and
has no effect on the standard operation of the card.
Proudly made
in the USA

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 3 of 330
General Board Specification
Power: +5VDC, (±12VDC for select modules) Operating Temp: 0°C to 70°C or -40°C to 85°C Size: 100mm x 20mm x 160mm (3U)
Available Function Modules
(GEN3 (A/E) Platforms)
Note 1 –Indicates wide selection (See part number in Operations Manual)
Note 2 –Contact factory for availability
Note 3 –Additional channels on some platform front I/O (check pinouts)
A/D Converter
Module Channels Input Scaling Resolution Accuracy(±) Sampling (programmable)
C1 10 1.25,2.5,5 or 10 VDC 16-bit 0.05% FS 200 KHz max
C2 10 5,10,20 or 40 VDC 16-bit 0.1% FS 200 KHz max
C3 10 0-25 mA 16-bit 0.1% FS 200 KHz ma
C4 10 6.25,12.5,25 or 50 VDC 16-bit 0.1% FS 200 KHz max
CA 10 (Channels 1-6 are C2 type and Channels 7-10 are C3 type)
D/A Converter
Module Channels Output Range Resolution Accuracy (±) Settling time
F1 10 10 or 0-10 VDC 16-bit 0.05% FS 15s max
F3 10 5 or 0-5 VDC 16-bit 0.05% FS 10s max
F5 4 20 or 0-20 VDC 16-bit 0.05% FS 10s max
J3 10 1.25 or 0-1.25 VDC 16-bit 0.05% FS 10s max
J5 10 2.5 or 0-2.5 VDC 16-bit 0.05% FS 10s max
J8 4 20 to 80 VDC 16-bit 0.15% FS 350s max
Thermocouple
Module Channels Update rate Resolution Accuracy (±) Thermocouple Interface
G326 4.17 –470 Hz 24-bit 0.75 –2.0 °C NIST J,K,T,E,N,B,R,S & ±100 mV)
RTD
Module Channels Update rate Resolution Accuracy (±) Interface
G4 6 16.7 Hz/channel 16-bit 0.05% FS 2, 3 or 4 wire
Strain Gage
Module Channels Update rate Resolution Accuracy (±) Interface
G524 4.7 Hz –4.8KHz 16-bit 0.1% FS Conventional 4-Arm Bridge
Encoder/Counter
Module Channels Signal Voltage Resolution Modes
E7 4 RS422 / 24 VDC 32-bit Encoder (SSI, A-Quad-B), Counter (up/down)
L(R)VDT/D
Module Channels Frequency Resolution Accuracy (±) Interface
L14 360 Hz to 20 KHz 16-bit 0.025% FS 2 or 3/4 wire
SYN(RSL)/D
Module Channels Frequency Resolution Accuracy (±) Tracking Rate
S14 50 Hz to 20 KHz 16-bit 1 arc-min 190 RPS
D/SYN(RSL)
Module Channels Frequency Resolution Accuracy (±) Power
613 47 Hz –10 KHz 16-bit 0.1° 0.25 VA / channel (max.)
D/L(R)VDT
Module Channels Frequency Resolution Accuracy (±) Power
513 47 Hz –10 KHz 16-bit 0.2% FS 0.1 VA / channel (max.)
I/O, TTL/CMOS
Module Channels Input Range Output level Programmable
D7 16 0 –5.5 V TTL/CMOS Input or Output
I/O, Differential
Module Channels Input Range (422) Input Range (485) Output Range (422/485)
D8 11 (16)3 -10V to +10V -7V to +12V -0.25V to +5V
I/O, Discrete
Module Channels Input Range Output Range Programmable Notes
K6 (v4) 16 0 –60 VDC 0 –60 VDC Input or Output (500 mA –2 A) (source/sink)
K7 12 (16)3 ±80V ±80V Input or Output Isolated switch (600mA)
Relay
Module Channels Type SW Volt/Current SW Power (max) Notes
KN, KL 4 DPDT (1 CH Form C) 220V / 2A (max) 60W / 62.5 VA KN=non-latch, KL=latching
Serial Communications
Module Channels HW Interface levels support Bit rate (Async/Sync) Tx/Rx Buffer Notes
P8 4 RS-232/422/423(MIL-STD-188C-unbal.)/485 1 / 4 Mbit/s per Ch. 32KB Partial modem
PC 4 Isolated RS422/485 1 / 4 Mbit/s per Ch. 32KB Partial modem
CANBus
Module Channels CAN protocol Message Buffer Data rate (Prog) Notes
P6, PA 4 P6= 2.0A/B / PA=J1939 16K RX/TX 1 Mb/s max. Bosch® IP Core
MIL-STD-1553
Module Channels Operational Modes Onboard RAM Coupled
N7, N8 2 BC,RT, BM, BM/RT 128Kbyte per ch N7 = Transformer / N8 = Direct
ARINC 429/575
Module Channels Frequency Input/output Message Buffer
A4 6 100 KHz or 12.5 KHz RX/TX 256 word Tx/Rx
DC Power Supply
Module Channels Voltage Output VOut Regulation Current Output
V1, V2 1, 2 +/- 15V 1% 450 mA(max)
AC Reference
Module Channels Frequency Accuracy Voltage Power
W11 47 Hz –20KHz 3% 2 –115 Vrms 6 VA (max.)
A/D & Discrete I/O
(Slot 3 only)
Module A/D Channels Input Scaling Resolution Accuracy Sampling
KA 4(multiplexed) 10 VDC 14-Bit 0.1% FS 3 KHz Max
I/O Channels Input Range Output Range Format Resolution
28 0 –50 VDC 0 –50 VDC 12 In/12 Out/4 Prog. 12-bit
Reference (v9)
(Slot 3 only)
Module Channels Frequency Accuracy Voltage Power
W6 1 47 Hz –20 KHz 2% 2 –28 Vrms 5 VA (max)
W7 1 47 Hz –2 KHz 5% 115 Vrms 5 VA (max)

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 4 of 330
SOFTWARE SUPPORT
The ENAIBL Software Support Kit (SSK) is supplied with all system platform based board level products. This
platform’s SSK contents include html format help documentation which defines board specific library functions
and their respective parameter requirements. A board specific library and its source code is provided (module
level ‘C’ and header files) to facilitate function implementation independent of user operating system (O/S).
Portability files are provided to identify Board Support Package (BSP) dependent functions and help port code to
other common system BSPs. With the use of the provided help documentation, these libraries are easily ported to
any 32-bit O/S such as RTOS or Linux.
The latest version of a board specific SSK can be downloaded from our website www.naii.com in the software
downloads section. A Quick-Start Software Manual is also available for download where the SSK contents are
detailed, Quick-Start Instructions provided and GUI applications are described therein. For other operating system
support, contact factory.

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 5 of 330
TABLE OF CONTENTS
....................................................................................................................................................................................1
MODEL 68C3 .............................................................................................................................................................2
3U, OPENVPX, MULTI-FUNCTION I/O CARD .........................................................................................................2
FEATURES ................................................................................................................................................................2
DESCRIPTION ...........................................................................................................................................................2
GENERAL BOARD SPECIFICATION.......................................................................................................................3
Available Function Modules.....................................................................................................................................................3
SOFTWARE SUPPORT.............................................................................................................................................4
SPECIFICATIONS................................................................................................................................................... 22
General –For the Motherboard.............................................................................................................................................22
ARINC 429/575 (Module A4) –Six RX/TX Channels, Configurable......................................................................................22
MIL-STD-1553 (Module N7) –Two Dual/Redundant Channels, Transformer Coupled.........................................................22
MIL-STD-1553 (Module N8) –Two Dual/Redundant Channels, Directly Coupled ................................................................22
CANBus(ModuleP6,PA) –Four CANBus Interfaces...................................................................................................................23
Serial Comms (Module P8) –High Speed, RS-232/422/423(188C)/485...............................................................................23
RS-422/485(ModulePC) –Isolated, Four High Speed RS-422 / 485 Serial Communications....................................................24
A/D (Module C1) –Ten A/D Channels (1.25 to 10.0 VDC FS) Uni or Bipolar........................................................................25
A/D (Module C2) –Ten A/D Channels (5.0 to 40.0 VDC FS) Uni or Bipolar..........................................................................26
A/D (Module C3) –Ten A/D Channels (4-25mA)...................................................................................................................27
A/D (Module C4) –Ten A/D Channels (6.25 to 50.0 VDC FS) Uni or Bipolar........................................................................28
A/D Combo (Module CA) –Six Channels (±40VDC) & Four Channels (4-25mA) .................................................................29
Specifications applicable to channels 1-6 (40 VDC A/D)..................................................................................................29
Specifications applicable to channels 7-10 (4-25mA A/D)................................................................................................29
Specifications applicable to ALL channels:.......................................................................................................................29
I/O (Module D7) –Sixteen TTL Channels—Programmable for I/O.......................................................................................30
TTL Input..........................................................................................................................................................................30
TTL Output........................................................................................................................................................................30
I/O (Module D8) –Eleven (Sixteen*) Differential Multi-Mode Transceiver Channels.............................................................30
Differential Input................................................................................................................................................................30
Differential Output.............................................................................................................................................................30
D/A (Module F1) − Ten D/A Outputs (10 VDC) ...................................................................................................................31
D/A (Module F3) −Ten D/A Outputs (5 VDC) .....................................................................................................................31
D/A (Module F5) − Four D/A High Current Outputs (20VDC at 100 mA).............................................................................32
D/A (Module J3) −Ten D/A Outputs (1.25 VDC).................................................................................................................32
D/A (Module J5) −Ten D/A Outputs (2.5 VDC)...................................................................................................................33
D/A (Module J8) –Four D/A High Voltage Outputs (20 to 80 VDC)................................................................................33
Thermocouple (Module G3) –Six Channel, Thermocouple Measurement Module...............................................................34
RTD (Module G4) –Six Channel RTD Measurement............................................................................................................35
Load/Strain (Module G5) –Four Channel, Load Cell / Strain Gage Module..........................................................................36
DISCRETE (Module K6) (ver. 4) –Sixteen (16) Programmable Discrete I/O Channel..........................................................37
Features: ..........................................................................................................................................................................37
Input Characteristics:........................................................................................................................................................37
Output Characteristics:.....................................................................................................................................................37
General Characteristics:...................................................................................................................................................37
Discrete (Module K7) - Isolated, Progammable, Bi-Directional I/O Switch ............................................................................38
Relay(ModuleKN,KL) –Isolated, Four Independent Relay Channels .......................................................................................39
Combo (Module KA) - 4 A/D Channels, 28 Discrete I/O Channels........................................................................................40
A/D Channels....................................................................................................................................................................40
4 A/D Channels.................................................................................................................................................................40

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 6 of 330
Discrete Channels ............................................................................................................................................................40
28 I/O Channels total, (12 In, 12 Out, 4 programmable In/Out .........................................................................................40
Input Characteristics:........................................................................................................................................................40
Output Characteristics:.....................................................................................................................................................40
General Characteristics:...................................................................................................................................................40
LVDT (Module L*) –Four Isolated LVDT Measurement Channels (2, 3 or 4 Wire)...............................................................41
S/D (Module S*) –Four Isolated Synchro/Resolver Measurement Channels........................................................................41
D/S (Module 6*) –Three Isolated Digital-to-SYN/RSL Ch, 0.25 VA Power Output ................................................................42
DLV (Module 5*) –Three Isolated DLV Stimulus Channels, LVDT or RVDT Outputs...........................................................43
Encoder (Module E7) –Four (4) Isolated SSI, A-Quad-B Encoder / General Counter..........................................................44
SSI Mode..........................................................................................................................................................................44
Incremental Quadrature (A-QUAD-B) Encoder / Counter Mode.......................................................................................44
General.............................................................................................................................................................................44
DC Power Supply (Module V*) - Isolated ±15V DC/DC converter.......................................................................................45
Input..................................................................................................................................................................................45
Output...............................................................................................................................................................................45
Power Input.......................................................................................................................................................................45
AC Reference (Module W6, W7) –Optional, Isolated, On-Board Reference Supply.............................................................46
Reference (Module W*) –AC Source, Isolated, Programmable............................................................................................47
68C3 ADDRESS CONFIGURATION...................................................................................................................... 48
PRODUCT CONFIGURATION AND MEMORY MAP ............................................................................................ 49
68C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING......................................................................50
ARINC 429/575 SIX CHANNEL, TX/RX (MODULE A4) ........................................................................................ 51
Features................................................................................................................................................................................51
ARINC 429/575 Overview .....................................................................................................................................................51
Functional Description...........................................................................................................................................................51
Receive Operation.................................................................................................................................................................52
Transmit Operation................................................................................................................................................................52
Schedule Transmit Commands .............................................................................................................................................53
Message...........................................................................................................................................................................53
Gap...................................................................................................................................................................................53
FixedGap..........................................................................................................................................................................53
Pause ...............................................................................................................................................................................53
Interrupt............................................................................................................................................................................54
Jump.................................................................................................................................................................................54
Stop..................................................................................................................................................................................54
Transient Protection..........................................................................................................................................................54
Built-In-Test ......................................................................................................................................................................54
Loop-Back ........................................................................................................................................................................54
Specifications ........................................................................................................................................................................54
Module Factory Defaults........................................................................................................................................................55
Registers and Delays ............................................................................................................................................................55
Tx (Transmit) Buffer (FIFO)...................................................................................................................................................56
Rx (Receive) Buffer (FIFO)....................................................................................................................................................56
Rx FIFO (Buffer) Threshold...................................................................................................................................................57
Tx FIFO (Buffer) Threshold ...................................................................................................................................................57
Rx FIFO (Buffer) Level (Number of Rx Buffer Words)...........................................................................................................57
Tx FIFO (Buffer) Level (Number of Tx Buffer Words)............................................................................................................57
Channel Control Low.............................................................................................................................................................58
Channel Control High............................................................................................................................................................59
Channel Status......................................................................................................................................................................60
Interrupt Enable.....................................................................................................................................................................61

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 7 of 330
Interrupt Status......................................................................................................................................................................62
Transmit FIFO Rate (Hi+Lo)..................................................................................................................................................62
Mailbox (MBOX) Address Register........................................................................................................................................63
Mailbox (MBOX) Status Register...........................................................................................................................................63
Mailbox (MBOX) Data Register .............................................................................................................................................64
Receive Data Unbuffered Register........................................................................................................................................64
Transmit Trigger Register......................................................................................................................................................65
Transmit Pause Register.......................................................................................................................................................65
Transmit Stop Register..........................................................................................................................................................66
Time Stamp Control Register................................................................................................................................................66
Timestamp Hi + Lo Register..................................................................................................................................................67
Module Reset Register..........................................................................................................................................................67
Memory Page Register..........................................................................................................................................................67
Memory Page Window ..........................................................................................................................................................68
Tx Message Memory Format.................................................................................................................................................68
Tx Schedule Program Memory Format..................................................................................................................................68
Rx Match Memory Layout......................................................................................................................................................69
Async Tx Data (Hi + Lo) ........................................................................................................................................................69
BIT Status Register ...............................................................................................................................................................69
DSP Compile Time................................................................................................................................................................70
Interrupt Vector......................................................................................................................................................................70
MODULE PCI MEMORY MAP –6 CHANNEL ARINC COMMUNICATIONS (A4) ............................................... 71
1553 COMMUNICATIONS (MODULES N7 AND N8) ............................................................................................ 72
Features................................................................................................................................................................................72
Module Memory Map (Length=40000h).................................................................................................................................72
CANBUS CONTROL AREA NETWORK (MODULE P6, PA)................................................................................ 73
Principle of Operation............................................................................................................................................................73
Features................................................................................................................................................................................74
P6 Specific CAN A/B Register Descriptions ..........................................................................................................................75
Control Register (set per channel) (P6 –CAN A/B Only)..................................................................................................75
Acceptance Mask HI (set per channel) (P6 –CAN A/B Only)...........................................................................................75
Acceptance Mask LO (set per channel) (P6 –CAN A/B Only) .........................................................................................76
Acceptance Code HI (set per channel) (P6 –CAN A/B Only)...........................................................................................76
Acceptance Code LO (set per channel) (P6 –CAN A/B Only) .........................................................................................76
FIFO Frame Components (P6 –CAN A/B Only)...............................................................................................................76
MSG_ID4..........................................................................................................................................................................76
MSG_ID3..........................................................................................................................................................................77
MSG_ID2..........................................................................................................................................................................77
MSG_ID1..........................................................................................................................................................................77
Data Size..........................................................................................................................................................................78
DataX................................................................................................................................................................................78
PA Specific J1939 Register Descriptions ..............................................................................................................................79
CH X Control (PA - J1939 only)........................................................................................................................................79
Receive Filter Ch X Priority/PGN_HI (PA - J1939 only)....................................................................................................79
Receive Filter Ch X PGN_LO (PA - J1939 only)...............................................................................................................79
Receive Filter Ch X Dest/Src Address (PA - J1939 only) .................................................................................................79
P6 (CAN A/B) or PA (J1939) Global Register Descriptions...................................................................................................80
Hardware Error Register (Global).....................................................................................................................................80
Last Error Code for Channel X (Global)............................................................................................................................80
Comm Status for Channel X (Global) ...............................................................................................................................81
Ch X Baud / Bit Timing Register (Global) .........................................................................................................................82
Ch X Baud Rate Prescaler Extension Reg (Global)..........................................................................................................83

68C3 Operations Manual
North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 8 of 330
Ch X TX/RX Error Counter (Global)..................................................................................................................................83
Level Control (Global)......................................................................................................................................................83
FIFO Frame (Global) ........................................................................................................................................................83
PGN_HI (Global)...............................................................................................................................................................84
PGN_LO (Global) .............................................................................................................................................................84
Source Address (Global) ..................................................................................................................................................84
Priority (Global).................................................................................................................................................................84
Destination Address (Global)............................................................................................................................................84
Data Size (Global) ............................................................................................................................................................84
Data1..Data250 (Global)...................................................................................................................................................84
Empty (Global)..................................................................................................................................................................84
Vector Address (Global) ...................................................................................................................................................84
MODULE (P6) CANBUS CAN A/B PCI REGISTER MAP..................................................................................... 85
MODULE (PA) CANBUS J1939 PCI REGISTER MAP.......................................................................................... 86
FOUR CHANNEL, SERIAL (RS232/422/485) (MODULE P8) / ISOLATED RS-422/RS-485 (MODULE PC) ...... 87
Serial Communications Specifications..............................................................................................................................89
Communication Module Factory Defaults: Registers and Delays.........................................................................................90
Transmit Buffer......................................................................................................................................................................91
Receive Buffer.......................................................................................................................................................................91
Number of Words Tx Buffer...................................................................................................................................................91
Number of Words Rx Buffer ..................................................................................................................................................92
Protocol.................................................................................................................................................................................92
Clock Mode ...........................................................................................................................................................................92
Interface Levels.....................................................................................................................................................................93
Tx-Rx Configuration Low.......................................................................................................................................................94
Tx-Rx Configuration High ......................................................................................................................................................94
Channel Control Low.............................................................................................................................................................95
Channel Control High............................................................................................................................................................95
Channel Control Extended ....................................................................................................................................................96
Data Configuration.................................................................................................................................................................96
Baud Rate .............................................................................................................................................................................97
Preamble...............................................................................................................................................................................97
Tx Buffer Almost Empty.........................................................................................................................................................97
Rx Buffer Almost Full.............................................................................................................................................................98
Rx Buffer High Watermark.....................................................................................................................................................98
Rx Buffer Low Watermark .....................................................................................................................................................99
HDLC Rx Address/Sync Character........................................................................................................................................99
HDLC Tx Address/Sync Character......................................................................................................................................100
Termination Character.........................................................................................................................................................100
XON Character....................................................................................................................................................................100
XOFF Character..................................................................................................................................................................101
FIFO Status.........................................................................................................................................................................101
Time Out Value....................................................................................................................................................................101
Interrupt Enable...................................................................................................................................................................102
Interrupt Status....................................................................................................................................................................103
Interrupt Vector....................................................................................................................................................................103
Channel Status....................................................................................................................................................................104
FOUR CHANNEL SERIAL COMMUNICATIONS (MODULE P8/PC) PCI MEMORY MAP................................. 105
A/D (MODULES C1, C2, C3, C4 & CA)................................................................................................................ 106
Principle of Operation..........................................................................................................................................................106
Built-In Test (BIT) / Diagnostic Capability............................................................................................................................106

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North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 9 of 330
Data Read...........................................................................................................................................................................107
Range & Polarity..................................................................................................................................................................107
Filter Break Frequency........................................................................................................................................................107
Latch All A/Ds......................................................................................................................................................................107
D0 Test Range ....................................................................................................................................................................107
D0 Test Voltage...................................................................................................................................................................108
Calibration Interval Delay ....................................................................................................................................................108
FIFO Buffer Operational Description ...................................................................................................................................108
FIFO Buffer Data (per channel): .....................................................................................................................................108
Words in FIFO (per channel): .........................................................................................................................................108
Hi-Threshold (per channel):............................................................................................................................................108
Low-Threshold (per channel):.........................................................................................................................................108
Delay (per channel): .......................................................................................................................................................108
FIFO Size (per channel): ................................................................................................................................................109
Sample Rate (per channel):............................................................................................................................................109
Clear FIFO (per channel):...............................................................................................................................................109
Buffer Control (per channel):...........................................................................................................................................109
Trigger Control (per channel):.........................................................................................................................................110
FIFO Status (per channel):.............................................................................................................................................110
Interrupt Enable (per channel):.......................................................................................................................................110
Software Trigger (per channel):......................................................................................................................................111
Clock Rate Input..................................................................................................................................................................111
Test Enable.........................................................................................................................................................................112
Test (D2) Verify ...................................................................................................................................................................112
Active Channels...................................................................................................................................................................112
BIT Status............................................................................................................................................................................112
Open Status ........................................................................................................................................................................113
BIT Status Interrupt Enable.................................................................................................................................................113
Open Status Interrupt Enable..............................................................................................................................................113
BIT Interrupt Vector.............................................................................................................................................................113
Open Interrupt Vector..........................................................................................................................................................113
FIFO Buffer Interrupt Vector................................................................................................................................................113
Interrupt and Status Register Operation/Clarification ..........................................................................................................114
A/D (MODULES C1, C2, C3 & C4) PCI MEMORY MAP...................................................................................... 115
I/O DIGITAL TTL/CMOS (MODULE D7) .............................................................................................................. 116
Principle of Operation..........................................................................................................................................................116
Automatic Background Built-In Test (BIT)/Diagnostic Capability.........................................................................................116
Write Output........................................................................................................................................................................116
Read Input or Output...........................................................................................................................................................117
External VCC Select............................................................................................................................................................117
De-bounce Time..................................................................................................................................................................117
De-bounce LSB...................................................................................................................................................................117
Input/Output Format ............................................................................................................................................................117
Reset Over-Current.............................................................................................................................................................118
Status Indications................................................................................................................................................................118
Interrupt Vectors..................................................................................................................................................................118
Interrupt and Status Register Operation/Clarification ..........................................................................................................119
I/O DIGITAL TTL/CMOS (MODULE D7) PCI MEMORY MAP............................................................................. 120
DIFFERENTIAL MULTI-MODE TRANSCEIVERS (MODULE D8) ...................................................................... 121
Principle of Operation..........................................................................................................................................................121
Automatic Background Built-In Test (BIT) / Diagnostic capability........................................................................................121

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North Atlantic Industries, Inc.
12/19/2014
Rev: 2014-12-19-0947
www.naii.com
Page 10 of 330
Write Output........................................................................................................................................................................121
Read Input or Output...........................................................................................................................................................121
De-bounce Time..................................................................................................................................................................122
De-bounce LSB...................................................................................................................................................................122
Slew Rate Mode..................................................................................................................................................................122
Input Termination Control....................................................................................................................................................122
Input/Output Format ............................................................................................................................................................123
Reset Over-Current.............................................................................................................................................................123
Status Indications................................................................................................................................................................123
Interrupt Vectors..................................................................................................................................................................124
Interrupt and Status Register Operation/Clarification ..........................................................................................................125
I/O (MODULE D8) PCI MEMORY MAP................................................................................................................ 126
D/A (MODULES F & J, EXCEPT J8).................................................................................................................... 127
Principle of Operation..........................................................................................................................................................127
Built-In Test (BIT) / Diagnostic Capability............................................................................................................................127
Data (Write D/A) Output (F1, F3, J3, J5 Modules)...............................................................................................................127
Data (Write D/A) Output (F5 Module Only)..........................................................................................................................127
D/A Polarity .........................................................................................................................................................................128
D/A Wrap Voltage................................................................................................................................................................128
Filter Function......................................................................................................................................................................128
Current Reading..................................................................................................................................................................128
Output Data Trigger.............................................................................................................................................................128
Reset to Zero.......................................................................................................................................................................128
Retry Overload ....................................................................................................................................................................128
Reset Overload....................................................................................................................................................................128
Over Current Override.........................................................................................................................................................129
Power Sup. Ch 1 & 2, Ch 3 & 4...........................................................................................................................................129
Single/Differential Mode Selector Ch 1 & 2, Ch 3 & 4 (For F5 Module Only).......................................................................129
Range Ch. 1 & 2, Ch. 3 & 4 (For F5 Module Only)..............................................................................................................129
D/A FIFO Buffer Operational Description ............................................................................................................................129
D/A Data:........................................................................................................................................................................129
Words in FIFO: ...............................................................................................................................................................130
Hi-Threshold:..................................................................................................................................................................130
Lo-Threshold:..................................................................................................................................................................130
Delay: .............................................................................................................................................................................130
Size:................................................................................................................................................................................130
Sample Rate:..................................................................................................................................................................131
Clear FIFO:.....................................................................................................................................................................131
Buffer Control:.................................................................................................................................................................131
Trigger Control:...............................................................................................................................................................132
FIFO Status: ...................................................................................................................................................................132
Interrupt Enable:.............................................................................................................................................................133
Software Trigger:............................................................................................................................................................133
Clock Rate Input:............................................................................................................................................................133
Test Enable.........................................................................................................................................................................133
D2 Test Verify......................................................................................................................................................................133
BIT Status............................................................................................................................................................................133
Over Current Status.............................................................................................................................................................134
BIT Status Interrupt Enable.................................................................................................................................................134
Over Current Status Interrupt Enable..................................................................................................................................134
BIT Interrupt Vector.............................................................................................................................................................134
Channel X FIFO Interrupt Vector.........................................................................................................................................134

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Over-Current Interrupt Vector..............................................................................................................................................134
Interrupt and Status Register Operation/Clarification ..........................................................................................................135
D/A (MODULE F OR J, EXCEPT J8) PCI MEMORY MAP.................................................................................. 136
HIGH VOLTAGE D/A (MODULE J8).................................................................................................................... 137
Principle of Operation..........................................................................................................................................................137
Built-In-Test (BIT) / Diagnostic Capability............................................................................................................................137
Data (Write D/A) Output ......................................................................................................................................................137
D/A Output Range...............................................................................................................................................................138
D/A Output Polarity..............................................................................................................................................................138
D/A Wrap-Around................................................................................................................................................................138
Current Reading..................................................................................................................................................................138
Reset to Zero.......................................................................................................................................................................138
Retry Overload ....................................................................................................................................................................138
Reset Overload....................................................................................................................................................................138
Over Current Override.........................................................................................................................................................139
Test Enable.........................................................................................................................................................................139
D2 Test Verify......................................................................................................................................................................139
BIT Status............................................................................................................................................................................139
Over Current Status.............................................................................................................................................................139
BIT Status Interrupt Enable.................................................................................................................................................140
Over Current Status Interrupt Enable..................................................................................................................................140
BIT Interrupt Vector.............................................................................................................................................................140
Over-Current Interrupt Vector..............................................................................................................................................140
Interrupt and Status Register Operation/Clarification ..........................................................................................................141
D/A (MODULE J8) PCI MEMORY MAP............................................................................................................... 142
THERMOCOUPLE MEASUREMENT (MODULE G3).......................................................................................... 143
Principle of Operation..........................................................................................................................................................143
Built-In-Test (BIT) / Diagnostic Capability............................................................................................................................143
Temperature........................................................................................................................................................................144
Thermocouple Type.............................................................................................................................................................144
Operational Mode................................................................................................................................................................144
ADC Data (RAW).................................................................................................................................................................145
Thermocouple Voltage ........................................................................................................................................................145
External Compensation Temperature..................................................................................................................................145
Compensation Type ............................................................................................................................................................146
DPRAM Busy.......................................................................................................................................................................146
BIT/Open Test Interval ........................................................................................................................................................146
Update Rate........................................................................................................................................................................147
Temperature Units...............................................................................................................................................................147
BIT Status............................................................................................................................................................................147
Open Detect Status.............................................................................................................................................................147
BIT Status Interrupt Enable .................................................................................................................................................148
Open Status Interrupt Enable..............................................................................................................................................148
BIT Interrupt Vector.............................................................................................................................................................148
Open Circuit Interrupt Vector...............................................................................................................................................148
Interrupt and Status Register Operation/Clarification ..........................................................................................................149
Appendix A (IEEE 754 Format)...........................................................................................................................................150
IEEE 754 Binary Formats ...............................................................................................................................................150
Appendix B (G3 Optional External Isothermal Block Accessory).........................................................................................151
Isothermal Block Applications.........................................................................................................................................151
Optional Accessory NAI P/N ACC-ISO-THERM-BLK1...................................................................................................152

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THERMOCOUPLE (MODULE G3) PCI MEMORY MAP...................................................................................... 153
RTD (MODULE G4)............................................................................................................................................... 154
Principle of Operation..........................................................................................................................................................154
Built-In-Test (BIT) / Diagnostic Capability............................................................................................................................154
Resistance...........................................................................................................................................................................155
Range..................................................................................................................................................................................155
Wire Mode...........................................................................................................................................................................155
2-Wire Lead Resistance Compensation..............................................................................................................................156
Busy ....................................................................................................................................................................................156
BIT/Open Interval ................................................................................................................................................................156
CAL Interval.........................................................................................................................................................................156
BIT Status............................................................................................................................................................................156
Open Detection Status ........................................................................................................................................................156
BIT Status Interrupt Enable.................................................................................................................................................157
Open Status Interrupt Enable..............................................................................................................................................157
BIT Interrupt Vector.............................................................................................................................................................157
Open Circuit Interrupt Vector...............................................................................................................................................157
Interrupt and Status Register Operation/Clarification ..........................................................................................................158
RTD (MODULE G4) PCI MODULE REGISTER MAP .......................................................................................... 159
LOAD/STRAIN (MODULE G5) ............................................................................................................................. 160
Principles of Operation........................................................................................................................................................160
Built-In Test (BIT) / Diagnostic Capability............................................................................................................................160
Data 16................................................................................................................................................................................161
Data 24................................................................................................................................................................................161
Output Force .......................................................................................................................................................................161
Output V/V...........................................................................................................................................................................161
Range..................................................................................................................................................................................162
Remote Sense Select..........................................................................................................................................................162
Excitation Select..................................................................................................................................................................162
Chop Enable........................................................................................................................................................................163
Excitation Voltage................................................................................................................................................................163
Load Cell Sensitivity............................................................................................................................................................163
Filter Configuration..............................................................................................................................................................164
BUSY...................................................................................................................................................................................165
BIT/OPEN Interval...............................................................................................................................................................165
CAL Interval.........................................................................................................................................................................165
BIT Status............................................................................................................................................................................165
Open Detection Status ........................................................................................................................................................165
BIT Status Interrupt Enable.................................................................................................................................................165
Open Status Interrupt Enable..............................................................................................................................................166
BIT Interrupt Vector.............................................................................................................................................................166
Open Circuit Interrupt Vector...............................................................................................................................................166
Interrupt and Status Register Operation/Clarification ..........................................................................................................167
Appendix (G5) .....................................................................................................................................................................168
STRAIN GAGE (MODULE G5) PCI MODULE MEMORY REGISTER MAP....................................................... 169
I/O DISCRETE (MODULE K6 VER. 4)...................................................................................................................... 171
Description ..........................................................................................................................................................................171
FEATURES .........................................................................................................................................................................171
Continuous Background BIT Testing...................................................................................................................................171
Input/Output Format ............................................................................................................................................................172
Input/Output Interface..........................................................................................................................................................172

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Fig 1 Fig 2 Fig 3.........................................................................................................................................................172
Threshold Programming......................................................................................................................................................173
Max High Threshold ............................................................................................................................................................173
Upper Threshold..................................................................................................................................................................174
Lower Threshold..................................................................................................................................................................174
Min Low Threshold..............................................................................................................................................................174
De-bounce Time..................................................................................................................................................................174
Read I/O..............................................................................................................................................................................175
Vcc Value............................................................................................................................................................................175
Pull-Up/Down Current Configuration ...................................................................................................................................175
Current for Source/Sink.......................................................................................................................................................176
Write Output........................................................................................................................................................................177
Current Share Configuration................................................................................................................................................177
Read Output Voltage...........................................................................................................................................................178
Read Output Current...........................................................................................................................................................178
Reset Over-Current.............................................................................................................................................................178
Status Indications................................................................................................................................................................178
Interrupt Enable...................................................................................................................................................................178
Interrupt Vectors..................................................................................................................................................................179
Interrupt and Status Register Operation/Clarification ..........................................................................................................180
I/O Discrete (Module K6) –Addendum A (PWM Enhanced Function).................................................................................181
Description......................................................................................................................................................................181
Features .........................................................................................................................................................................181
Operational Control Registers:........................................................................................................................................181
Operational notes/considerations: ..................................................................................................................................181
PWM/Timer Period .........................................................................................................................................................183
PWM/TIMER Pulse Width...............................................................................................................................................183
PWM/TIMER Configuration (Polarity).............................................................................................................................184
PWM/TIMER Mode Select..............................................................................................................................................184
PWM/TIMER Mode Enable.............................................................................................................................................185
Register Summary..........................................................................................................................................................185
Operational Notes (General)...........................................................................................................................................185
DISCRETE (MODULE K6 VER. 4) PCI MODULE MEMORY REGISTER MAP.................................................. 186
I/O DISCRETE (MODULE K7).............................................................................................................................. 187
Description ..........................................................................................................................................................................187
Features..............................................................................................................................................................................187
Principles of Operation........................................................................................................................................................187
Continuous Background Built-in-Test (BIT).........................................................................................................................187
Input/Switch Interface..........................................................................................................................................................188
Switch Control .....................................................................................................................................................................188
Threshold Programming......................................................................................................................................................188
Max High Threshold ............................................................................................................................................................189
Upper Threshold..................................................................................................................................................................189
Lower Threshold..................................................................................................................................................................189
Min Low Threshold..............................................................................................................................................................189
De-Bounce Time..................................................................................................................................................................189
Read I/O..............................................................................................................................................................................190
Read Output Voltage (Actual)..............................................................................................................................................190
Read Output Voltage (Averaged) ........................................................................................................................................190
Read Switch Current (Actual)..............................................................................................................................................190
Read Switch Current (Average)...........................................................................................................................................191
Reset Over-Current.............................................................................................................................................................191

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Status Indications................................................................................................................................................................191
Interrupt Enable...................................................................................................................................................................191
Interrupt Vectors..................................................................................................................................................................192
Interrupt and Status Register Operation/Clarification ..........................................................................................................193
DISCRETE (MODULE K7) PCI MODULE MEMORY REGISTER MAP .............................................................. 194
I/O RELAY (MODULE KN, KL)............................................................................................................................. 195
Principle of Operation..........................................................................................................................................................195
Automatic Background Built-In Test (BIT) Diagnostic Capability.........................................................................................195
Write Output........................................................................................................................................................................195
Read State ..........................................................................................................................................................................195
Status, BIT Fault..................................................................................................................................................................196
Interrupt Enable, BIT Fault ..................................................................................................................................................196
Interrupt Vector, BIT Fault...................................................................................................................................................196
Interrupt and Status Register Operation/Clarification ..........................................................................................................197
I/O RELAY (MODULE KN, KL) PCI MEMORY MAP ........................................................................................... 198
DISCRETE/ANALOG TO DIGITAL COMBINATION (MODULE KA).................................................................. 199
Principle of Operation..........................................................................................................................................................199
Discrete I/O.....................................................................................................................................................................199
Analog to Digital Conversion (A/D).................................................................................................................................199
Built-In Test (BIT) / Diagnostic Capability............................................................................................................................199
Analog to Digital Conversion (A/D).................................................................................................................................199
Discrete I/O.....................................................................................................................................................................199
KA Module A/D Specific Functions......................................................................................................................................200
Data Read ......................................................................................................................................................................200
A/D Range......................................................................................................................................................................200
BIT Status.......................................................................................................................................................................200
BIT Status Interrupt Enable ............................................................................................................................................200
KA Module Discrete I/O Specific Functions.........................................................................................................................201
Write Output....................................................................................................................................................................201
Read I/O.........................................................................................................................................................................201
Threshold Programming .................................................................................................................................................201
Hysteresis.......................................................................................................................................................................201
Max High Threshold........................................................................................................................................................202
Upper Threshold.............................................................................................................................................................202
Lower Threshold.............................................................................................................................................................202
Min Low Threshold .........................................................................................................................................................202
De-Bounce Time.............................................................................................................................................................203
Input/Output Interface.....................................................................................................................................................203
Input/Output Format........................................................................................................................................................203
Reset Over-Current ........................................................................................................................................................204
Status Indications ...........................................................................................................................................................204
Status Interrupt Enable...................................................................................................................................................205
Interrupt and Status Register Operation/Clarification ..........................................................................................................206
DISCRETE / A-D COMBINATION (MODULE KA) PCI MEMORY MAP ............................................................. 207
LVDT MEASUREMENT (MODULE L*) ................................................................................................................ 209
Principle of Operation (LVDT) .............................................................................................................................................209
Interfacing LVDT to Converter.............................................................................................................................................209
2-Wire System.....................................................................................................................................................................209
3/4-Wire System..................................................................................................................................................................209
Built-In Test (BIT) / Diagnostic Capability............................................................................................................................209
The On-line D2 Test .......................................................................................................................................................209

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The Off-line D3 Test, ......................................................................................................................................................209
The Off-line D0 Test .......................................................................................................................................................209
Various LVDT Configurations..............................................................................................................................................210
2-wire LVDT Connections:..............................................................................................................................................210
3/4-wire LVDT Connections:...........................................................................................................................................210
Position Data.......................................................................................................................................................................210
Bandwidth (BW)...................................................................................................................................................................211
Bandwidth Select.................................................................................................................................................................211
Active Channels...................................................................................................................................................................211
Latch (Track/Hold)...............................................................................................................................................................211
Test (D2) Verify ...................................................................................................................................................................211
Test Enable.........................................................................................................................................................................212
Test Position........................................................................................................................................................................212
2-Wire/4-Wire Select ...........................................................................................................................................................212
Input Reference Frequency Measurement..........................................................................................................................213
Input Signal Voltage (VL-L) Measurement ............................................................................................................................213
Input Reference Voltage (VREF) Measurement..................................................................................................................213
Signal Loss Threshold.........................................................................................................................................................213
Reference Loss Threshold ..................................................................................................................................................213
Signal Status .......................................................................................................................................................................213
Reference Status.................................................................................................................................................................214
Signal Status Interrupt Enable.............................................................................................................................................214
Reference Status Interrupt Enable ......................................................................................................................................214
BIT Status Interrupt Enable.................................................................................................................................................214
OSC (Onboard) Excitation Set Frequency...........................................................................................................................215
OSC (Onboard) Excitation Set Voltage ...............................................................................................................................215
Interrupt Vector....................................................................................................................................................................216
LVDT FIFO Buffer Operational Description.........................................................................................................................216
LVDT Data:.....................................................................................................................................................................216
Words in FIFO: ...............................................................................................................................................................216
FIFO Status: ...................................................................................................................................................................216
Hi-Threshold:..................................................................................................................................................................217
Low-Threshold:...............................................................................................................................................................217
Delay: .............................................................................................................................................................................217
Size:................................................................................................................................................................................217
Sample Rate:..................................................................................................................................................................217
Clear FIFO:.....................................................................................................................................................................217
Buffer Data Type:............................................................................................................................................................218
Trigger Mode: .................................................................................................................................................................218
Software Trigger:............................................................................................................................................................218
Status, BIT Fail....................................................................................................................................................................219
Interrupt and Status Register Operation/Clarification ..........................................................................................................220
LVDT (MODULE L) PCI MEMORY MAP.............................................................................................................. 221
SYNCHRO/RESOLVER MEASUREMENT (MODULE S*)................................................................................... 222
S/D (Module S*)...................................................................................................................................................................222
Principle of Operation..........................................................................................................................................................222
Built-In Test (BIT) / Diagnostic capability.............................................................................................................................222
Data.....................................................................................................................................................................................223
Velocity................................................................................................................................................................................223
Bandwidth (BW)...................................................................................................................................................................223
Bandwidth Select.................................................................................................................................................................224
Ratio....................................................................................................................................................................................224

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Active Channels...................................................................................................................................................................224
Latch (Track/Hold)...............................................................................................................................................................224
Test (D2) Verify ...................................................................................................................................................................225
Test Enable.........................................................................................................................................................................225
Test Angle...........................................................................................................................................................................225
Synchro/Resolver Select.....................................................................................................................................................225
Angle Δ................................................................................................................................................................................226
Angle Δ INIT ........................................................................................................................................................................226
Input Reference Frequency Measurement..........................................................................................................................226
Input Signal Voltage (VL-L) Measurement ............................................................................................................................226
Input Reference Voltage (VREF) Measurement..................................................................................................................226
A & B Resolution .................................................................................................................................................................227
Signal Loss Threshold.........................................................................................................................................................227
Reference Loss Threshold ..................................................................................................................................................227
Velocity Scale......................................................................................................................................................................227
Signal Status .......................................................................................................................................................................228
Reference Status.................................................................................................................................................................228
S/D Lock Loss Status (Two Speed Lock-Loss) ...................................................................................................................228
S/D Angle Change Status (Angle Δ Alert) ...........................................................................................................................228
Signal Status Interrupt Enable.............................................................................................................................................229
Reference Status Interrupt Enable ......................................................................................................................................229
BIT Status Interrupt Enable.................................................................................................................................................229
S/D Lock Loss Status Interrupt Enable................................................................................................................................229
S/D Angle Change (Angle Δ Alert) Interrupt Enable ............................................................................................................230
OSC (Optional Onboard Reference Supply) Set Frequency ...............................................................................................230
OSC (Optional Onboard Reference Supply) Set Voltage....................................................................................................230
Interrupt Vector....................................................................................................................................................................231
S/D FIFO Buffer Operational Description ............................................................................................................................231
S/D Data:........................................................................................................................................................................231
Words in FIFO (Count): ..................................................................................................................................................231
FIFO Status: ...................................................................................................................................................................231
Hi-Threshold:..................................................................................................................................................................231
Low-Threshold:...............................................................................................................................................................232
Delay: .............................................................................................................................................................................232
Size:................................................................................................................................................................................232
Sample Rate:..................................................................................................................................................................232
Clear FIFO:.....................................................................................................................................................................232
Buffer Data Type:............................................................................................................................................................232
Trigger Mode: .................................................................................................................................................................233
Interrupt:.........................................................................................................................................................................233
Software Trigger:............................................................................................................................................................233
Status, BIT Fail....................................................................................................................................................................233
Interrupt and Status Register Operation/Clarification ..........................................................................................................234
S/D (MODULE S) PCI MEMORY MAP................................................................................................................. 235
D/S THREE CHANNEL (MODULE 6*) ................................................................................................................. 237
Principle of Operation..........................................................................................................................................................237
Built-In Test (BIT) / Diagnostic Capability............................................................................................................................237
Wrap S/D Angle Read.........................................................................................................................................................237
Input Reference Voltage Measurement...............................................................................................................................237
Input Signal Voltage (VL-L) Measurement...........................................................................................................................237
Signal Loss Threshold.........................................................................................................................................................238
Reference Loss Threshold ..................................................................................................................................................238

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D/S Channel Frequency......................................................................................................................................................238
D/S Status, Signal Loss.......................................................................................................................................................238
D/S Write Angle –Single Speed..........................................................................................................................................238
D/S Write Angle –Two Speed.............................................................................................................................................239
D/S Stop Angle....................................................................................................................................................................239
D/S Rotation........................................................................................................................................................................239
D/S Rotation Rate................................................................................................................................................................239
D/S Rotation Mode, Continuous or Start/Stop.....................................................................................................................239
Start Rotation ......................................................................................................................................................................239
Stop Rotation.......................................................................................................................................................................239
D/S Rotation Status.............................................................................................................................................................240
D/S Set Reference Voltage .................................................................................................................................................240
D/S Set Signal Voltage........................................................................................................................................................240
D/S Test Enable ..................................................................................................................................................................240
Test (D2) Verify ...................................................................................................................................................................240
D/S Ratio 1/2.......................................................................................................................................................................241
D/S Output Mode.................................................................................................................................................................241
D/S Synchro / Resolver Select ............................................................................................................................................241
D/S Trigger Source Select...................................................................................................................................................241
D/S Trigger Slope Select.....................................................................................................................................................241
D/S Module Power Enable ..................................................................................................................................................242
D/S Active Channels............................................................................................................................................................242
D/S Status, Reference Loss................................................................................................................................................242
D/S Status, Phase Lock Loss..............................................................................................................................................243
D/S Set Phase Offset ..........................................................................................................................................................243
D/S Status, BIT Test............................................................................................................................................................243
Reference Loss Interrupt Enable.........................................................................................................................................244
Signal Loss Interrupt Enable ...............................................................................................................................................244
BIT Test Fail Interrupt Enable..............................................................................................................................................244
Phase Lock Loss Interrupt Enable.......................................................................................................................................244
OSC (Optional Onboard Reference Supply) Set Frequency ...............................................................................................244
OSC (Optional Onboard Reference Supply) Set Voltage....................................................................................................245
Interrupt Vector....................................................................................................................................................................245
Interrupt and Status Register Operation/Clarification ..........................................................................................................246
D/S 3 CHANNEL (6*) PCI MODULE MEMORY MAP.......................................................................................... 247
DLV 3 CHANNEL (MODULE 5*) .......................................................................................................................... 248
Principle of Operation..........................................................................................................................................................248
Built-in Test/Diagnostic Capability.......................................................................................................................................248
Wrap LVDT Position (Read)................................................................................................................................................248
DLV Channel Excitation Voltage..........................................................................................................................................248
DLV Channel Signal Voltage...............................................................................................................................................249
Signal Loss Threshold.........................................................................................................................................................249
Excitation Loss Threshold ...................................................................................................................................................249
DLV Write Position ..............................................................................................................................................................249
DLV Response / Filter Time ................................................................................................................................................249
Status, Signal Loss..............................................................................................................................................................250
DLV Channel Frequency.....................................................................................................................................................250
DLV Set Channel Excitation Voltage...................................................................................................................................250
DLV Set Channel Signal Voltage.........................................................................................................................................250
DLV Test Enable .................................................................................................................................................................250
Test (D2) Verify ...................................................................................................................................................................251
DLV Output Mode................................................................................................................................................................251

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DLV 2-wire or 3/4-Wire Select.............................................................................................................................................251
DLV Module Power Enable .................................................................................................................................................252
DLV Current ........................................................................................................................................................................252
DLV Active Channels...........................................................................................................................................................252
DLV Status, Excitation.........................................................................................................................................................253
DLV Status, Phase Lock Loss.............................................................................................................................................253
DLV Set Phase Offset .........................................................................................................................................................253
DLV Current Threshold........................................................................................................................................................253
OSC (Onboard) Excitation Set Frequency...........................................................................................................................254
OSC (Onboard) Excitation Set Voltage ...............................................................................................................................254
DLV Status, BIT Test...........................................................................................................................................................255
Excitation Loss Interrupt Enable..........................................................................................................................................255
Signal Loss Interrupt Enable ...............................................................................................................................................255
BIT Test Fail Interrupt Enable..............................................................................................................................................255
Phase Lock Loss Interrupt Enable.......................................................................................................................................256
Interrupt Vector....................................................................................................................................................................256
Interrupt and Status Register Operation/Clarification ..........................................................................................................257
3 CH DLV (5*) (PCI) MODULE MEMORY MAP................................................................................................... 258
SSI / ENCODER / QUADRATURE COUNTER (MODULE E7)............................................................................ 259
Principles of Operation........................................................................................................................................................259
Channel Inputs ....................................................................................................................................................................260
SSI Mode.............................................................................................................................................................................260
Description ..........................................................................................................................................................................260
Standard SSI Interface Controller Mode..............................................................................................................................261
SSI Standard Mode Selection .............................................................................................................................................261
Listen Only Mode.................................................................................................................................................................262
SSI Listen Only Mode Selection..........................................................................................................................................262
Parity...................................................................................................................................................................................263
Control Register 0................................................................................................................................................................264
Control Register 1................................................................................................................................................................265
SSI Received Data High......................................................................................................................................................265
SSI Received Data Low.......................................................................................................................................................265
SSI Received ZB, Parity......................................................................................................................................................265
SSI Status ...........................................................................................................................................................................266
Counter Modes....................................................................................................................................................................267
Counter Match Register..................................................................................................................................................267
Counter Preload Register...............................................................................................................................................267
Counter Latch Register..................................................................................................................................................267
Counter Control Register................................................................................................................................................267
Index Control Modes (ICM) .................................................................................................................................................268
No I-Control.........................................................................................................................................................................268
Load on I .............................................................................................................................................................................268
Latch on I.............................................................................................................................................................................268
Gate on I..............................................................................................................................................................................269
Reset on I............................................................................................................................................................................269
Special Count Mode............................................................................................................................................................269
Special Count Modes ..........................................................................................................................................................269
Divide-by-N..........................................................................................................................................................................269
Single Cycle ........................................................................................................................................................................269
Internal Clock Prescaler ......................................................................................................................................................270
CLKDIV...........................................................................................................................................................................270
Counter Input Mode (CIM)..............................................................................................................................................270

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Counter Status Register......................................................................................................................................................271
Timer Mode .........................................................................................................................................................................271
Direction Count....................................................................................................................................................................271
Up/Down Count...................................................................................................................................................................272
Quadrature Mode ................................................................................................................................................................272
Counter Command Register................................................................................................................................................272
Interval Timer.......................................................................................................................................................................272
Interval Timer Control..........................................................................................................................................................273
Interval Timer Clock Periods ...............................................................................................................................................273
Global Control Registers .....................................................................................................................................................274
Global Control Register High..........................................................................................................................................274
Multiple Channel Read........................................................................................................................................................275
Interrupt...............................................................................................................................................................................277
Interrupt Vector Registers....................................................................................................................................................277
Interrupt Enable Register.....................................................................................................................................................278
De-bounce, Digital Input Filter.............................................................................................................................................278
De-bounce Register High [15:0] ..........................................................................................................................................278
De-bounce Register Low [0]................................................................................................................................................278
CPLD (Module Configuration Registers) .............................................................................................................................279
CPLD Register High .......................................................................................................................................................279
CPLD Register Low........................................................................................................................................................280
Differential (DE) / Single-Ended (SE) Selection...................................................................................................................281
CPLD Status........................................................................................................................................................................281
Appendix A –Quadrature (A-Quad-B) Discussion...............................................................................................................282
Quadrature Count...........................................................................................................................................................282
Appendix B –Operation Mode Signal Details......................................................................................................................285
FOUR CHANNEL SSI/ENCODER (MODULE E7) PCI MEMORY MAP..............................................................................287
ISOLATED ±15V DC/DC CONVERTER (MODULE V1, V2).............................................................................. 289
Description ..........................................................................................................................................................................289
Features:.............................................................................................................................................................................289
Principles of Operation........................................................................................................................................................289
Continuous Background Built-in-Testing (BIT) ....................................................................................................................289
Registers.............................................................................................................................................................................290
On/Off..................................................................................................................................................................................290
Output Voltage (V+).............................................................................................................................................................290
Output Voltage (V-)..............................................................................................................................................................290
Output Current (V+).............................................................................................................................................................290
Output Current (V-)..............................................................................................................................................................291
Fault ....................................................................................................................................................................................291
Clear Fault...........................................................................................................................................................................291
Interrupt and Status Register Operation/Clarification ..........................................................................................................292
MODULE (V*), DUAL ±15V DC/DC CONVERTER, PCI MEMORY REGISTER MAP ........................................ 293
REFERENCE (MODULE W*)................................................................................................................................ 294
Principle of Operation..........................................................................................................................................................294
Reference Frequency..........................................................................................................................................................294
Reference Voltage...............................................................................................................................................................295
Reference Module Power Enable........................................................................................................................................295
Reference Overcurrent1.......................................................................................................................................................295
REFERENCE (MODULE W*) PCI MEMORY MAP .............................................................................................. 296
MODULE IDENTIFICATION ................................................................................................................................. 297
Module Design Version .......................................................................................................................................................297

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Module Design Revision......................................................................................................................................................297
Module DSP Revision..........................................................................................................................................................297
Module FPGA Revision.......................................................................................................................................................298
Module ID............................................................................................................................................................................298
GENERAL USE REGISTER MEMORY MAP....................................................................................................... 299
Common User Register Memory Map (PCI)........................................................................................................................299
Part Number........................................................................................................................................................................299
Serial Number......................................................................................................................................................................299
Platform...............................................................................................................................................................................300
Model...................................................................................................................................................................................300
Generation...........................................................................................................................................................................300
Special Spec .......................................................................................................................................................................300
Date Code...........................................................................................................................................................................301
Module ID............................................................................................................................................................................301
Revision Level, Interface FPGA...........................................................................................................................................301
Revision Level, Interface DSP.............................................................................................................................................301
Board Ready .......................................................................................................................................................................302
Watchdog Timer..................................................................................................................................................................302
Soft Reset............................................................................................................................................................................302
Interrupt Level (Not Used)...................................................................................................................................................302
Design Version....................................................................................................................................................................303
Interrupt Status....................................................................................................................................................................303
Customer Defined Register Allocation............................................................................................................................304
Ethernet Configuration Registers.........................................................................................................................................304
ETHERNET ........................................................................................................................................................... 305
Ethernet Socket Protocol, Version 1....................................................................................................................................305
Type Codes Summary.........................................................................................................................................................306
Error Codes.........................................................................................................................................................................306
68C3 CONNECTOR/PIN-OUT INFORMATION ................................................................................................... 307
Front and Rear Panel Connectors.......................................................................................................................................307
General Notes: ....................................................................................................................................................................307
Optional Onboard Reference...............................................................................................................................................307
Trigger Input........................................................................................................................................................................307
Front Panel System Ground................................................................................................................................................307
Chassis Ground...................................................................................................................................................................307
Front Panel Connectors J1, J2:...........................................................................................................................................307
Front Panel (J1, J2) (Connector Placement and Orientation):.............................................................................................308
Rear I/O VPX Connectors P0 –P2:.....................................................................................................................................309
Rear I/O Utility Plane (P0):..................................................................................................................................................310
Rear I/O Data/Control Planes (P1):.....................................................................................................................................310
Rear I/O Data/Control Planes (P1 Continued):....................................................................................................................311
USER I/O –Defined Area (User Defined I/O) (P3-P6):........................................................................................................311
Rear I/O Summary:..............................................................................................................................................................312
SLOT 1 –Analog and Digital I/O Modules (User Defined I/O Pin-Outs)..............................................................................313
SLOT 1 –Digital I/O Modules (User Defined I/O Pin-Outs)..................................................................................................314
SLOT 1 –Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)......................................................................315
SLOT 1 –Communications I/O Modules (User Defined I/O Pin-Outs) ................................................................................316
SLOT 2 –Analog I/O Modules (User Defined I/O Pin-Outs)................................................................................................317
SLOT 2 –Digital I/O Modules (User Defined I/O Pin-Outs)..................................................................................................318
SLOT 2 –Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)......................................................................319
SLOT 2 –Communications Modules (User Defined I/O Pin-Outs)......................................................................................320
SLOT 3 –Onboard Reference or Multi-Function Combo (User Defined I/O Pin-Outs)........................................................321