NXP Semiconductors LPC84x User manual
UM11029
LPC84x User manual
Rev. 1.0 — 16 June 2017 User manual
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Keywords LPC84x, LPC84x UM, LPC84x user manual
Abstract LPC84x User manual
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NXP Semiconductors UM11029
LPC84x User manual
Revision history
Rev Date Description
v.1 20170616 Initial revision. LPC84x User manual.
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1.1 Introduction
The LPC84x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and
16 KB of SRAM.
The peripheral complement of the LPC84x includes a CRC engine, four I2C-bus
interfaces, up to five USARTs, up to two SPI interfaces, one multi-rate timer, self-wake-up
timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC,
two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch
matrix, an input pattern match engine, and up to 54 general-purpose I/O pins.
Remark: For additional documentation, see Section 32.2 “References”.
1.2 Features
•System:
–ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to
30 MHz with single-cycle multiplier and fast single-cycle I/O port.
–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
–System tick timer.
–AHB multilayer matrix.
–Serial Wire Debug (SWD) with four break points and two watch points. JTAG
boundary scan (BSDL) supported.
–Micro Trace Buffer (MTB)
•Memory:
–Up to 64 KB on-chip flash programming memory with 64 Byte page write and
erase.
–Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on
power-up.
–Code Read Protection (CRP).
–Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of
SRAM can be used for MTB.
–Bit-band addressing supported to permit atomic operations to modify a single bit.
•ROM API support:
–Bootloader.
–Supports Flash In-Application Programming (IAP).
–Supports In-System Programming (ISP) through USART, SPI, and I2C.
–FAIM API.
–FRO API.
–Flash In-Application Programming (IAP) and In-System Programming (ISP).
UM11029
Chapter 1: LPC84x Introductory information
Rev. 1.0 — 16 June 2017 User manual
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Chapter 1: LPC84x Introductory information
•Digital peripherals:
–High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to
32 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter. GPIO direction
control supports independent set/clear/toggle of individual bits.
–High-current source output driver (20 mA) on four pins.
–High-current sink driver (20 mA) on two true open-drain pins.
–GPIO interrupt generation capability with boolean pattern-matching feature on
eight GPIO inputs.
–Switch matrix for flexible configuration of each I/O pin function.
–CRC engine.
–DMA with 25 channels and 13 trigger inputs.
•Timers:
–One SCTimer/PWM with five input and seven output functions (including capture
and match) for timing and PWM applications. Inputs and outputs can be routed to
or from external pins and internally to or from selected peripherals. Internally, the
SCTimer/PWM supports 8 match/captures, 8 events, and 8 states.
–One 32-bit general purpose counter/timer, with four match outputs and three
capture inputs. Supports PWM mode, external count, and DMA.
–Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to
four programmable, fixed rates.
–Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a
low-power, low-frequency internal oscillator, or an external clock input in the
always-on power domain.
–Windowed Watchdog timer (WWDT).
•Analog peripherals:
–One 12-bit ADC with up to 12 input channels with multiple internal and external
trigger inputs and with sample rates of up to 1.2 Msamples/s. The ADC supports
two independent conversion sequences.
–Comparator with five input pins and external or internal reference voltage.
–Two 10-bit DACs.
•Serial peripherals:
–Five USART interfaces with pin functions assigned through the switch matrix and
two fractional baud rate generators.
–Two SPI controllers with pin functions assigned through the switch matrix.
–Four I2C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates
on two true open-drain pins and listen mode. Three I2Cs support data rates up to
400 kbit/s on standard digital pins.
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Chapter 1: LPC84x Introductory information
•Clock generation:
–Free Running Oscillator (FRO). This oscillator provides a selectable 18 MHz,
24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these
outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz,
and15 MHz for system clock. The FRO is trimmed to ±1 % accuracy over the entire
voltage and temperature range 0 C to 70 C.
–Low power boot at 1.5 MHz using FAIM memory.
–External clock input for clock frequencies of up to 25 MHz.
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–Low power oscillator can be used as a clock source to the watchdog timer.
–Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
–PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator, the external clock
input, or the internal FRO.
–Clock output function with divider that can reflect all internal clock sources.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption.
–Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and
deep power-down mode.
–Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and
I2C peripherals.
–Timer-controlled self wake-up from deep power-down mode.
–Power-On Reset (POR).
–Brownout detect (BOD).
•Unique device serial number for identification.
•Single power supply (1.8 V to 3.6 V).
•Operating temperature range -40 °C to +105 °C.
•Available in LQFP64, LQFP48, HVQFN48, and HVQFN33 packages
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Chapter 1: LPC84x Introductory information
1.3 Ordering options
1.4 General description
1.4.1 ARM Cortex-M0+ core configuration
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in
the core are the NVIC and Serial Wire Debug with four breakpoints and two watch points.
The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO
access at address 0xA000 0000. The ARM Cortex M0+ core version is r0p1.
The core includes a single-cycle multiplier and a system tick timer (SysTick).
Table 1. Ordering information
Type number Package
Name Description Version
LPC845M301JBD64 LQFP64 Plastic low profile quad flat package; 64 leads; body 1010 1.4 mm SOT314-2
LPC845M301JBD48 LQFP48 Plastic low profile quad flat package; 48 leads; body 77 1.4 mm SOT313-2
LPC845M301JHI48 HVQFN48 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 48
terminals; body 77 0.85 mm
SOT619-1
LPC845M301JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm
SOT617-11
LPC844M201JBD64 LQFP64 Plastic low profile quad flat package; 64 leads; body 1010 1.4 mm SOT314-2
LPC844M201JBD48 LQFP48 Plastic low profile quad flat package; 48 leads; body 77 1.4 mm SOT313-2
LPC844M201JHI48 HVQFN48 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm
SOT619-1
LPC844M201JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm
SOT617-11
Table 2. Ordering options
Type number Flash/KB SRAM/KB USART I2CSPI DAC GPIO Package
LPC845M301JBD64 64 16 5 4 2 2 54 LQFP64
LPC845M301JBD48 64 16 5 4 2 2 42 LQFP48
LPC845M301JHI48 64 16 5 4 2 2 42 HVQFN48
LPC845M301JHI33 64 16 5 4 2 1 29 HVQFN33
LPC844M201JBD64 64 8 2 2 2 - 54 LQFP64
LPC844M201JBD48 64 8 2 2 2 - 42 LQFP48
LPC844M201JHI48 64 8 2 2 2 - 42 HVQFN48
LPC844M201JHI33 64 8 2 2 2 - 29 HVQFN33
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Chapter 1: LPC84x Introductory information
1.5 Block diagram
Note: Yellow shaded blocks support general purpose DMA
Fig 1. LPC84x block diagram aaa-022793
aaa-022793-x
CLKOUT
Vdd
CLKIN
XTALIN
XTALOUT
SWD Port
JTAG Test and
Boundary Scan
interface RESET
Clock Generation,
Power Control,
and other
System Functions
Voltage Regulator
DEBUG
INTERFACE
IOP bus
GPIOs GPIOs AND
GPOINT
Flash
interface
Flash
64 kB
General
Purpose
DMA
controller
MTB slave
interface
DMA
registers CRC
Multilayer
AHB Matrix
AHB to
APB bridge
FAIM
256-bit
T0 Match/
Capture
I2C2,3
COMP
Inputs
ADC Inputs
and Triggers
DAC1 outputs
DAC0 outputs
PIOs
UART0,1,2, 3, 4
SPI0,1
I2C0,1
APB slave group
Watchdog
Osc Windowed WDT
Note:
SCT Timer/
PWM
ARM
Cortex M0+
System control
IOCON Registers
Flash Registers (NVMC)
CTIMER32
I2C2/3
UARTs 0-4
SPI0/1
I2C0/1
Periph Input Mux Selects
Comparator
PMU Registers
12-bit ADC
10-bit DAC1
10-bit DAC0
FAIM Registers
Switch Matrix
Wakeup Timer
Multi-Rate Timer
Boot ROM
16 kB
SRAM/MTB
8 kB
SRAM
8 kB
Yellow shaded blocks support general purpose DMA
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2.1 How to read this chapter
The memory mapping is identical for all LPC84x parts. Different LPC84x parts support
different flash and SRAM memory sizes.
2.2 General description
The LPC84x incorporates several distinct memory regions. Figure 2 shows the overall
map of the entire address space from the user program viewpoint following reset.
The APB peripheral area is 512 KB in size and is divided to allow for up to 32 peripherals.
Each peripheral is allocated 16 KB of space simplifying the address decoding.
The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and
sleep mode control, are located on the private peripheral bus.
The GPIO port and pin interrupt/pattern match registers are accessed by the ARM
Cortex-M0+ single-cycle I/O enabled port (IOP).
UM11029
Chapter 2: LPC84x memory mapping
Rev. 1.0 — 16 June 2017 User manual
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Chapter 2: LPC84x memory mapping
2.2.1 Memory mapping
2.2.2 Micro Trace Buffer (MTB)
The LPC84x supports the ARM Cortex-M0+ Micro Trace Buffer. See Section 31.5.4.
Fig 2. LPC84x Memory mapping
aaa-027479
(reserved)
MTB registers
DMA controller
SCTimer / PWM
AHB perpherals
CRC engine
0x5001 4000
0x5001 0000
0x5000 C000
0x5000 8000
0x5000 4000
0x5000 0000
(reserved)
private peripheral bus
(reserved)
GPIO interrupts
Memory space
GPIO
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
active interrupt vectors
Boot ROM
RAM1
RAM0
AHB
peripherals
APB
peripherals
Flash memory
(up to 64 MB)
0xFFFF FFFF
0xE010 0000
0xE000 0000
0xA008 0000
0xA004 0000
0xA000 0000
0x5001 4000
0x5000 0000
0x4008 0000
0x4000 0000
0x1000 4000
0x1000 2000
0x1000 0000
0x0F00 4000
0x0F00 0000
0x0001 0000
0x0000 0000
0x0000 00C0
0x0000 0000
(reserved)
UART4
UART3
UART2
APB perpherals
UART1
UART0
(reserved)
SPI1
SPI0
I2C1
I2C0
(reserved)
Syscon
IOCON
Flash controller
(reserved)
CTIMER 0
I2C3
I2C2
Input Multiplexing
(reserved)
Analog Comparator
PMU
ADC
DAC1
DAC0
(reserved)
Switch Matrix
Wake-up Timer
Multi-Rate Timer
Watchdog timer
31-30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4007 FFFF
0x4007 8000
0x4007 4000
0x4007 0000
0x4006 C000
0x4006 8000
0x4006 4000
0x4006 0000
0x4005 C000
0x4005 8000
0x4005 4000
0x4005 0000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
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3.1 How to read this chapter
The bootloader is identical for all parts.
3.2 Features
•16 KB on-chip boot ROM
•Contains the bootloader with In-System Programming (ISP) facility over multiple
peripheral communication (UART, I2C, and SPI) and the following API:
–In-Application Programming (IAP) of flash memory.
–Integer divide routines.
–FAIM API.
–FRO API.
3.3 Basic configuration
Depending on the FAIM configuration, the boot ROM sets the FRO control register to
select the operating frequency accordingly. If FAIM is not programmed or contains an
invalid value, the ROM begins at 12 MHz.
3.4 Pin description
When the ISP entry pin (PIO0_12) is pulled LOW on reset, the part enters ISP mode and
the ISP command handler starts up.
UM11029
Chapter 3: LPC84x Boot Process
Rev. 1.0 — 16 June 2017 User manual
Table 3. Pin location in ISP mode
ISP mode Default FAIM configuration FAIM ISP selection
(FAIM word0, bit 30
and 31), Table 5
FAIM ISP pin
function (FAIM
word0, bit 30
and 31)
USART ISP PIO0_25 is UART0 TX
PIO0_24 is UART0 RX
Applicable when FAIM content
is invalid.
0x00 See: Table 6
I2C ISP PIO0_11 is I2C0 SDA
PIO0_10 is I2C0 SCL
Applicable when FAIM content
is invalid.
0x01 -
SPI ISP PIO0_15 is SPI0 SCK
PIO0_22 is SPI0 SSEL0
PIO0_26 is SPI0 MISO
PIO0_27 is SPI0 MOSI
0x02 See: Table 6
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Chapter 3: LPC84x Boot Process
3.5 General description
3.5.1 Bootloader
The bootloader executes every time the device is powered on or reset. Based on the chip
configuration information, the bootloader controls initial operation after reset, including
setting internal voltage regulator, system clock, flash controller, miscellaneous factory
trimming value, and then allows programming and reprogramming of internal flash via a
set of commands on USART, I2C slave, or SPI slave bus. The LPC84x device must be
connected to a host system that provides the UART, I2C or SPI master connections.
During the boot process, a LOW level after reset on the ISP pin is considered as an
external hardware request to start the ISP command handler via USART, I2C, or SPI
interface. Otherwise, the bootloader checks if there is valid user code in flash. If the valid
user code is not found, the bootloader checks the FAIM configuration and enters one of
the ISP modes. Auto detect is selected if FAIM is invalid.
Remark: The sampling of pin the ISP entry pin can be disabled through programming
flash location 0x0000 02FC (see Section 4.3.6 “Code Read Protection (CRP)”).
See Chapter 5 “LPC84x ISP and IAP”for more details.
3.5.2 ROM-based APIs
Once the part has booted, the user can access several APIs located in the boot ROM. The
ROM API supports:
•Boot loader.
•Flash In-Application Programming (IAP).
•In-System Programming (ISP) through USART, SPI, and I2C.
•On-chip ROM APIs for integer divide.
•FAIM API.
•FRO API.
The structure of the boot ROM APIs is shown in Figure 3.
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Chapter 3: LPC84x Boot Process
Fig 3. Boot ROM structure
…
…
+0x0
+0x4
+0x8
+0x10
+0xC
Device API 3
Power profiles API function table
IAP calls
Clock setting and enter low power mode API
aaa-026624
Ptr to IAP
0x0F001FF1
Ptr to ROM Driver table
0x0F001FF8
ROM Driver Table
Reserved
Reserved
Reserved
Ptr to Device API Table n
Device API n
Ptr to Function 0
Ptr to Function 1
Ptr to Function 2
Ptr to Function n
Device API 4
Integer Divide routines function table
Pointer to 32-bit integer divide routines
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Chapter 3: LPC84x Boot Process
The boot ROM structure should be included as follows:
typedef struct {
const uint32_t reserved0; /*!< Reserved */
const uint32_t reserved1; /*!< Reserved */
const uint32_t reserved2; /*!< Reserved */
const PWRD_API_T *pPWRD; /*!< Power API function table base address */
const ROM_DIV_API_T *divApiBase; /*!< Divider API function table base address */
} LPC_ROM_API_T;
#define ROM_DRIVER_BASE (0x0F001FF8)
3.6 Functional description
3.6.1 Memory map after any reset
The boot ROM block is 16 KB in size. The boot block is located in the memory region
starting from address 0x0F00 0000. The bootloader is designed to run from this memory
area, but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is
described in Section 4.3.7 “ISP interrupt and SRAM use”. The interrupt vectors residing in
the boot block of the on-chip flash memory also become active after reset, i.e., the bottom
512 bytes of the boot block are also visible in the memory region starting from the address
0x0000 0000.
Table 4. API calls
API Description Reference
Flash IAP Flash In-Application programming Table 37
Integer divider API 32-bit integer divide routines Table 471
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Chapter 3: LPC84x Boot Process
3.6.2 Boot process
Fig 4. Boot process flowchart
aaa-026887
Reset
Enable debugger
FAIM content invalid,
fixed USART/I2C/
SPI port pins
FAIM ISP select 0,
USART port/pin
setting
FAIM ISP select 0,
USART port/pin
setting
FAIM ISP select 2,
SPI port/pin
setting
UART ISP
USART ISP
command handler
I2C/SPI ISP
command handler
I2C ISP
User code
SPI ISP
Device configure/
Initialize
CRP 1/2/3
enabled
WDT reset
No_ISP or
CRP3
enabled
no
no
no
0/1/2
invalid
21
0
no
no
User code
valid
User code
valid
ISP pin
low
USART/I2S/
SPI ISP auto
detected
FAIM content
valid or 0/1/2
yes
yes
yes
A
A
yes
yes
yes
no
no
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4.1 How to read this chapter
The Fast Initialization Memory (FAIM) is a 256-bit memory configured as eight words (or
rows) of 32-bits per word.
4.2 General description
The FAIM is a multiple time programmable (MTP), ultra low power memory, the full
contents of which are read and latched immediately after reset, with no clocks required.
The FAIM contents provide a user-programmable initial configuration for aspects of the
microcontroller, which take effect immediately after reset, before code begins to run. For
instance, the standard I/O pads normally come out of reset with the internal pull-ups
enabled. In some systems this may cause excess current to flow, until software can
reconfigure the pads. However, by programming the FAIM appropriately, every pad's reset
configuration can be customized. Other aspects which can be controlled by the FAIM are
initial FRO divider value (low power start), serial wire debug disable, default ISP interface
and pins, etc. One 32-bit FAIM row can be programmed, or read, using the ROM IAP calls
FAIMWrite and FAIMRead (see Chapter 5 “LPC84x ISP and IAP”for details).
After a FAIMMWrite, a FAIMRead is required to update the output of the FAIM. Once a
read has been performed, the FAIM contents are visible in the AHB Peripheral address
space starting at 0x5001_0000.
For the pull-up, pull-down, and HI-Z IOCON pin configuration settings, a reset is needed
to transfer the newly programmed FAIM values into the IOCON pin configuration registers.
Executing a FAIMWrite followed by a FAIMRead does not update the current configuration
in the IOCON pin configuration registers. Only a reset can do so. Software can at any time
rewrite the IOCON pin configuration. Similarly, for SWD Disable, Low Power Start
configuration, ISP interface and pin select, a reset is needed to update the actual startup
configuration.
The FAIM is limited to 200 program cycles, so care must be taken to write this memory
only when necessary during an end-product's development. Also, the FAIM programming
voltage range is 3.0 V Vdd 3.6 V.
Remark: If internal pull-down is enabled via FAIM on the ISP pin (PIO0_12) or the reset
pin (PIO0_5), ensure to have a strong external pull-up to avoid going into ISP mode or into
reset after boot-up.
4.2.1 FAIM bit definitions
The functions of FAIM bits are described in the following tables.
UM11029
Chapter 4: LPC84x FAIM
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Chapter 4: LPC84x FAIM
Table 5. FAIM word 0 bit description
Bit Description Default value
0 SWD disable 0
0 SWD enabled
1 SWD disabled
1 Low Power Boot 0
0 Normal boot (12 MHz)
1 Low Power Boot (1.5 MHz)
26:2 Reserved 0
28 Reserved 0
29, 27 FAIM content valid bits 11
00 FAIM content invalid
01 FAIM content invalid
10 FAIM content invalid
11 FAIM content valid
31:30 ISP interface select 0
00 USART0
01 I2C0
10 SPI0
11 Reserved
Table 6. FAIM word 1 bit description
Bit Description Default value
4:0 ISP Rx pin select (USART0 Rx, SPI MOSI) 0x18
0x0
0x1
...
0x1F
PIOn_0
PIOn_1
...
PIOn_31
7:5 ISP Rx port select (USART0 Rx, SPI MOSI) 0
0x0 Port 0
0x1 Port 1
12:8 ISP Tx pin select (USART0 Tx, SPI MISO) 0x19
0x0
0x1
...
0x1F
PIOn_0
PIOn_1
...
PIOn_31
15:13 ISP Tx port select (USART0 Tx, SPI MISO) 0
0x0 Port 0
0x1 Port 1
20:16 ISP clock pin select (SPI SCK) 0
0x0
0x1
...
0x1F
PIOnPIOn_0
PIOn_1
...
PIOn_31
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Chapter 4: LPC84x FAIM
23:21 ISP clock port select (SPI SCK) 0
0x0 Port 0
0x1 Port 1
28:24 ISP SPI0 SSELN0 pin select 0
0x0
0x1
...
0x1F
PIOn_0
PIOn_1
...
PIOn_31
31:29 ISP SPI0 SSELN0 port select 0
0x0 Port 0
0x1 Port 1
Table 7. FAIM word 2 bit description
Bit Description Default value
31:0 Reserved 0
Table 8. FAIM word 3 bit description
Bit Description Default value
31:0 Reserved 0
Table 9. FAIM word 4 bit description
Bit Description Default value
19:0 Reserved 0
21:20 PIO1_21 0x2
0x0 Hi-Z
0x1 Pull-down
0x2 Pull-up
0x3 Repeater
23:22 PIO1_20. See description of bits of bits 21:20. 0x2
25:24 PIO1_19. See description of bits 21:20. 0x2
27:26 PIO1_18. See description of bits 21:20. 0x2
29:28 PIO1_17. See description of bits 21:20. 0x2
31:30 PIO1_16. See description of bits 21:20. 0x2
Table 10. FAIM word 5 bit description
Bit Description Default value
1:0 PIO1_15
0x0 Hi-Z 0x2
0x1 Pull-down
0x2 Pull-up
0x3 Repeater
3:2 PIO1_14. See description of bits 1:0. 0x2
Table 6. FAIM word 1 bit description
Bit Description Default value
UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 19 of 515
NXP Semiconductors UM11029
Chapter 4: LPC84x FAIM
5:4 PIO1_13. See description of bits 1:0. 0x2
7:6 PIO1_12. See description of bits 1:0. 0x2
9:8 PIO1_11. See description of bits 1:0. 0x2
11:10 PIO1_10. See description of bits 1:0. 0x2
13:12 PIO1_9. See description of bits 1:0. 0x2
15:14 PIO1_8. See description of bits 1:0. 0x2
17:16 PIO1_7. See description of bits 1:0. 0x2
19:18 PIO1_6. See description of bits 1:0. 0x2
21:20 PIO1_5. See description of bits 1:0. 0x2
23:22 PIO1_4. See description of bits 1:0. 0x2
25:24 PIO1_3. See description of bits 1:0. 0x2
27:26 PIO1_2. See description of bits 1:0. 0x2
29:28 PIO1_1. See description of bits 1:0. 0x2
31:30 PIO1_0. See description of bits 1:0. 0x2
Table 11. FAIM word 6 bit description
Bit Description Default value
1:0 PIO0_31 0
0x0 Hi-Z 0x2
0x1 Pull-down
0x2 Pull-up
0x3 Repeater
3:2 PIO0_30. See description of bits 1:0. 0x2
5:4 PIO0_29. See description of bits 1:0. 0x2
7:6 PIO0_28. See description of bits 1:0. 0x2
9:8 PIO0_27. See description of bits 1:0. 0x2
11:10 PIO0_26. See description of bits 1:0. 0x2
13:12 PIO0_25. See description of bits 1:0. 0x2
15:14 PIO0_24. See description of bits 1:0. 0x2
17:16 PIO0_23. See description of bits 1:0. 0x2
19:18 PIO0_22. See description of bits 1:0. 0x2
21:20 PIO0_21. See description of bits 1:0. 0x2
23:22 PIO0_20. See description of bits 1:0. 0x2
25:24 PIO0_19. See description of bits 1:0. 0x2
27:26 PIO0_18. See description of bits 1:0. 0x2
29:28 PIO0_17. See description of bits 1:0. 0x2
31:30 PIO0_16. See description of bits 1:0. 0x2
Table 10. FAIM word 5 bit description
Bit Description Default value
UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 20 of 515
NXP Semiconductors UM11029
Chapter 4: LPC84x FAIM
Table 12. FAIM word 7 bit description
Bit Description Default value
1:0 PIO0_15 0
0x0 Hi-Z 0x2
0x1 Pull-down
0x2 Pull-up
0x3 Repeater
3:2 PIO0_14. See description of bits 1:0. 0x2
5:4 PIO0_13. See description of bits 1:0. 0x2
7:6 PIO0_12. See description of bits 1:0. 0x2
9:8 PIO0_11. See description of bits 1:0. 0x2
11:10 PIO0_10. See description of bits 1:0. 0x2
13:12 PIO0_9. See description of bits 1:0. 0x2
15:14 PIO0_8. See description of bits 1:0. 0x2
17:16 PIO0_7. See description of bits 1:0. 0x2
19:18 PIO0_6. See description of bits 1:0. 0x2
21:20 PIO0_5. See description of bits 1:0. 0x2
23:22 PIO0_4. See description of bits 1:0. 0x2
25:24 PIO0_3. See description of bits 1:0. 0x2
27:26 PIO0_2. See description of bits 1:0. 0x2
29:28 PIO0_1. See description of bits 1:0. 0x2
31:30 PIO0_0. See description of bits 1:0. 0x2
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