Mesa 7I90HD User manual

7I90HD EPP/SPI/SERIAL
ANYTHING I/O
MANUAL
Version 1.7

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iii
Table of Contents
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
HARDWARE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GENERAL .................................................... 2
CONNECTOR POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5V I/O TOLERANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
FPGA FLASH SELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SECONDARY FLASH WRITE ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
RS-422 CABLE POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS . . . . . . . . 4
7I90HD I/O CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
POWER CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
JTAG CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EPP/SPI CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RS-422 CONNECTOR PIN-OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FPGA ....................................................... 11
HOST COMMUNICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EPP ........................................................ 11
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LBP ........................................................ 11
LBP16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LBP HOST INTERFACE (SSERIAL REMOTE) . . . . . . . . . . . . . . . . . . . . . . . 11
EPP HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LBP16 HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PC SERIAL HOST ADAPTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FALLBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DUAL EEPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
EEPROM LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
BITFILE FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MESAFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FREE EEPROM SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FALLBACK INDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FAILURE TO CONFIGURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CLOCK SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

iv
Table of Contents
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LEDS ....................................................... 21
PULLUP RESISTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I/O LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STARTUP I/O VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SUPPLIED CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
HOSTMOT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SVST8_4IM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SVST4_8 ............................................... 22
SVST8_8IM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SVST1_4_7I47S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2X7I65 ................................................. 22
SV12IM_2X7I48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SV6_7I49............................................... 22
PIN FILES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REFERENCE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LBP16LBP16 COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LBP16CRC ............................................. 25
LBP16 FRAMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
INFOAREA ............................................. 26
INFO AREA MEMSIZES FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INFO AREA MEMRANGES FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . 27
INFO AREA ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7I90HD SUPPORTED MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . 29
SPACE0: HOSTMOT2 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPACE3: FPGA FLASH EEPROM CHIP ACCESS . . . . . . . . . . . . . . . 31
FLASH MEMORY REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SPACE4: LBP TIMER/UTIL REGISTERS . . . . . . . . . . . . . . . . . . . . . . 34
SPACE6: LBP STATUS/CONTROL REGISTERS . . . . . . . . . . . . . . . . 35
MEMORY SPACE 6 LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ERROR REGISTER FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SPACE7: LBP READ ONLY INFORMATION . . . . . . . . . . . . . . . . . . . . 37
MEMORY SPACE 7 LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CARD DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7I90HD 1
GENERAL
DESCRIPTION
TheMESA7I90HD isaverylowcost,generalpurpose,FPGAbasedprogrammable
I/O card with a EPP parallel, RS-422 serial or SPI host interface.
Dual FPGA configuration EEPROMs allow simple recovery from programming
mistakes. Firmware modules are provided for hardware step generation, quadrature
encoder counting, PWM generation, digital I/O, Smart Serial remote I/O, BISS, SSI, SPI,
UART interfaces and more.
All motion control firmware is open source and easily modified to support new
functions or different mixes of functions.
All I/O bits are 5V tolerant and can sink 24 mA. All I/O pins support 3.3V LVDS
signaling. Socketed pullup resistors are provided for all pins so thattheymaybe connected
directly to opto-isolators, contacts etc.
The 7I90HD has 72 I/O bits available on three 50 pin connectors, all connectors use
I/O module rack compatible pinouts and are compatible with all Mesa 50 pin FPGA
daughtercards.

7I90HD 2
HARDWARE CONFIGURATION
GENERAL
Hardware setup jumper positions assume that the 7I90HD card is oriented in an
upright position, that is, with the EPP/SPI connector pointing towards the left.
CONNECTOR POWER
The 7I90HD has the option to supply 5V or 3.3V power from 7I90HDs I/O
connectors to daughtercards.
The power optionis individuallyselectable for each of thethree I/O connectors. The
5V power is protected by per connector PTC devices so will not cause damage to the
7I90HDorsystem ifaccidentallyshorted.Thedaughtercardvoltagealsoselectsthepullup
resistor supply voltage for each connector. Note that all current Mesa daughtercards use
5V.
JUMPER POS FUNCTION
W6 UP 5V DAUGHTERCARD AND PULLUP POWER
W6 DOWN 3.3V DAUGHTERCARD AND PULLUP POWER
5V I/O TOLERANCE
The FPGA used on the 7I90HD has a 4V absolute maximum input voltage
specification. To allow interfacing with 5V inputs, the 7I90HD has bus switches on all I/O
pins. The bus switches work by turning off when the input voltage exceeds a preset
threshold. The 5V I/O tolerance option is the default and should normally be left enabled.
For high speed applications where only 3.3V maximum signals are present and
overshoot clamping is desired, the 5V I/O tolerance option can be disabled. W1 controls
the 5V I/O tolerance option. When W1 is on the default UP position, 5V tolerance mode
is enabled. When W1 is in the DOWN position, 5V tolerance mode is disabled. Note that
W1 controls 5V tolerance on all I/O connectors.

7I90HD 3
HARDWARE CONFIGURATION
FPGA FLASH SELECT
To make recovery from FPGA configuration errors easier, there are two FPGA
configuration flash memories on the 7I90HD card. Jumper W3 selects between the two
flash memories. That is, if one flash memory is inadvertently corrupted, the other one can
be used to boot the 7I90HD, allowing the corrupted flash memory to be re-written. It is
suggested that W3 be left in the UP position (primary flash memory) for normal operation,
and only changed to the DOWN position (secondary flash memory) if configuration fails.
Once rebooted via a power cycle, jumper W3 should be promptly restored to the UP
position to allow the primary flash memory to be re-written.
W3 MEMORY
UP PRIMARY (NORMAL OPERATION)
DOWN SECONDARY (BACKUP)
SECONDARY FLASH WRITE ENABLE
To prevent accidentally overwriting the secondary FPGA configuration, a jumper
must be installed on jumper block W4 to enable writing to the secondary flash chip. When
W4 is not present, the secondary flash is read-only.
RS-422 CABLE POWER
The7I90HDcansupplyorsource5V powerfrom its RS-422connectorJ1if desired.
If cable power is selected, the 7I90 can be powered via a CAT5 interface cable. Cable
power is compatible with Mesa serial daughtercards. W5 controls the cable power option.
When W5 is in the up position, 5V power can be sourced or supplied by J1 pins 7 and 8.
When W5 is in the down position, J1 pins 7 and 8 are unconnected.

7I90HD 4
CONNECTORS
CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS

7I90HD 5
CONNECTORS
I/O CONNECTORS
The7I90HDhas3I/Oconnectors,P1throughP3.7I90HDIOconnectorpinoutsare
as follows:
P1 CONNECTOR PINOUT
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
1 IO0 2 GND 3 IO1 4 GND
5 IO2 6 GND 7 IO3 8 GND
9 IO4 10 GND 11 IO5 12 GND
13 IO6 14 GND 15 IO7 16 GND
17 IO8 18 GND 19 IO9 20 GND
21 IO10 22 GND 23 IO11 24 GND
25 IO12 26 GND 27 IO13 28 GND
29 IO14 30 GND 31 IO15 32 GND
33 IO16 34 GND 35 IO17 36 GND
37 IO18 38 GND 39 IO19 40 GND
41 IO20 42 GND 43 IO21 44 GND
45 IO22 46 GND 47 IO23 48 GND
49 POWER 50 GND

7I90HD 6
CONNECTORS
I/O CONNECTORS
P2 CONNECTOR PINOUT
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
1 IO24 2 GND 3 IO25 4 GND
5 IO26 6 GND 7 IO27 8 GND
9 IO28 10 GND 11 IO29 12 GND
13 IO30 14 GND 15 IO31 16 GND
17 IO32 18 GND 19 IO33 20 GND
21 IO34 22 GND 23 IO35 24 GND
25 IO36 26 GND 27 IO37 28 GND
29 IO38 30 GND 31 IO39 32 GND
33 IO40 34 GND 35 IO41 36 GND
37 IO42 38 GND 39 IO43 40 GND
41 IO44 42 GND 43 IO45 44 GND
45 IO46 46 GND 47 IO47 48 GND
49 POWER 50 GND

7I90HD 7
CONNECTORS
I/O CONNECTORS
P3 CONNECTOR PINOUT
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
1 IO48 2 GND 3 IO49 4 GND
5 IO50 6 GND 7 IO51 8 GND
9 IO52 10 GND 11 IO53 12 GND
13 IO54 14 GND 15 IO55 16 GND
17 IO56 18 GND 19 IO57 20 GND
21 IO58 22 GND 23 IO59 24 GND
25 IO60 26 GND 27 IO61 28 GND
29 IO62 30 GND 31 IO63 32 GND
33 IO64 34 GND 35 IO65 36 GND
37 IO66 38 GND 39 IO67 40 GND
41 IO68 42 GND 43 IO69 44 GND
45 IO70 46 GND 47 IO71 48 GND
49 POWER 50 GND

7I90HD 8
CONNECTORS
POWER CONNECTOR PINOUT
P7 is the 7I90HDs power connector. P7 is a 3.5MM plug-in screw terminal block.
P7 pinout is as follows:
PIN FUNCTION
1 +5V TOP, SQUARE PAD
2 GND BOTTOM, ROUND PAD
JTAG CONNECTOR PINOUT
P6 is a JTAG programming connector. This is normally used only for debugging or
if both EEPROM configurations have been corrupted. In case of corrupted EEPROM
contents the EEPROM can be re-programmed using Xilinx’s Impact tool.
P6 JTAG CONNECTOR PINOUT
PIN FUNCTION
1 TMS
2 TDI
3 TDO
4 TCK
5 GND
6 +3.3V

7I90HD 9
CONNECTORS
EPP/SPI CONNECTOR
P4 is the EPP printer port / SPI host interface connector. P4 is a 26 pinheader. P4's
pin-out matches stands DB25 printer port pin-out, allowing a simple flat cable with a
DB25M IDC connector on one end and a 26 pin female header on the other end to
interface the hosts printer port to the 7I90HD.
P4 PIN DB25 PIN SIGNAL P4 PIN DB25 PIN SIGNAL
1 1 /STROBE 2 14 /AUTOFD
3 2 PD0 4 15 /FAULT
5 3 PD1 6 16 /INIT
7 4 PD2 8 17 /SELECTIN
9 5 PD3 10 18 GND
11 6 PD4 - SPICLK 12 19 GND
13 7 PD5 - SPIIN 14 20 GND
15 8 PD6 - SPIOUT 16 21 GND
17 9 PD7 - /SPICS 18 22 GND
19 10 /ACK 20 23 GND
21 11 BUSY 22 24 GND
23 12 PERROR 24 25 GND
25 13 SELECT 26 VCC

7I90HD 10
CONNECTORS
RS-422 CONNECTOR
J1 is the 7I90HDs RS-422 serial interface. J1 is a RJ-45 jack. The serial interface
pinout is compatible with standard 8 wire CAT5 Ethernet cables. J1 pinout is as follows:
PIN SIGNAL DIR EIA/TIA 568B COLOR
1 RXA TO 7I90HD ORANGE WHITE
2 RXB TO 7I90HD ORANGE
3 TXA FROM 7I90HD GREEN WHITE
4 GND EITHER BLUE
5 GND EITHER BLUE WHITE
6 TXB FROM 7I90HD GREEN
7 +5V EITHER BROWN WHITE (5V if W5 is up)
8 +5V EITHER BROWN (5V if W5 is up)
J1s pinout is designed to match breakout cards like the 7I44 and 7I74. A standard
CAT5 or CAT5E cable can be used to connect the 7I90HD to a 7I44/7I74. CAT5E cable
is suggested if the serial cable is used for powering the 7I90HD, as the larger wire size
result in lower voltage drop.

7I90HD 11
OPERATION
FPGA
The 7I90HD use a Xilinx Spartan6 FPGA in a 144 pin TQFP package: XC6SLX9-
TQG144.
HOST COMMUNICATION
Currentytherearefourdifferenthostcommunicationoptionsavailablewithstandard
7I90HD firmware: EPP parallel and SPI (on P4) a LBP sserial slave and LBP16 remote
HostMot2usingtheRS-422interface.EPP,SPI,andLBP16canbeusedashostinterfaces
to the HostMot2 suite of I/O firmware, while the LBP implementation is used for a simple
fixed purpose Smart Serial 72 bit I/O device.
EPP The 7I90HDs EPP interface allows the 7I90HD to interface to PC parallel ports
giving a medium speed real time interface (~1 Mbyte/sec) suited to motion control
applications like LinuxCNC.
SPI The 7I90HD SPI interface is also a medium speed real time (~1 to 5 Mbytes/sec)
interface that allows simple interfacing to microcontrollers and SOCs.
LBP LBP is a simple binaryserial master slave protocol. The LBP implementation in the
7I90HD allows the 7I90HDto be use as a simple 72 I/O Smart Serial slave for remote TTL
level interfacing.
LBP16LBP16 is a simple binary serial master slave protocol suited to larger data blocks
than LBP. LBP16 allows very large I/O expansion capabilities while maintaining a simple
real time interface.
LBP HOST INTERFACE
The7I90canimplementasimpleremotesserialinterfaceusingLBP.Thisinterface
provides 72 I/O bits and is appropriate for applications likeOPTO22module rack I/O. The
bit file for this mode is 7i90_ssremote.bit. For compatibility with I/O module racks, all I/O
is open drain and active low. This allows any IO pin to be used as an input or output.
Active low means a true input or output bit at the host is low at the 7I90 I/O pins. Pins that
are used as inputs must have their corresponding outputs in the false state. In addition to
the 72 GPIO bits, Three quadrature MPG counters are implemented on GPIO bits 48
through 53: 48=A0,49=B0,50=A1,51=B1,52=A2,53=B2.
A 50 ms watchdog timer is implemented and will set all outputs to a high state (via
I/O pullups) if valid communications are not received at faster than a 50 ms/packet rate.

7I90HD 12
OPERATION
EPP HOST INTERFACE
The EPP host interface option allows the 7I90HD to connect to EPP compatible
parallel port on PCs for a medium speed real time interface. The interface from host EPP
printer port to the FPGA uses 12 FPGA pins. These consist of an eight bit bidirectional
data bus (D0..D7), and four handshake lines.
P4 PIN EPPNAME SPPNAME FPGA PIN DIRECTION
1 /WRITE /STROBE 40 TO FPGA
2 /DSTROBE /AUTOFD 41 TO FPGA
8 /ASTROBE /SELECTIN 48 TO FPGA
21 WAIT BUSY 61 FROM FPGA
3 D0 D0 43 BIDIR
5 D1 D1 45 BIDIR
7 D2 D2 47 BIDIR
9 D3 D3 51 BIDIR
11 D4 D4 55 BIDIR
13 D5 D5 56 BIDIR
15 D6 D6 57 BIDIR
17 D7 D7 58 BIDIR
With standard HostMot2 EPP configurations, minumum AStrobe and Dstrobe
durations are 200 nS. Read data is availablein less than 70 nS from the strobe. Write data
is sampled by the 7I90 180 nS from the beginning of the strobe, and wait is deasserted
200 nS from the beginning of the strobe.

7I90HD 13
OPERATION
SPI HOST INTERFACE
GENERAL
The SPI host interface is a medium speed real time host interface with a low pin
count for microcontrollers and SOC’s that have built in SPI interface hardware. The
7I90HDs SPI interface is a slave interface and uses a SPI frame size of 32 bits for all
transactions. The interface supports a SPI clock rate up to 50 MHz.
SPI MODE
The host interface uses the convention that the clock idles low, host data is shifted
into the 7I90HD on the SPI clock rising edge, and data is shifted out of the 7I90HD on the
clock fallingedge. ThismatchesSPImastersetupwithCPOL=0andCPHA=0.TheCSpin
is active low. To support the highest transfer rates the master should have a "late sample"
option.
SPI HEADER
SPItransactionsalwaysstartswitha32bitheaderwhichcontainsthetargetregister
address, the read or write command, the number of data elements to be transferred and
the address increment bit.
SPI HEADER
AAAAAAAAAAAAAAAACCCC I NNNNNNNXXXX
The first 16 bits ("A" in the table above) are the HostMot2 register address (byte
address), MSb first. The next 4 bits ("C") are the command. Currently only 2 commands
are supported, read (0xA) and write (0xB). The next bit ("I") is the address increment bit.
When this bit is set, the register address is incremented (by 4) after every register
read/write access, allowing burst transfers from groups of sequential registers without
requiring a new address to be sent. Burst transfers with the increment bit cleared can be
usedformultiplereads/writestoasingleaddressforFIFOaccessandsimilarapplications.
The next 7 bits ("N") are the burst length for sequential transfers.Valid burst lengths are 1
through 127. The "X" bits are unused.
TRANSFER SEQUENCE
For SPI reads the master sends the header followed by N frames of 32 dummy (0)
bits, N being the burst length specified in the SPI header. The read data is returned on
each 32 bit frame after the header frame.
On writes, the N frames of write data are sent by the master following the SPI
header. The 7I90HD returns dummy data when write data is being received.

7I90HD 14
OPERATION
SPI HOST INTERFACE
DATA TRANSFER SEQUENCE
Example 1: Read 3 doublewords starting at 0x1000 with increment.
Master asserts /CS
Master sends 0x1000A830 7I90HD echos dummy data
Master sends 0x00000000 7I90HD echos register data @0x1000
Master sends 0x00000000 7I90HD echos register data @0x1004
Master sends 0x00000000 7I90HD echos register data @0x1008
Master de-asserts /CS
Example 2: Write 4 doublewords (A,B,C,D) to location 0x600C:
Master asserts /CS
Master sends 0x600CB040 7I90HD echos dummy data
Master sends 0x0000000A 7I90HD echos dummy data
Master sends 0x0000000B 7I90HD echos dummy data
Master sends 0x0000000C 7I90HD echos dummy data
Master sends 0x0000000D 7I90HD echos dummy data
Master de-asserts /CS
Themastermayde-assert/CSbetweenframesorleaveitassertedwithoutaffecting
the SPI interface behavior as long as the CS idle time does not exceed the burst timeout
value.
BURST TIMEOUT
Because the 7I90HD’s SPI interface supports burst transfers of programmable
length, its possible that an aborted or incorrect command could leave the 7I90HD in an
unknown state. To recover from this condition, the 7I90HDs SPI interface has a timeout
on bursts. The default timeout is 50 uSec. If /CS is de-asserted for 50 usec, the SPI
interface will be reset (and any pending burst aborted) so that it expects a SPI header (a
newcommand) as the next frame. A side effect of this timeout is that abursttransfer must
never de-assert /CS for longer than 50 uSec during a burst.
SPI SIGNAL INTEGRITY
When using the SPI interface, signal quality is of very high importance. For best
signal quality you should always use a flatcable with all 8 ground wires on P4 connected
to the SPI master. In addition, the SPI master clock signal should be series terminated so
that it has a 130 Ohm total source resistance to match the flat cable impedance. This
typically means adding a ~47 Ohm series resistor in the SPI CLK line at the master end.

7I90HD 15
OPERATION
LBP16 HOST INTERFACE
GENERAL
The LBP16 serial host interface is a high speed (to 10 Mbits/sec) RS-422 host
interface suited to remote data acquisition anddistributedI/O systems. Like the otherhost
interfaces the LBP16 allows all of the standard HostMot2 I/O modules to be used. LBP16
uses standard asynchronous communication.
CONNECTIONS
The RJ45 connector J1 is used for LBP16 serial communications. This connector
matches the pinout of MESAs 7I74 and 7I44 daughtercards for FPGA host interfaces, so
only a standard CAT5 cable is needed.
SETUP OPTIONS
The current LBP16 firmware has no EEPROM setup options but has 2 jumper
selectable options, Low_Baud and CRC_Disable. These options are intended to simplify
testing and allow 115200 baud rate for firmware updating via normal USB-serial adapters.
These options are selected by grounding pins on the EPP/SPI interface connector. This
can be accomplished easily by installing standard .1" shunts across pins on P4 since the
even numbered pins are grounded and the signal pins have pullup resistors.
HIGH (OPEN) LOW (SHORTED)
P4 pins 23,24 2.5 M Baud 115.2 K Baud
P4 pins 21,22 CRC enabled CRC disabled
Note that setting the low baud rate option sets the packet framing timeout to 25
charactertimesinsteadof thenormal2charactertimes.Thisistomakeaccess easierwith
standard serial ports and USB/serial adapters.
PROTOCOL
For detailed information on the LBP16 serial protocol, see the reference section of
this manual

7I90HD 16
OPERATION
PC HOST ADAPTER
In orderto run any of the serial command line utilities a RS-422 adapter is needed.
Mesacanprovideasuitableadapter.Twosuchadaptersare 3I21or3I22.Theseadapters
connects the RJ-45 RS-422 interface on the 7I90HD to a DB9 serial port (3I21) or USB
port (3I22) and provide 5V link power.
MINIMAL HOST PC ADAPTER
A simple home made host adapter can be made by directly connecting RS-232
signals from a 9 pin PC serial port or USB RS-232 adapter to the 7I90HD’s RS-422
signals via a one ended CAT5 cable. A single resistor between RS-232 TXD and RS-422
RXB is needed to prevent overloading the RS-232 TXD output
CAT5 PIN DE-9F PIN CAT5 SIGNAL DE-9F SIGNAL CAT5 COLOR
1 5 RXA GND ORANGE WHITE
2 3 RXB (1) TXD (1) ORANGE
3 XX TXA XX GREEN WHITE
4 5 GND GND BLUE
5 5 GND GND BLUE WHITE
6 2 TXB RXD GREEN
7 XX +5V (2) XX BROWN WHITE
8 XX +5V (2) XX BROWN
Notes:
1. Connect via 470 Ohm 1/4 watt resistor. All other signals directly connected
2. If not supplied by the adapter, +5V power must be supplied via the 7I90HDs 5V power
connector P7