NyQuest Innovation Labs NY6 Series Configuration guide

USER MANUEL
NY6 Series
Single-Chip 4-bit MCU with 8~24 I/O,
6
-ch Speech/MIDI Synthesizer
Version 1.3
Mar. 28, 2019
NYQUEST TECHNOLOGY CO. reserves the right to change this document without prior notice. Information provided by NYQUEST is believed to be accurate and reliable.
However, NYQUEST makes no warranty for any errors which may appear in this document. Contact NYQUEST to obtain the latest version of device specifications before
placing your orders. No responsibility is assumed by NYQUEST for any infringement of patent or other rights of third parties which may result from its use. In addition,
NYQUEST prod
ucts are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a m
alfunction or failure of the product
may reasonably be expected to result in significant injury to the user, without the express wr
itten approval of NYQUEST.

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Revision History
Version Date Description Modified Page
1.0 2016/08/31 Formal release. -
1.1 2016/11/25
1. Modify pad description.
2. Update DC characteristics.
3. Fix typos.
10
11
-
1.2 2017/05/17 1. Add description that a 0.1uF power capacitor nearby PB_VDD is
necessary if LDO regulator is enabled.
26
1.3 2019/03/28 Remove NY6C450A / NY6C520A / NY6C640A / NY6C720A. -

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Table of Contents
Chapter 1. Introduction ........................................................................................................... 6
1.1 General Description ...........................................................................................................6
1.2 Features.............................................................................................................................6
1.3 Product List ........................................................................................................................9
1.4 Block Diagram..................................................................................................................10
1.5 Pad Description................................................................................................................10
1.6 Electrical Characteristics ..................................................................................................11
1.6.1 Absolute Maximum Rating .................................................................................................. 11
1.6.2 DC Characteristics............................................................................................................... 11
Chapter 2. Hardware Architecture........................................................................................ 12
2.1 Overview ..........................................................................................................................12
2.1.1 Function Block Diagram ...................................................................................................... 12
2.1.2 Hardware Summary Table................................................................................................... 12
2.2 Clock Generator ...............................................................................................................13
2.3 System Reset...................................................................................................................14
2.3.1 Power-On Reset (POR)....................................................................................................... 14
2.3.2 Low Voltage Reset (LVR) .................................................................................................... 14
2.3.3 Watch-Dog Timer Reset (WDTR)........................................................................................ 14
2.3.4 I/O Port External Reset........................................................................................................ 14
2.4 Address Pointer................................................................................................................15
2.4.1 Program Counter (PC)......................................................................................................... 15
2.4.2 Stack (STK) ......................................................................................................................... 15
2.4.3 Multi-function Register Pointer (RPT).................................................................................. 15
2.4.4 Head Voice Pointer (HVPR) & Tail Voice Pointer (TVPR) .................................................. 16
2.4.5 Data Pointer (DPR).............................................................................................................. 16
2.5 Arithmetic Logic Unit (ALU) ..............................................................................................17
2.5.1 ALU Instruction Summary.................................................................................................... 17
2.5.2 ALU Related Status Flag ..................................................................................................... 19
2.6 Memory Organization .......................................................................................................19
2.6.1 ROM .................................................................................................................................... 19
2.6.2 RAM..................................................................................................................................... 20
2.7 I/O Ports...........................................................................................................................20
2.7.1 Pull-High Input Mode ........................................................................................................... 21
2.7.2 Floating Input Mode............................................................................................................. 21
2.7.3 Output Mode ........................................................................................................................ 22
2.7.4 I/O Pin Mask Option ............................................................................................................ 22
2.8 Infrared Transmitter..........................................................................................................23

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2.9 Interrupt Generator...........................................................................................................24
2.10 SPI Control Interface........................................................................................................25
2.11 Comparator ......................................................................................................................25
2.12 LDO Regulator .................................................................................................................26
2.13 Low Voltage Detector (LVD).............................................................................................26
2.14 Audio Synthesizer Structure .............................................................................................26
2.14.1 Speech Synthesis................................................................................................................ 27
2.14.2 MIDI Synthesis .................................................................................................................... 27
2.14.3 PH Value ............................................................................................................................. 28
2.14.4 Audio Output........................................................................................................................ 28
2.14.5 Envelope Control ................................................................................................................. 29
2.14.6 Volume Control.................................................................................................................... 29
Chapter 3. System Control.................................................................................................... 30
3.1 Introduction ......................................................................................................................30
3.1.1 System Register Address Map ............................................................................................ 30
3.1.2 Memory Register Address Map........................................................................................... 33
3.2 RPT..................................................................................................................................33
3.3 ROD.................................................................................................................................34
3.4 INTx / INTFx ($0 ~ $03)....................................................................................................34
3.5 BTF ($04).........................................................................................................................34
3.6 ONOFF ($05) ...................................................................................................................35
3.7 LVD ($0A) ........................................................................................................................35
3.8 TMCS ($0B) .....................................................................................................................35
3.9 RTMx ($0C/$0D) ..............................................................................................................35
3.10 XMDx ($0E/$0F) ..............................................................................................................36
3.11 SPIV ($10) .......................................................................................................................36
3.12 SPIC ($11) .......................................................................................................................36
3.13 SPIDx ($12/$13)...............................................................................................................37
3.14 I/O Ports Register ($14 ~ $1F) .........................................................................................37
3.15 Audio Control Register .....................................................................................................38
3.15.1 CHARC ................................................................................................................................ 38
3.15.2 DECMDx.............................................................................................................................. 38
3.15.3 VOL...................................................................................................................................... 39
3.16 Register Without Address Mapping ..................................................................................39
3.16.1 BANK ................................................................................................................................... 39
3.16.2 PAGE................................................................................................................................... 39
3.16.3 CHNM.................................................................................................................................. 40
3.16.4 ENV ..................................................................................................................................... 40
3.16.5 Head Play Flag .................................................................................................................... 40

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3.16.6 Play Flag.............................................................................................................................. 40
3.16.7 PH Value Setting ................................................................................................................. 41
3.16.8 Mixer Data ........................................................................................................................... 41
3.17 Audio Playback ................................................................................................................42
3.17.1 Voice Playback .................................................................................................................... 42
3.17.2 Melody Playback, Head-Only Mode .................................................................................... 45
3.17.3 Melody Playback, Tail-Only Mode....................................................................................... 48
3.17.4 Melody Playback, Head+Tail Mode..................................................................................... 51
3.17.5 Ramp-up/Ramp-down Procedure for DAC.......................................................................... 55
3.18 Power Saving Mode .........................................................................................................58
3.18.1 Slow Mode ........................................................................................................................... 58
3.18.2 Halt Mode ............................................................................................................................ 58
Chapter 4. Instruction Set ..................................................................................................... 59
4.1 Instruction Classified Table ..............................................................................................59
4.2 Instruction Descriptions....................................................................................................62
4.2.1 Arithmetic Instructions ......................................................................................................... 62
4.2.2 Conditional Instructions ....................................................................................................... 69
4.2.3 Audio Instructions ................................................................................................................ 71
4.2.4 Other Instructions ................................................................................................................ 77

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Chapter 1. Introduction
1.1 General Description
The NY6 series IC is a powerful 4-bit micro-controller based sound processor. There are 6 channels that
are configured as speech or MIDI, and all of these 6 channels or part of them can be played with speech or
MIDI simultaneously. By using the high fidelity 4-bit, 5-bit mixed ADPCM or PCM speech/ MIDI timbre
synthesis algorithm with up to 44.1KHz sample rate, NY6 produces high quality voices. As NY6 is specially
designed for MIDI synthesis application, it provides Attack-Decay-Sustain-Release method (ADSR) with
256-level envelope for Patch (instrument) synthesis. NY6 can precisely synthesize any tone frequency of
MIDI with +/- 0.5% accurate internal oscillation and automatic Tone-Calibration. Therefore NY6 melody
quality is very close to real instrument.
Moreover, NY6 is equipped with new Nyquest’s developed high-quality noise filtering algorithm of 250KHz
over-sampling, which can remove noise in order to improve speech and melody quality greatly. Up to 16-
level digital volume can be applied to final synthetic speech or melody that is tailored for applications of
volume adjustment. NY6 provides two kinds of audio outputs with fine resolution, one is 12-bit current-type
D/A converter (DAC) and the other is 12-bit Pulse-Width-Modulation (PWM). Therefore NY6 speech/
melody quality is the best choice among all solutions.
Hardware SPI (Mode0/Mode3) is supported for Channel-0 voice data automatically (auto mode, 24-bit
addressing capability) and user data (user mode) fetch from external SPI memory. Voltage comparator is
built-in for analog signal detecting applications. Software low voltage reset counting mechanism is provided
for low power management.
The RISC MCU architecture is very easy to program and control, various applications can be easily
implemented. There are 75 instructions, and most of them are executed in single cycle. Besides normal
operation mode, NY6 also provides Halt mode (or Sleep mode) and Slow mode to minimize power
dissipation.
1.2 Features
Wide operating voltage range: 2.0V to 5.5V.
4-bit RISC type micro-controller with 75 instructions.
NY6A have 10 items. 160K x 10-bit ROM is the maximum size.
NY6B have 11 items. 208K x 10-bit ROM is the maximum size.
NY6C have 12 items. 1728K x 10-bit ROM is the maximum size.
336x4-bit RAM, divided into 6 pages.
2MHz system clock for instruction execution.

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Slow mode to operate with low power consumption (+/-3.0% accuracy).
Halt mode to save power, less than 1uA@3V standby current.
Built-in RC oscillation is accurate with +/- 0.5% frequency deviation.
Low voltage reset (LVR=1.9V) and watch-dog reset (WDT) are supported to protect the system.
Special hardware for LVR occurrence counting by program to manage low battery system operation.
One interrupt entrance for multiple interrupt sources with an independent stack.
8-bit timer counter is applied to multiple clock source for various application.
Low Voltage Detector (LVD) is built-in for monitoring the status of power and protect malfunction if
unstable power is given. (NY6A doesn’t support LVD function)
LDO regulator is supported for the power supply of SPI flash. (NY6A doesn’t support LDO function)
Hardware SPI for external SPI devices data access. Dual power system operation supported (ex: NY6
@ 5V, SPI @ 3V).
Up to 24 flexible Bi-direction I/Os. Direction of each I/O is independently controlled by individual register
bit.
Each Bi-direction I/O pin can be optioned as different input and output function. For the input option,
users can select one of three kinds of option: input with pull-high resistor, input without pull-high
resistor, or input with register-controlled pull-high resistor (high-to-low wakeup only). For the output
option, users can select one of three kinds of option: output with normal drive/sink sink current, large
sink current or constant sink current. (Mask option)
Shared pins to provide IR carrier, comparator, SPI interface and external reset feature. (Mask option)
Shared Pin Function NY6A NY6B/NY6C
External reset (Reset) PA3/Reset PA3/Reset
IR carrier (IR) PA2/IR PA2/IR
Comparator
N/A PA1/VIN
N/A PA0/VIP
SPI
N/A PB0/CSb
N/A PB1/SCK
N/A PB2/SDO (MOSI)
N/A PB3/SDI (MISO)
(NY6A doesn’t support the Comparator and SPI function)
Selection of IR carrier frequency and data high/low IR output is supported.

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Built-in voltage comparator for analog signal detection applications. Comparator output flag can be
configured to generate interrupt and wakeup. Also, the flag can be used for timer counter clock source
for specific application. (NY6A doesn’t support Comparator function)
Maximum of 6 channels can be played simultaneously, and each channel can be arbitrarily assigned as
speech or MIDI channel.
New high fidelity 4-bit / 5-bit mixed ADPCM or 10-bit PCM speech synthesis algorithm and ADSR with
256-step envelope for MIDI synthesis.
Patented noise filtering algorithm with 250KHz over sampling to enhance signal-to-noise ratio and
provide excellent sound quality without ROM size increase.
16-level digital volume control for synthetic speech/melody.
Built-in hardware automatic Tone-Calibration of near-zero frequency deviation for precise tone
frequency.
High quality 12-bit D/A converter or 12-bit PWM driver. (NY6A doesn’t support DAC output)
PWM driver can be normal PWM or Ultra PWM.

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1.3 Product List
P/N Voice Duration
@6KHz (sec)
ROM Size
(bit)
Program ROM
Size (bit) I/O PWM DAC
NY6A003A 3.3 12K x 10 12K x 10 8 12-bit -
NY6A005A 5 16K x 10 16K x 10 8 12-bit -
NY6A008A 8.3 24K x 10 24K x 10 8 12-bit -
NY6A011A 11.7 32K x 10 32K x 10 8 12-bit -
NY6A018A 18.3 48K x 10 48K x 10 8 12-bit -
NY6A025A 25 64K x 10 64K x 10 8 12-bit -
NY6A035A 35 88K x 10 64K x 10 8 12-bit -
NY6A045A 45 112K x 10 64K x 10 8 12-bit -
NY6A055A 55 136K x 10 64K x 10 8 12-bit -
NY6A065A 65 160K x 10 64K x 10 8 12-bit -
NY6B005A 5 16K x 10 16K x 10 16 12-bit 12-bit
NY6B008A 8.3 24K x 10 24K x 10 16 12-bit 12-bit
NY6B011A 11.7 32K x 10 32K x 10 16 12-bit 12-bit
NY6B018A 18.3 48K x 10 48K x 10 16 12-bit 12-bit
NY6B025A 25 64K x 10 64K x 10 16 12-bit 12-bit
NY6B035A 35 88K x 10 64K x 10 16 12-bit 12-bit
NY6B045A 45 112K x 10 64K x 10 16 12-bit 12-bit
NY6B055A 55 136K x 10 64K x 10 16 12-bit 12-bit
NY6B065A 65 160K x 10 64K x 10 16 12-bit 12-bit
NY6B075A 75 184K x 10 64K x 10 16 12-bit 12-bit
NY6B085A 85 208K x 10 64K x 10 16 12-bit 12-bit
NY6C112A 111.7 272K x 10 64K x 10 24 12-bit 12-bit
NY6C132A 131.7 320K x 10 64K x 10 24 12-bit 12-bit
NY6C158A 158.3 384K x 10 64K x 10 24 12-bit 12-bit
NY6C185A 185 448K x 10 64K x 10 24 12-bit 12-bit
NY6C225A 225 544K x 10 64K x 10 24 12-bit 12-bit
NY6C265A 265 640K x 10 64K x 10 24 12-bit 12-bit
NY6C305A 305 736K x 10 64K x 10 24 12-bit 12-bit
NY6C345A 345 832K x 10 64K x 10 24 12-bit 12-bit

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1.4 Block Diagram
1.5 Pad Description
Pin ATTR. Description
VDD1~3 Power Positive power.
GND1~4 Power Negative power.
PA0/VIP I/O Bit 0 for Port A, or positive input of comparator.
PA1/VIN I/O Bit 1 for Port A, or negative input of comparator.
PA2/IR I/O Bit 2 for Port A, or IR carrier output.
PA3/Reset I/O Bit 3 for Port A, or external reset input.
PB_VDD Power Power for PBx and external component. (Not available for NY6A)
PB0/CSb I/O Bit 0 for Port B, or chip select pin for SPI interface.
PB1/SCK I/O Bit 1 for Port B, or serial clock pin for SPI interface.
PB2/SDO I/O Bit 2 for Port B, or serial data output pin (MOSI) for SPI interface.
PB3/SDI I/O Bit 3 for Port B, or serial data input pin (MISO) for SPI interface.
PC0~3 I/O Bit 0~3 for Port C.
PD0~3 I/O Bit 0~3 for Port D.
PE0~3 I/O Bit 0~3 for Port E.
PF0~3 I/O Bit 0~3 for Port F.
PWM1/DAC O PWM1 output or DAC output.
PWM2 O PWM2 output.
* NY6A: PA0~PB3. (There is no Comparator, LVD, LDO, SPI, and DAC function.)

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1.6 Electrical Characteristics
The following table lists the electrical characteristics. All the product’s properties must refer to each part’s
datasheet.
1.6.1 Absolute Maximum Rating
Symbol
Parameter
Rated Value
Unit
VDD - VSS
Supply voltage
-0.5 ~ +6.0
V
VIN Input voltage VSS–0.3V ~ VDD+0.3 V
TOP
Operating Temperature
0 ~ +70
°C
TST Storage Temperature -25 ~ +85 °C
1.6.2 DC Characteristics
Symbol
Parameter
V
DD
Min.
Typ.
Max.
Unit
Condition
VDD
Operating voltage
--
2.0
3.0
5.5
V
2MHz.
ISB
Supply
current
Halt mode
3.0
0.1
0.5
uA Sleep, no load.
4.5
0.1
0.5
ISL Slow mode
3.0
50
uA BT=16.384ms, no load
4.5
80
IOP Normal mode
3.0
1.8
mA 2MHz, no loading
4.5
5.0
IIL
Input current
(Internal
pull-high)
Weak
(1.2M ohms)
3.0
2.5
uA
VIL=0V
4.5
7.4
Strong
(100k ohms)
3.0
30
uA
4.5
75
IOH Output high current
3.0
-7
mA
VOH=2.0V
4.5
-11
VOH=3.5V
IOL
Output low current
(Normal current)
3.0
10
mA
VOL=1.0V
4.5
16
Output low current
(Large current)
3.0
20
mA
4.5
30
Output low current
(Constant current)
3.0
18
mA
4.5
21
IDAC
DAC output current
3.0
1.4
mA
Half-scale
IPWM
PWM output current
(Normal PWM)
3.0
60
mA
Load=8 ohms
4.5
100
PWM output current
(Ultra PWM)
3.0
80
mA
4.5
125
∆F/F Frequency deviation
by voltage drop
3.0 -0.5
%
Fosc(3.0v)-Fosc(2.4v)
Fosc(3v)
4.5 0.5 Fosc(4.5v)-Fosc(3.0v)
Fosc(4.5v)
∆F/F Frequency lot deviation 3.0 -0.5 0.5 % Fmax(3.0v)-Fmin(3.0v)
Fmax(3.0v)
Fosc Oscillation Frequency - 1.90 2 2.05 MHz VDD=2.0~5.5V

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Chapter 2. Hardware Architecture
2.1 Overview
2.1.1 Function Block Diagram
2.1.2 Hardware Summary Table
Name
Function
Address
HVPR0~5 Voice Head pointer according to CHNM.
TVPR0~5 Voice Tail pointer according to CHNM
DPR0~7 Data pointer (share with STK7~0)
STK0~7 8-level interrupt dedicated stack(share with DPR0~7)
PC Program counter
RPT Multi-function register pointer M[0x0 ~ 0x5]
XMD Indexed RAM data access register T[0xE~0xF]
RAM 336 nibbles RAM (6 pages, each 56 nibbles)
ROM Program & data ROM
ROD1 ROM[7:4] data access register M[0x6]
ROD2[1:0] ROM[9:8] data access register M[0x7]
INST Instruction register

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Name
Function
Address
INST DEC Instruction decoder
BANK Program Bank Register
AUD DEC Audio decoder
DECMDx PCM / ADPCM control register T[0x7 ~ 0x8]
CHNM Active channel select
ENV0~5 8-bit Envelope of CHNM
Multiplier Hardware multiplier for MIDI
VOL Digital volume control register T[0x9]
CHARC Mix Channel#, Output choice T[0x6]
Mixer Channels audio data mixer
PWM / DAC PWM, D/A audio output
Clock Generator Ring oscillator clock generator
WDT Watch-dog timer and reset generator
BT System base timer
PHC PH Counter
TM Timer Counter T[0xC ~ 0xD]
INTx Interrupt generator T[0x0 ~ 0x1]
LVD Low Voltage Detector T[0x0A]
SYS Reset System reset generator
POR Power reset generator
LVR Low Voltage Reset
ACC 4-bit accumulator
ALU 4-bit arithmetic logic unit
C Carry flag for arithmetic
Z Zero flag for arithmetic
COMP Comparator
SPI SPI Control Interface T[0x10 ~ 0x11]
IR Infrared transmit block
LDO LDO Regulator for PB port (SPI Application) T[0x10]
I/O Ports I/O port register T[0x14 ~ 0x1F]
*T[] : System register and the hex number 0x? Between the brackets means its address.
*M[] : Memory register and the hex number 0x? Between the brackets means its address.
2.2 Clock Generator
The clock generator is a Ring oscillator, and users can only select the internal resistor oscillation (INT-R).
The INT-R oscillator accuracy is up to ± 0.5%.

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2.3 System Reset
Reset Reset Initialization Normal Operation
18 / 131 ms
Reset Reset Initialization Normal Operation
Reset Vector
Reset Initialization Procedure
2.3.1 Power-On Reset (POR)
After Power-on, the power-on reset initialization will automatically be set out. After the system leaves
the reset initialization procedure, it enters the normal operation and the program counter starts at the
reset vector. POR set a POR flag to high for system low voltage management. It can be cleared by
user.
2.3.2 Low Voltage Reset (LVR)
When the system enters the normal operation, the power supply voltage must be kept in an effective
working voltage range. When the power supply voltage is lower than the effective working voltage
range, the system can’t work properly. To prevent the system crash, we have a low voltage detector in
the NY6 IC. When the detector detects a harmful low voltage supply, it will cause a low voltage reset.
The so-called “low voltage” point of the NY6 IC is approximate 1.9V. RAM (Pages5 $3E, $3F) are
optioned to be protected for the record of LVR occurrence times of system low voltage management.
2.3.3 Watch-Dog Timer Reset (WDTR)
To recover from program function, the NY6 IC supports an embedded watch-dog timer reset. The
WDTR function always works with the program executing. Users have to clear the WDT periodically to
prevent from timing up with a reset generation. Typically, the minimum time-up period of the WDT is
about 240ms and users can clear WDT through instruction CWDT0 and CWDT1.
2.3.4 I/O Port External Reset
The PA3/Reset I/O pin of the NY6 can be optioned as a reset pin. A reset pin should always be pulled-
high in normal operation, whether users use the built-in internal pull-high resister option or use an
external pull-high resister on PCB with internal pull-high resister option disabled. When the reset pin
falls to the ground level, it generates an external reset.

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2.4 Address Pointer
The NY6 micro-controller contains a program counter (PC), a multi-function register pointer (RPT), 6 head
pointers (HVPR0~5) and 6 tail pointers (TVPR0~5) for channel 0~5 and 8 data pointers (DPR) which are
shared with interrupt stack (STK). Particularly, the address of DPR is indexed by CHNM register, but the
STK is nested type which starts from index 7 for STK0, ex. DPR0 is same address as STK7. The length of
each address pointer is 21-bit maximum, depends on the product parts. Users have to keep in mind that
the initial value of all the pointers is unknown, except the PC and RPT.
2.4.1 Program Counter (PC)
As a program instruction is executed, the PC will contain the address of the next program instruction to
be executed. PC is 18-bit wide for NY6A/NY6B and 21-bit wide for NY6C. The PC starts from the reset
vector (address 0x000000) after the system reset, and its value is increased by one every instruction
cycle unless changed by an interrupt or a branch instructions which are listed in table below. The
interrupt vector is at address 0x000010.
Inst./Event Function
JMP Addr Jump to {BANK, Addr}.
CALL Addr Push the PC+2 to the STK and load {BANK, Addr} to PC.
Interrupt Push PC+1 to STK automatically.
RET Pop STK back to PC. Return to the main program from subroutine
IRET Pop STK back to PC. Return to the main program from the interrupt routine.
Addr : 16-bit immediate address.
2.4.2 Stack (STK)
Eight level hardware push/pop stacks are available which are reacted to CALL or interrupt occurrence.
When an interrupt/CALL takes apart, the system pushes PC+1/PC+2 to STK automatically. When the
program returns to the main program from subroutine / the interrupt routine by RET / IRET instruction,
the system pops the STK back to the PC. Unused STK can be used as DPR. The STK max width is 18
bits for NY6A and 21 bits for NY6B/NY6C.
2.4.3 Multi-function Register Pointer (RPT)
As implied in the name, RPT are multi-function registers. There are at most six RPT that are RPT0,
RPT1, RPT2, RPT3, RPT4 and RPT5. RPT0~RPT4 are 4-bit wide and RPT5 is 1-bit wide, i.e. RPT5[0].
The RPT max width is 18 bits for NY6A/6B and 21 bits for NY6C. Users have to operate RPT in
coordination with instructions below.

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Inst./Event Function
LDEN Load RPT[7:0] to ENV, according to CHNM.
RBEN Load ENV to RPT[7:0], according to CHNM
PLAY Play RPT to HVPR, according to CHNM.
LDSEC Load RPT to TVPR, according to CHNM.
LDPH Load RPT[11:0] to PH, according to CHNM.
RBVPR Read HVPR to RPT, according to CHNM.
RBNVPR Read TVPR to RPT, according to CHNM.
LDPR Load RPT to DPR/STK, according to CHNM.
RBPR Read DPR/STK to RPT, according to CHNM.
RBSPRH Read SPR[23:12] to RPT[11:0]
RBSPRL Read SPR[11:0] to RPT[11:0]
LDSPRH Load RPT[11:0] to SPR[23:12]
LDSPRL Load RPT[11:0] to SPR[11:0]
RBDA Read DAC[11:8] data to RPT2(RPT[11:8])
LDPC Move RPT to PC
RBPC Move PC to RPT
XMD0 Use {PAGE, RPT1[1:0], RPT0} as address to access indexed RAM data.
XMD1 Use {PAGE, RPT3[1:0], RPT2} as address to access indexed RAM data.
2.4.4 Head Voice Pointer (HVPR) & Tail Voice Pointer (TVPR)
Because NY6 is a 6-channel sound processor, 6 voice pointers each with 21-bit width are necessary for
playing speech or MIDI of each channel. When PLAY is executed, the system loads RPT to HVPR of
the channel that assigned by the CHNM register. When LDSEC is executed, the system loads RPT to
TVPR of the channel that assigned by the CHNM register. Therefore, users have to move the start
address of the speech or MIDI data to RPT first. Moreover, users can read HVPR/TVPR back by
RBVPR/RBNVPR instruction, because RBVPR/RBNVPR moves HVPR/TVPR of the channel that
assigned by the CHNM register to RPT. The HVPR/TVPR max width is 18 bits for NY6A/6B and 21 bits
for NY6C.
2.4.5 Data Pointer (DPR)
Eight data pointers each with 21-bit width are necessary for reading ROM data of each channel. When
LDPR is executed, the system loads RPT to DPR of the channel that assigned by the CHNM register.
The read back ROM data is placed on ROD2[1:0], ROD1, ACC. ACC is the 4 LSB of ROM data.
Besides, users can read DPR back by RBPR instruction, because RBPR moves DPR of the channel
that assigned by the CHNM register to RPT. The DPR max width is 18 bits for NY6A and 21 bits for
NY6B/NY6C. Unused DPR can be used as STK.

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2.5 Arithmetic Logic Unit (ALU)
The NY6 series provides a 4-bit arithmetic logic unit with a 4-bit accumulator to perform logic, unsigned
arithmetic, data transfer and conditional branch operation. We have two status bits (carry and zero) to
indicate the result of the operation. One or two operands will be the data sources of the ALU operation. The
operands can be ACC, RAM, register, or literal constant data.
2.5.1 ALU Instruction Summary
2.5.1.1 Logic Instruction
Instruction Function Flag Influenced
XORM m A ←M[m] ⊕A Z
ANDM m A ←M[m] & A Z
XORL L A ←L ⊕A Z
ANDL L A ←L & A Z
ORL L A ←L | A Z
RRC Right Rotate A with C C, Z
RLC Left Rotate A with C C, Z
RRA Right Rotate A
RLA Left Rotate A
M[m] : 4-bit RAM data at memory address m1, 0x00≤m ≤0x3F.
2.5.1.2 Arithmetic Instruction
Instruction Function Flag Influenced
ADDM m {C, A} ← A + M[m] + C C, Z
SUBM m {C, A} ← A – M[m] - (~B) C, Z
INCM m {C, M[m]} ← M[m] + 1 C, Z
DECM m {C, M[m]} ← M[m] - 1 C, Z
ADDL L A ←A + L + C C, Z
SUBL L {C, A} ←A - L - (~B) C, Z
INCA A ←A + 1 C, Z
DECA A ←A - 1 C, Z
M[m] : 4-bit RAM data at memory address m1, 0x00≤m ≤0x3F.
B : 1-bit borrow flag data, shared with carry flag, B=~C.

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2.5.1.3 Data Transfer Instruction
Instruction Function Flag Influenced
MVAM m M[m] ←A
MVMA m A ←M[m] Z
MVAT t1 T[t1] ←A
MVTA t1 A ←T[t1] Z
MVLA L A ←L
INTCB t2, b Clear T[t2][b]
INTSB t2, b Set T[t2][b]
SETC C ←1 C
CLRC C ←0 C
M[m] : 4-bit RAM data at memory address m1, 0x00≤m ≤0x3F.
T[t1] : 4-bit system register data at address t1, 0x0≤t1 ≤0x1F
T[t2] : 4-bit system register data at address t2, 0x0≤t2 ≤0x3
b : bit address, 0x0≤b ≤0x3
The width of the system register address ‘t1’ of MVAT and MVTA instruction is 5-bit (0x00~0x1F),
and address ‘t2’ of INTCB and INTSB instruction is 2-bit, to access system register 0x0~0x3 related
to interrupt execution. The width of ‘b’ is 2-bit for bit address of system register to execute clear or
set desired bit by INTCB and INTSB. The width of the RAM address `m’ of instructions associated
with memory operation is 6-bit. Only 0x00~0x07 registers are independent of SRAM page. Users
can use memory-related instructions to handle RAM of address 0x08~0x3F, but the RAM page is
still working.
2.5.1.4 Conditional Branch Instruction
Instruction Function Flag Influenced
SAGT L Skip when A > L
SALT L Skip when A < L
SANE L Skip when A != L
SCEZ Skip if C = 0
SZEZ Skip if Z = 0
SCNZ Skip if C != 0
SZNZ Skip if Z !=0
SBZ b Skip when A[b] = 0
SNP Skip when Play = 0, according to CHNM
SP Skip when Play = 1, according to CHNM.
SANP Skip when ALL 6 channels Play = 0
SNHP Skip when head Play = 0, according to CHNM.

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A conditional branch instruction compares two operands and skips next instruction if expression is
true. The skip operation is making an instruction NOP, not jump across it.
⊕: Exclusive OR bitwise logical operation
& : AND bitwise logical operation
| : OR bitwise logical operation
A : 4-bit Accumulator data
C : 1-bit carry flag data
Z : 1-bit zero flag data
L : 4-bit immediately literal data
A[b] : b-th bit of Accumulator, 0 ≤b ≤3.
2.5.2 ALU Related Status Flag
Symbol
Flag
Description
C Carry C=1 if a carry-out occurs after an addition operation.
C=0 if a borrow-in occurs after a subtraction operation.
Z Zero Z=1 if the result of an ALU operation is zero.
Besides CLRC and SETC commands directly assign the value of the carry flag, C is influenced by the
arithmetic result. C means carry and also means the complement of borrow. If the addition operation
result is larger than 0xF, C=1, and C=0 if the result is ≤15. If the subtraction operation smaller than 0,
C=0, and C=1 if the result ≧0.
2.6 Memory Organization
There are maximum 1728K words ROM, 6x56 nibbles of RAM and 32 nibbles of dedicated System
Register.
2.6.1 ROM
A large program/data/voice single ROM is provided, and its
structure is shown below. The reserved region contains system
information and can’t be utilized by users. After reset process is
completed, NY6 will start program execution from address
0x000.
Because program page size is 64K words defined by 16-bit
length address of ROM, allowable range of unconditional branch
instructions JMP and CALL are limited by program page size.
However, combining with 3-bit BANK register, the total program
size is 512K words. If users want to branch to program which is
located beyond current program bank, user can change the
BANK register first and then execute JMP or CALL instruction.
Address
ROM
$000000
Reset Vector
$00000F
$000010
Interrupt Vector
$00001E
$00001F
Reserved
$0003FF
$000400
Program & Data
Bank 0
$00FFFF
$010000
Program & Data

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2.6.2 RAM
There are 6 pages of RAM, each page of RAM contains 56 nibbles. It’s total 336 nibbles. The page of
RAM defined by MPG (PAGE0~5), and its initial is PAGE0. Memory Registers of RPT0~5 and ROD1~2
will occupy address space from 0x00 to 0x07. Moreover, this address
space of PAGE0~5 are mapped to the same dedicated registers. As
consequence, the address space of PAGE0~5 RAM which can be used by
programmer is 0x08~0x3F.
In addition to the immediate addressing mode, the indexed addressing
mode is also supported. The page and address of the indexed RAM
should be stored into {PAGE, RPT1[1:0], RPT0} or {PAGE, RPT3[1:0],
RPT2} first, and users can read from or write in the XMD0/XMD1 memory
register to realize the indexed RAM access.
2.7 I/O Ports
There are at most 24 I/O pins, designated as PAx through PFx, and x=0~3. All the I/O pins are bi-
directional. An individual and independent register bit can determine the direction of each I/O pin. These
register bits are PAIO (SFR $15), PBIO (SFR $17), PCIO (SFR $19), PDIO (SFR $1B), PEIO (SFR $1D)
and PFIO (SFR $1F).
Using as input pin of each I/O, there are 3 kinds of mask option. Users can select input with pull-high
resistor, input without pull-high resistor, or input with register-controlled pull-high resistor (high-to-low
wakeup only). If users want to enable/disable pull-high resistor by register during program execution, only
high-to-low level change on this pin can wakeup NY6. On the other hand, if the pull-high resistor is fixed by
option, either high-to-low or low-to-high level change on this pin can wakeup NY6. Users can refer Chapter
3.14 I/O Ports Register for details.
The pull-high resistor of all the I/O pins has two kinds of option: weak and strong. The weak one is about
1.2MΩ@3V for normal application and the strong one is about 100KΩ@3V usually for key matrix function.
When users decide this option, the same strength of pull-high resistor will be applied to all I/O pin.
Using as output pin of each I/O, there are 3 kinds of mask option. Users can select output with normal drive
current and normal sink current, normal drive current and large sink current, or normal drive current and
constant sink current.
Some I/O ports can also be optioned as specific application, i.e. External reset pin (PA3), an infrared (IR)
output pin (PA2), inputs of voltage comparator (PA0/PA1) or SPI associated control pins (PB0~3). A reset
pin can possess a pull-high resister or not according to the mask option, which is used to enable/disable
the pull-high resistor of I/O pin.
Address ROM
0x00
0x07
Memory
Registers
0x08
0x3F
General SRAM
56 nibbles
Page 0 ~ 5