NyQuest Innovation Labs NY6 Series Configuration guide

USER MANUEL
NY6 Series
Single-Chip 4-bit MCU with 8~24 I/O,
6
-ch Speech/MIDI Synthesizer
Version 1.3
Mar. 28, 2019
NYQUEST TECHNOLOGY CO. reserves the right to change this document without prior notice. Information provided by NYQUEST is believed to be accurate and reliable.
However, NYQUEST makes no warranty for any errors which may appear in this document. Contact NYQUEST to obtain the latest version of device specifications before
placing your orders. No responsibility is assumed by NYQUEST for any infringement of patent or other rights of third parties which may result from its use. In addition,
NYQUEST prod
ucts are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a m
alfunction or failure of the product
may reasonably be expected to result in significant injury to the user, without the express wr
itten approval of NYQUEST.

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Revision History
Version Date Description Modified Page
1.0 2016/08/31 Formal release. -
1.1 2016/11/25
1. Modify pad description.
2. Update DC characteristics.
3. Fix typos.
10
11
-
1.2 2017/05/17 1. Add description that a 0.1uF power capacitor nearby PB_VDD is
necessary if LDO regulator is enabled.
26
1.3 2019/03/28 Remove NY6C450A / NY6C520A / NY6C640A / NY6C720A. -

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Table of Contents
Chapter 1. Introduction ........................................................................................................... 6
1.1 General Description ...........................................................................................................6
1.2 Features.............................................................................................................................6
1.3 Product List ........................................................................................................................9
1.4 Block Diagram..................................................................................................................10
1.5 Pad Description................................................................................................................10
1.6 Electrical Characteristics ..................................................................................................11
1.6.1 Absolute Maximum Rating .................................................................................................. 11
1.6.2 DC Characteristics............................................................................................................... 11
Chapter 2. Hardware Architecture........................................................................................ 12
2.1 Overview ..........................................................................................................................12
2.1.1 Function Block Diagram ...................................................................................................... 12
2.1.2 Hardware Summary Table................................................................................................... 12
2.2 Clock Generator ...............................................................................................................13
2.3 System Reset...................................................................................................................14
2.3.1 Power-On Reset (POR)....................................................................................................... 14
2.3.2 Low Voltage Reset (LVR) .................................................................................................... 14
2.3.3 Watch-Dog Timer Reset (WDTR)........................................................................................ 14
2.3.4 I/O Port External Reset........................................................................................................ 14
2.4 Address Pointer................................................................................................................15
2.4.1 Program Counter (PC)......................................................................................................... 15
2.4.2 Stack (STK) ......................................................................................................................... 15
2.4.3 Multi-function Register Pointer (RPT).................................................................................. 15
2.4.4 Head Voice Pointer (HVPR) & Tail Voice Pointer (TVPR) .................................................. 16
2.4.5 Data Pointer (DPR).............................................................................................................. 16
2.5 Arithmetic Logic Unit (ALU) ..............................................................................................17
2.5.1 ALU Instruction Summary.................................................................................................... 17
2.5.2 ALU Related Status Flag ..................................................................................................... 19
2.6 Memory Organization .......................................................................................................19
2.6.1 ROM .................................................................................................................................... 19
2.6.2 RAM..................................................................................................................................... 20
2.7 I/O Ports...........................................................................................................................20
2.7.1 Pull-High Input Mode ........................................................................................................... 21
2.7.2 Floating Input Mode............................................................................................................. 21
2.7.3 Output Mode ........................................................................................................................ 22
2.7.4 I/O Pin Mask Option ............................................................................................................ 22
2.8 Infrared Transmitter..........................................................................................................23

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2.9 Interrupt Generator...........................................................................................................24
2.10 SPI Control Interface........................................................................................................25
2.11 Comparator ......................................................................................................................25
2.12 LDO Regulator .................................................................................................................26
2.13 Low Voltage Detector (LVD).............................................................................................26
2.14 Audio Synthesizer Structure .............................................................................................26
2.14.1 Speech Synthesis................................................................................................................ 27
2.14.2 MIDI Synthesis .................................................................................................................... 27
2.14.3 PH Value ............................................................................................................................. 28
2.14.4 Audio Output........................................................................................................................ 28
2.14.5 Envelope Control ................................................................................................................. 29
2.14.6 Volume Control.................................................................................................................... 29
Chapter 3. System Control.................................................................................................... 30
3.1 Introduction ......................................................................................................................30
3.1.1 System Register Address Map ............................................................................................ 30
3.1.2 Memory Register Address Map........................................................................................... 33
3.2 RPT..................................................................................................................................33
3.3 ROD.................................................................................................................................34
3.4 INTx / INTFx ($0 ~ $03)....................................................................................................34
3.5 BTF ($04).........................................................................................................................34
3.6 ONOFF ($05) ...................................................................................................................35
3.7 LVD ($0A) ........................................................................................................................35
3.8 TMCS ($0B) .....................................................................................................................35
3.9 RTMx ($0C/$0D) ..............................................................................................................35
3.10 XMDx ($0E/$0F) ..............................................................................................................36
3.11 SPIV ($10) .......................................................................................................................36
3.12 SPIC ($11) .......................................................................................................................36
3.13 SPIDx ($12/$13)...............................................................................................................37
3.14 I/O Ports Register ($14 ~ $1F) .........................................................................................37
3.15 Audio Control Register .....................................................................................................38
3.15.1 CHARC ................................................................................................................................ 38
3.15.2 DECMDx.............................................................................................................................. 38
3.15.3 VOL...................................................................................................................................... 39
3.16 Register Without Address Mapping ..................................................................................39
3.16.1 BANK ................................................................................................................................... 39
3.16.2 PAGE................................................................................................................................... 39
3.16.3 CHNM.................................................................................................................................. 40
3.16.4 ENV ..................................................................................................................................... 40
3.16.5 Head Play Flag .................................................................................................................... 40

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3.16.6 Play Flag.............................................................................................................................. 40
3.16.7 PH Value Setting ................................................................................................................. 41
3.16.8 Mixer Data ........................................................................................................................... 41
3.17 Audio Playback ................................................................................................................42
3.17.1 Voice Playback .................................................................................................................... 42
3.17.2 Melody Playback, Head-Only Mode .................................................................................... 45
3.17.3 Melody Playback, Tail-Only Mode....................................................................................... 48
3.17.4 Melody Playback, Head+Tail Mode..................................................................................... 51
3.17.5 Ramp-up/Ramp-down Procedure for DAC.......................................................................... 55
3.18 Power Saving Mode .........................................................................................................58
3.18.1 Slow Mode ........................................................................................................................... 58
3.18.2 Halt Mode ............................................................................................................................ 58
Chapter 4. Instruction Set ..................................................................................................... 59
4.1 Instruction Classified Table ..............................................................................................59
4.2 Instruction Descriptions....................................................................................................62
4.2.1 Arithmetic Instructions ......................................................................................................... 62
4.2.2 Conditional Instructions ....................................................................................................... 69
4.2.3 Audio Instructions ................................................................................................................ 71
4.2.4 Other Instructions ................................................................................................................ 77

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Chapter 1. Introduction
1.1 General Description
The NY6 series IC is a powerful 4-bit micro-controller based sound processor. There are 6 channels that
are configured as speech or MIDI, and all of these 6 channels or part of them can be played with speech or
MIDI simultaneously. By using the high fidelity 4-bit, 5-bit mixed ADPCM or PCM speech/ MIDI timbre
synthesis algorithm with up to 44.1KHz sample rate, NY6 produces high quality voices. As NY6 is specially
designed for MIDI synthesis application, it provides Attack-Decay-Sustain-Release method (ADSR) with
256-level envelope for Patch (instrument) synthesis. NY6 can precisely synthesize any tone frequency of
MIDI with +/- 0.5% accurate internal oscillation and automatic Tone-Calibration. Therefore NY6 melody
quality is very close to real instrument.
Moreover, NY6 is equipped with new Nyquest’s developed high-quality noise filtering algorithm of 250KHz
over-sampling, which can remove noise in order to improve speech and melody quality greatly. Up to 16-
level digital volume can be applied to final synthetic speech or melody that is tailored for applications of
volume adjustment. NY6 provides two kinds of audio outputs with fine resolution, one is 12-bit current-type
D/A converter (DAC) and the other is 12-bit Pulse-Width-Modulation (PWM). Therefore NY6 speech/
melody quality is the best choice among all solutions.
Hardware SPI (Mode0/Mode3) is supported for Channel-0 voice data automatically (auto mode, 24-bit
addressing capability) and user data (user mode) fetch from external SPI memory. Voltage comparator is
built-in for analog signal detecting applications. Software low voltage reset counting mechanism is provided
for low power management.
The RISC MCU architecture is very easy to program and control, various applications can be easily
implemented. There are 75 instructions, and most of them are executed in single cycle. Besides normal
operation mode, NY6 also provides Halt mode (or Sleep mode) and Slow mode to minimize power
dissipation.
1.2 Features
Wide operating voltage range: 2.0V to 5.5V.
4-bit RISC type micro-controller with 75 instructions.
NY6A have 10 items. 160K x 10-bit ROM is the maximum size.
NY6B have 11 items. 208K x 10-bit ROM is the maximum size.
NY6C have 12 items. 1728K x 10-bit ROM is the maximum size.
336x4-bit RAM, divided into 6 pages.
2MHz system clock for instruction execution.

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Slow mode to operate with low power consumption (+/-3.0% accuracy).
Halt mode to save power, less than 1uA@3V standby current.
Built-in RC oscillation is accurate with +/- 0.5% frequency deviation.
Low voltage reset (LVR=1.9V) and watch-dog reset (WDT) are supported to protect the system.
Special hardware for LVR occurrence counting by program to manage low battery system operation.
One interrupt entrance for multiple interrupt sources with an independent stack.
8-bit timer counter is applied to multiple clock source for various application.
Low Voltage Detector (LVD) is built-in for monitoring the status of power and protect malfunction if
unstable power is given. (NY6A doesn’t support LVD function)
LDO regulator is supported for the power supply of SPI flash. (NY6A doesn’t support LDO function)
Hardware SPI for external SPI devices data access. Dual power system operation supported (ex: NY6
@ 5V, SPI @ 3V).
Up to 24 flexible Bi-direction I/Os. Direction of each I/O is independently controlled by individual register
bit.
Each Bi-direction I/O pin can be optioned as different input and output function. For the input option,
users can select one of three kinds of option: input with pull-high resistor, input without pull-high
resistor, or input with register-controlled pull-high resistor (high-to-low wakeup only). For the output
option, users can select one of three kinds of option: output with normal drive/sink sink current, large
sink current or constant sink current. (Mask option)
Shared pins to provide IR carrier, comparator, SPI interface and external reset feature. (Mask option)
Shared Pin Function NY6A NY6B/NY6C
External reset (Reset) PA3/Reset PA3/Reset
IR carrier (IR) PA2/IR PA2/IR
Comparator
N/A PA1/VIN
N/A PA0/VIP
SPI
N/A PB0/CSb
N/A PB1/SCK
N/A PB2/SDO (MOSI)
N/A PB3/SDI (MISO)
(NY6A doesn’t support the Comparator and SPI function)
Selection of IR carrier frequency and data high/low IR output is supported.

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Built-in voltage comparator for analog signal detection applications. Comparator output flag can be
configured to generate interrupt and wakeup. Also, the flag can be used for timer counter clock source
for specific application. (NY6A doesn’t support Comparator function)
Maximum of 6 channels can be played simultaneously, and each channel can be arbitrarily assigned as
speech or MIDI channel.
New high fidelity 4-bit / 5-bit mixed ADPCM or 10-bit PCM speech synthesis algorithm and ADSR with
256-step envelope for MIDI synthesis.
Patented noise filtering algorithm with 250KHz over sampling to enhance signal-to-noise ratio and
provide excellent sound quality without ROM size increase.
16-level digital volume control for synthetic speech/melody.
Built-in hardware automatic Tone-Calibration of near-zero frequency deviation for precise tone
frequency.
High quality 12-bit D/A converter or 12-bit PWM driver. (NY6A doesn’t support DAC output)
PWM driver can be normal PWM or Ultra PWM.

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1.3 Product List
P/N Voice Duration
@6KHz (sec)
ROM Size
(bit)
Program ROM
Size (bit) I/O PWM DAC
NY6A003A 3.3 12K x 10 12K x 10 8 12-bit -
NY6A005A 5 16K x 10 16K x 10 8 12-bit -
NY6A008A 8.3 24K x 10 24K x 10 8 12-bit -
NY6A011A 11.7 32K x 10 32K x 10 8 12-bit -
NY6A018A 18.3 48K x 10 48K x 10 8 12-bit -
NY6A025A 25 64K x 10 64K x 10 8 12-bit -
NY6A035A 35 88K x 10 64K x 10 8 12-bit -
NY6A045A 45 112K x 10 64K x 10 8 12-bit -
NY6A055A 55 136K x 10 64K x 10 8 12-bit -
NY6A065A 65 160K x 10 64K x 10 8 12-bit -
NY6B005A 5 16K x 10 16K x 10 16 12-bit 12-bit
NY6B008A 8.3 24K x 10 24K x 10 16 12-bit 12-bit
NY6B011A 11.7 32K x 10 32K x 10 16 12-bit 12-bit
NY6B018A 18.3 48K x 10 48K x 10 16 12-bit 12-bit
NY6B025A 25 64K x 10 64K x 10 16 12-bit 12-bit
NY6B035A 35 88K x 10 64K x 10 16 12-bit 12-bit
NY6B045A 45 112K x 10 64K x 10 16 12-bit 12-bit
NY6B055A 55 136K x 10 64K x 10 16 12-bit 12-bit
NY6B065A 65 160K x 10 64K x 10 16 12-bit 12-bit
NY6B075A 75 184K x 10 64K x 10 16 12-bit 12-bit
NY6B085A 85 208K x 10 64K x 10 16 12-bit 12-bit
NY6C112A 111.7 272K x 10 64K x 10 24 12-bit 12-bit
NY6C132A 131.7 320K x 10 64K x 10 24 12-bit 12-bit
NY6C158A 158.3 384K x 10 64K x 10 24 12-bit 12-bit
NY6C185A 185 448K x 10 64K x 10 24 12-bit 12-bit
NY6C225A 225 544K x 10 64K x 10 24 12-bit 12-bit
NY6C265A 265 640K x 10 64K x 10 24 12-bit 12-bit
NY6C305A 305 736K x 10 64K x 10 24 12-bit 12-bit
NY6C345A 345 832K x 10 64K x 10 24 12-bit 12-bit

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1.4 Block Diagram
1.5 Pad Description
Pin ATTR. Description
VDD1~3 Power Positive power.
GND1~4 Power Negative power.
PA0/VIP I/O Bit 0 for Port A, or positive input of comparator.
PA1/VIN I/O Bit 1 for Port A, or negative input of comparator.
PA2/IR I/O Bit 2 for Port A, or IR carrier output.
PA3/Reset I/O Bit 3 for Port A, or external reset input.
PB_VDD Power Power for PBx and external component. (Not available for NY6A)
PB0/CSb I/O Bit 0 for Port B, or chip select pin for SPI interface.
PB1/SCK I/O Bit 1 for Port B, or serial clock pin for SPI interface.
PB2/SDO I/O Bit 2 for Port B, or serial data output pin (MOSI) for SPI interface.
PB3/SDI I/O Bit 3 for Port B, or serial data input pin (MISO) for SPI interface.
PC0~3 I/O Bit 0~3 for Port C.
PD0~3 I/O Bit 0~3 for Port D.
PE0~3 I/O Bit 0~3 for Port E.
PF0~3 I/O Bit 0~3 for Port F.
PWM1/DAC O PWM1 output or DAC output.
PWM2 O PWM2 output.
* NY6A: PA0~PB3. (There is no Comparator, LVD, LDO, SPI, and DAC function.)