Pleora Technologies iPORT PT1000-ST Installation instructions

PT1000-ST
Hardware Guide

...proven performance

These products are not intended for use in life support appliances, devices, or systems where malfunction of these products can reasonably
be expected to result in personal injury. Pleora Technologies Inc. (Pleora) customers using or selling these products for use in such applica-
tions do so at their own risk and agree to indemnify Pleora for any damages resulting from such improper use or sale.
Copyright © 2007 Pleora Technologies Inc. All information provided in this manual is believed to be accurate and reliable. No responsibility
is assumed by Pleora for its use. Pleora reserves the right to make changes to this information without notice. Redistribution of this manual
in whole or in part, by any means, is prohibited without obtaining prior permission from Pleora.
9/15/08

Contents
Product summary: iPORT............................................................................................. 3
Overview: Connector names........................................................................................ 7
Overview: Signal names ............................................................................................... 9
Connector summary: OEM: PT1000-ST .................................................................... 17
Connector: LAN: Copper ............................................................................................ 19
Connector: Power: Hirose HR10 6-pin ...................................................................... 23
Connector: Power: Molex 4 ........................................................................................ 25
Connector: Raw video: 2x 40-pin connector ............................................................ 27
Schematics: OEM: PT1000-ST ................................................................................... 31
Firmware: Generation 1 .............................................................................................. 33
Timing: Pixel bus......................................................................................................... 37
Timing: PLC ................................................................................................................. 41
Timing: Serial port: High-Bandwidth Serial: UART, USRT, and I2C ........................ 43
Timing: Serial port: Standard-Bandwidth: UART ..................................................... 47
Status LEDs: Overview ............................................................................................... 49
Status LEDs: Location: PT-series .............................................................................. 53
Specifications: Gen. 1 & 2 .......................................................................................... 55
Specifications: Programmable Logic Controller...................................................... 59
System design: Onboard memory............................................................................. 63
System design: Supported NICs................................................................................ 65
System design: Ethernet switches ............................................................................ 69
System design: PC requirements .............................................................................. 71
OEM Design: Camera Link pixel bus definitions...................................................... 73
OEM Design: Controlling EMI .................................................................................... 75
OEM design: Firmware selection............................................................................... 77
OEM Design: Serial communication.......................................................................... 79
OEM Design: Power supply........................................................................................ 83
OEM Design: Unused pins: ST-series IP Engines.................................................... 87
OEM Design: Prober board ........................................................................................ 89
OEM Design: Interface reference............................................................................... 93

3
Copyright © 2008 Pleora Technologies Inc.
Product summary: iPORT
Summary of IP Engine types
All IP Engines stream video data over Ethernet at speeds of up to 1 Gb/s. Packets are transported contin-
uously to the PC with the low, predictable end-to-end latency you require for your high-quality imaging
and video systems. Pleora’s innovative packet re-send technology ensures all image data arrives safely
to your PC. Data is never lost.
Summary of iPORT IP Engines
IP Engine Network
type
Form
factor
Video
type
Footprint
size
Power
cons. Best for
Supports
GigE
Vision
protocol
Supports
iPORT
protocol
NTx-Mini In-camera design
NTx-Pro In-system design
PT1000-VB In-camera design
PT1000-ST In-system design
FB1000-ST In-system design
PT1000-CL Machine vision
FB1000-CL Machine vision
PT2000-CLM Machine vision (2
Gb/s)
PT1000-ANL Security systems
PT1000-LV Older LVDS camera
systems
Legend
1 Gb; RJ-45 (copper) Raw video < 20 cm2<1.7 W
1 Gb, fiber-optic Camera Link
standard
< 30 cm2<2.5 W
OEM; printed circuit
board
LVDS camera <60 cm2(OEM)
<120 cm2(enclosed)
<5 W
Enclosed; aluminum case Analog (compos-
ite/S-video)
>120 cm2>5 W
RAW
RAW
RAW
RAW
RAW
CL
CL
CL
ANL
LV
RAW
CL
LV
ANL

4 Product summary: iPORT
Copyright © 2008 Pleora Technologies Inc.
Generation 3
Generation 3 IP Engines reduce power consumption, reduce overall size, and increase flexibility.
NTx-Pro
A bare board upon which most other Generation 3 IP Engines are based
(by adding a video-format card).
NTx is an abbreviation for network transceiver; Pro refers to its full feature
set and advanced capabilities.
NTx-Mini
A bare board similar to the Pro, but with a slightly reduced feature set to
minimize size and power consumption. The NTx-Mini offers the industry’s
smallest footprint, making it an ideal in-camera board for even the smallest
cameras.
NTx is an abbreviation for network transceiver; Mini refers to its ultra-small
size and ultra-low power consumption.
Generation 2
Generation 2 introduces fiber-optic Ethernet and adds more memory to the first-generation IP Engines.
The PCB grows slightly to accommodate the larger fiber-optic connectors. Otherwise, FB-series IP
Engines are technically similar to their first-generation equivalents. The fiber links are ideal for medical
and military systems that require very long-distance transmission, superior noise immunity, or better
data security.
FB-ST
A bare board similar to the Generation 1’s ST, but with a fiber-optic-based LAN
connector instead of copper-based.
FB-CL
Camera Link video over fiber-based Ethernet networks. FB is an
abbreviation for Fiber; CL is an acronym for Camera Link.
Generation 1
The ground-breaking Generation 1 IP Engines that started the video-over-Ethernet revolution – freeing
designers from the cost and cable-length constraints of traditional image grabbers. Rugged, well tested,
and widely deployed, Generation 1 IP Engines are used below the sea, in outer space, and everywhere in
between.
ST
A bare board upon which most other Generation 1 IP Engines are based. Other IP
Engines use a Video Format card to become the ANL, CL, LV, and so on.
ST is an abbreviation for streaming.
ANL
Standard 720 x 480 television video. Because the video
bandwidth is low, the IP Engine may carry two simultaneous
signals from up to 12 separate inputs. ANL-based IP Engines
are often used for security purposes, where many video sources
must be routed to a distant viewing station.
ANL is an abbreviation of analog.
CL
Camera Link video. The Camera Link standard is widely used
for machine vision applications, such as bottle inspection or
mail sorting.
CL is an acronym for Camera Link.

5
Copyright © 2008 Pleora Technologies Inc.
CLM
Camera Link Medium video. To allow for high-bandwidth cameras, the
Camera Link standard can split video into two streams of up to 1 Gbps
each. In most respects, CLM-based IP Engines are two separate CL-based
IP Engines that can operate independently, if needed.
CLM is an acronym for Camera Link Medium.
LV
LVDS video. LVDS is a precursor to the Camera Link standard,
which also communicates using low-voltage differential signal
wire pairs. (Because it describes the signal method rather than
the video standard, LVDS video is a bit of a misnomer.) LVDS
has largely been eclipsed by Camera Link.
LV is an acronym for low voltage.
VB
A bare board similar to the ST, but with a form factor designed to fit into the
back of a small camera. The VB is designed to receive raw video directly from
a camera’s PCB.
VB is an acronym for vertical board (the LAN connector rises vertically from
the PCB).

6 Product summary: iPORT
Copyright © 2008 Pleora Technologies Inc.

7
Copyright © 2008 Pleora Technologies Inc.
Overview: Connector names
To simplify identification, the IP Engine’s connectors are named. Though the names identify the
primary purpose of the connector, many connectors serve multiple purposes. IP Engines may not use all
connector types.
In this section:
Power connector .......................................................................................................... 7
Video connector ........................................................................................................... 7
Raw video connector ................................................................................................... 7
LAN connector ............................................................................................................ 8
PLC connector ............................................................................................................. 8
AdaptRBoard connector .............................................................................................. 8
Firmware selection connector ...................................................................................... 8
Serial connector ........................................................................................................... 8
Internal use connector .................................................................................................. 8
Power connector
The power connector supplies the IP Engine with power from an external low-voltage direct current
PSU. Many other connectors also carry power, so depending how you cable your camera and IP Engine,
you may not require a dedicated power connector.
Video connector
The video connector supplies the IP Engine with video from the camera. Video connectors use
established formats and connector types. Video connectors include:
• Camera Link
•LVDS
• Analog (BNC connector1)
• SDI/ASI (Serial Digital Interface/Asynchronous Serial Interface)
Depending on the format, some video connectors can carry camera control signals and serial communi-
cation.
Raw video connector
Some IP Engines replace the video connector with a raw video connector designed to plug directly into
a camera’s PCB. Raw video connectors use specialized pinouts that let you integrate your IP Engine and
camera into a small, single unit without the need for bulky video connectors.
Raw video connectors carry many signals that can include:
• Deserialized video data
• Power (to or from the IP Engine)
• Serial interface signals (that let the IP Engine control the camera)
• System level signals (camera clock, IP Engine clock, system reset controls, etc.)
• Firmware selection
1. OEM versions of the PT1000-ANL use a header connector. Thus, you can receive many standard analog video inputs
while maintaining a smaller footprint than would be possible with many BNC connectors.

8 Overview: Connector names
Copyright © 2008 Pleora Technologies Inc.
However, the greatest proportion of signals are dedicated to deserialized video data.
LAN connector
The LAN (local-area network) connector lets the IP Engine and host PC communicate over a local area
network. The host PC sends the IP Engine commands; the IP Engine replies with images and responses
to the commands. All network traffic is based on standard Ethernet protocols.
PLC connector
The PLC connector lets the IP Engine control external machinery. The IP Engine’s PLC (Programmable
Logic Controller) is versatile and programmable, so the potential uses depend on your imagination. In
general, the PLC connector carries signals that include:
• Inputs from and outputs to external machinery
• Power (to or from the IP Engine)
• Serial communication
Input and output types depend on the model of IP Engine, but can include:
•TTL
• Low-voltage differential pairs
• Optically isolated signals
To learn more about controlling external machinery with the IP Engine’s PLC, see the iPORT Program-
mable Logic Controller Reference Guide.
AdaptRBoard connector
AdaptRBoard connectors let you convert between the IP Engine’s internal signal levels (LVTTL) and
signal levels appropriate for communication with an external machine (TTL, optoisolators, LVDS, etc.).
Once the levels are converted (using a small AdaptRBoard, either from Pleora or of your own design),
the signals are routed to the PLC connector.
You can use the AdaptRBoard connector to add features and connections that meet your specific needs.
By including only the features you need (and none that you don’t), AdaptRBoard connectors give you
maximum flexibility so can you customize your design for minimum size, minimum power usage, and
minimum cost.
Firmware selection connector
The Firmware connector lets you choose if the IP Engine boots with its standard firmware or its backup
(typically emergency) firmware.
Serial connector
Serial connectors provide a dedicated serial communication between the IP Engine and another
component.
Internal use connector
Internal use connectors have no customer-usable pins.

9
Copyright © 2008 Pleora Technologies Inc.
Overview: Signal names
Numbered signal names are denoted with an arbitrary variable such as x. Thus, a signal listed as
VIDEO_DATAxwould be used as VIDEO_DATA0, VIDEO_DATA1, etc. The number of available
signals depends on the signal name and (sometimes) the IP Engine type.
In this section:
Signal names listed alphabetically............................................................................... 9
Signal type and direction ........................................................................................... 10
Internal signals............................................................................................................11
Power ......................................................................................................................... 12
IP Engine control ....................................................................................................... 12
Video control: Generic............................................................................................... 13
Video: Analog ............................................................................................................ 14
Video: LVDS.............................................................................................................. 14
PLC ............................................................................................................................ 14
Serial communication ................................................................................................ 15
Signal names listed alphabetically
ANALOG_VIDchannel_input................................................................................... 14
DGND........................................................................................................................ 12
DVCC ........................................................................................................................ 12
DVCC_SEL ............................................................................................................... 12
GND_ANALOG_VID............................................................................................... 14
GND_CHASSIS ........................................................................................................ 12
GND_FLTRD ............................................................................................................ 12
LVDS_IN-.................................................................................................................. 14
LVDS_IN+................................................................................................................. 14
OPTx_IN-................................................................................................................... 15
OPTx_IN+.................................................................................................................. 15
OPTx_OUT- ............................................................................................................... 15
OPTx_OUT+.............................................................................................................. 15
PWR........................................................................................................................... 12
RET............................................................................................................................ 12
Reserved......................................................................................................................11
RXD ........................................................................................................................... 16
SCK............................................................................................................................ 16
SCL ............................................................................................................................ 16
SER_HBx_CLK......................................................................................................... 15
SER_HBx_RX ........................................................................................................... 15
SER_HBx_TX ........................................................................................................... 15
SER_SBx_RX............................................................................................................ 15
SER_SBx_RX- .......................................................................................................... 15
SER_SBx_RX+ ......................................................................................................... 15
SER_SBx_RX_RS232............................................................................................... 16
SER_SBx_TX............................................................................................................ 15

10 Overview: Signal names
Copyright © 2008 Pleora Technologies Inc.
SER_SBx_TX-........................................................................................................... 15
SER_SBx_TX+.......................................................................................................... 15
SER_SBx_TX_RS232 ............................................................................................... 16
SYSTEM_CLK.......................................................................................................... 12
SYSTEM_CLK#........................................................................................................ 12
SYSTEM_FW_SEL................................................................................................... 13
SYSTEM_FW_SEL0................................................................................................. 13
SYSTEM_FW_SEL1................................................................................................. 13
SYSTEM_PWR_ON_RST#...................................................................................... 12
TTL_INx.................................................................................................................... 15
TTL_OUTx................................................................................................................ 15
TXD ........................................................................................................................... 16
VIDEO_CCx.............................................................................................................. 13
VIDEO_CCx- ............................................................................................................ 13
VIDEO_CCx+ ........................................................................................................... 13
VIDEO_CC_EXTRAx- ............................................................................................. 14
VIDEO_CC_EXTRAx+ ............................................................................................ 14
VIDEO_CLKx ........................................................................................................... 13
VIDEO_DATAx......................................................................................................... 13
VIDEO_DVAL .......................................................................................................... 13
VIDEO_FVAL ........................................................................................................... 13
VIDEO_LVAL ........................................................................................................... 13
VIDEO_SPARE......................................................................................................... 13
VIN_FLTRD .............................................................................................................. 12
Signal type and direction
Signal name, direction, level, and link
Signal name
Signal direction
(at IP Engine connec-
tors)
Signal level/standard
ANALOG_VIDchannel_input In CVBS/S-Video
DGND Power n/a
DVCC Power n/a
DVCC_SEL Power/In
GND_ANALOG_VID In n/a
GND_CHASSIS Power n/a
GND_FLTRD Power n/a
LVDS_IN- In LVDS
LVDS_IN+ In LVDS
OPTx_IN- In Opto
OPTx_IN+ In Opto
OPTx_OUT- Out Opto
OPTx_OUT+ Out Opto
PWR Power n/a
RET Power n/a
RXD In LVCMOS/LVTTL
SCK Out LVCMOS/LVTTL
SCL OutaLVCMOS/LVTTL
SER_HBx_CLK InaLVCMOS/LVTTL

11
Copyright © 2008 Pleora Technologies Inc.
Internal signals
IP Engines may use signals not intended for customer use.
Reserved
This signal is not intended for customer use. The signal may be an input, output, or set aside
for future use. Driving signals high, low, or using them as inputs may cause erratic behavior
and may permanently damage the IP Engine. Never connect to a reserved signal unless specif-
ically instructed to do so.
SER_HBx_RX In LVCMOS/LVTTL
SER_HBx_TX OutaLVCMOS/LVTTL
SER_SBx_RX In LVCMOS/LVTTL
SER_SBx_RX- In LV DS
SER_SBx_RX+ In LV DS
SER_SBx_RX_RS232 In RS-232
SER_SBx_TX Out LVCMOS/LVTTL
SER_SBx_TX- Out LVDS
SER_SBx_TX+ Out LVDS
SER_SBx_TX_RS232 Out RS-232
SYSTEM_CLK Out LVCMOS/LVTTL
SYSTEM_CLK# Out LVCMOS/LVTTL
SYSTEM_FW_SEL In LVCMOS/LVTTL
SYSTEM_FW_SEL0 In LVCMOS/LVTTL
SYSTEM_FW_SEL1 In LVCMOS/LVTTL
SYSTEM_PWR_ON_RST# In/Out LVCMOS/LVTTL
TTL_INx In LVCMOS/LVTTL
(5 V tolerant)
TTL_OUTx Out LVCMOS/LVTTL
TXD Out LVCMOS/LVTTL
VIDEO_CCx Out LVCMOS/LVTTL
VIDEO_CCx- Out LVDS
VIDEO_CCx+ Out LVDS
VIDEO_CC_EXTRAx- Out LVDS
VIDEO_CC_EXTRAx+ Out LVDS
VIDEO_CLKx In LVCMOS/LVTTL
VIDEO_DATAx In LVCMOS/LVTTL
VIDEO_DVAL In LVCMOS/LVTTL
VIDEO_FVAL In LVCMOS/LVTTL
VIDEO_LVAL In LVCMOS/LVTTL
VIDEO_SPARE In LVCMOS/LVTTL
VIN_FLTRD Power n/a
a. In/out for I2C.
Signal name, direction, level, and link
Signal name
Signal direction
(at IP Engine connec-
tors)
Signal level/standard

12 Overview: Signal names
Copyright © 2008 Pleora Technologies Inc.
Power
IP Engines can receive or output power from a variety of sources, as well as generate its own onboard
voltage sources. To keep from accidentally referring to a specific power rail, the generic terms VIN and
GND are never used.
PWR
RET
DC power directly from an external power supply. IP Engines can accept a wide voltage range.
VIN_FLTRD
GND_FLTRD
IP Engines filter the VIN and GND signals to minimize EMI. Voltage levels are unchanged.
These signals are available for connection to the camera (as inputs or outputs) and aren’t used
by the IP Engine’s circuitry.
DVCC
DGND
IP Engines further filter the VIN_FLTRD and GND_FLTRD signals and regulate voltage
levels using an onboard power supply. The DVCC and DGND signals power the IP Engine’s
internal circuitry. Due to fast level changes inherent to digital circuitry, these signals make
poor voltage references (or sources) for analog camera components.
GND_CHASSIS
Chassis ground. Chassis ground points typically include the IP Engine’s metal enclosure, and
the shell/case of external connectors. Depending on your EMI requirements, GND_CHASSIS
is typically connected to DGND, either with 0 Ohm resistors or ferrite beads.
DVCC_SEL
Selectable-level voltage. Some IP Engines use 2.5 V internally, but can support signalling with
cameras that use 3.3 V. If your camera uses 2.5 V, short DVCC_SEL with DVCC; if your
camera uses 3.3 V, supply DVCC_SEL with 3.3 V power (using either the camera’s power
supply or a standalone PSU).
For IP Engines that use DVCC_SEL, DVCC_SEL controls the input and output levels of the
following signals:
VIDEO_*
SER_SB0*
SER_SB1*
SER_HB0*
IP Engine control
The IP Engine includes onboard signals that let you control reset behavior, select firmware at boot-up
time, and access the IP Engine’s onboard clock. Voltage levels are with respect to DGND.
SYSTEM_CLK
SYSTEM_CLK#
The IP Engine’s onboard clock signal. To minimize EMI caused by the high-frequency clock,
some IP Engines use a differential pair – SYSTEM_CLK and its inverse, SYSTEM_CLK#.
SYSTEM_PWR_ON_RST#
IP Engine power-on-reset. The signal can be used as both an input or an output.
When power is first applied to the IP Engine, the IP Engine actively holds
SYSTEM_PWR_ON_RST# low. Once the voltages stabilize, the IP Engine releases the signal
and an onboard pull-up makes the signal high. You can use this case to suppress camera
activity if the camera boots faster than the IP Engine.
The SYSTEM_PWR_ON_RST# can also be used as an input to the IP Engine. By holding the
signal low, you can keep the IP Engine in its reset state (idle) until the camera is ready. You can
use this case if the IP Engine boots faster than the camera.

13
Copyright © 2008 Pleora Technologies Inc.
Finally, holding SYSTEM_PWR_ON_RST# low resets the IP Engine. When the IP Engine
resets, its state is lost, memory is flushed, connectivity with a host PC is lost, and IP addresses
are cleared.
To hold SYSTEM_PWR_ON_RST# low, use a 1 k-Ohm pull-down. For resets, use a
minimum signal duration of 1 ms.
SYSTEM_FW_SEL
Firmware select. When the IP Engine boots, the level determines whether the IP Engine loads
the main firmware or the backup firmware.
SYSTEM_FW_SEL0
SYSTEM_FW_SEL1
Firmware select. Similar to SYSTEM_FW_SEL, but with different values.
Video control: Generic
In general, the IP Engine’s onboard video signals are similar to deserialized Camera Link standard
signals.
VIDEO_CLKx
The camera’s clock signal. This signal is required by the IP Engine to properly synchronize
incoming video data (VIDEO_DATAy). You can also use the presence of the camera’s clock as
a rough test for the presence of a powered (and presumably working) camera. VIDEO_CLK0
is always available, VIDEO_CLK1 through VIDEO_CLK3 may not be.
VIDEO_DATAx
Image data. The content of the image data depends on the model of IP Engine and camera.
If the IP Engine uses a video-format card (such as ANL, CL, and LV series IP Engines), these
signals remain internal.
If the IP Engine is connected directly to a camera without a standardized interface, the data is
the raw output from the camera but is typically similar to uncompressed Camera Link Standard
image data.
Generation 3 IP Engines can carry packetized image data rather than bit-by-bit pixel data.
VIDEO_CCx
Camera control signals. These signals let you control your camera using the IP Engine’s PLC
(signals come from the PLC’s IO Block). The meaning of signals depends on the camera.
Within the IP Engine’s PLC, VIDEO_CC1 through VIDEO_CC4 are called Q4 through Q7.
VIDEO_CCx-
VIDEO_CCx+
Differential-pair equivalents of the VIDEO_CCxsignals.
VIDEO_FVAL
VIDEO_LVAL
VIDEO_DVAL
VIDEO_SPARE
Video-synchronization signals. The signals signify FVAL (frame valid), LVAL (line valid), and
DVAL (data valid), and SPARE (a spare signal provided for in the Camera Link Standard, but
with no defined usage). Not all cameras output all signals; for analog cameras, the signals are
generated by the video decoder chip.
As a general rule, the IP Engine’s image grabber can acquire images properly as long as it
receives the LVAL signal.
SYSTEM_FW_SEL0 settings
SYSTEM_FW_SEL0
level
SYSTEM_FW_SEL1 level
Low (0) High (1)
Low (0) Backup firmware load Reserved
High (1) Reserved Main firmware load

14 Overview: Signal names
Copyright © 2008 Pleora Technologies Inc.
The IP Engine’s PLC lets you create your own FVAL and LVAL signals and pass them on the
image grabber; see the IO Block in the iPORT Programmable Logic Controller Reference
Guide.
Video: Analog
ANALOG_VIDchannel_input
Analog video. ANL-series IP Engines can output one of 6 inputs per channel. They can have
up to two channels. ANL-series IP Engines can also output S-video by combining two inputs
(one Y input, one UV input). Signal levels are with respect to DGND.
GND_ANALOG_VID
The return path for ANALOG_VIDchannel_input. The IP Engine’s onboard wiring connects
GND_ANALOG_VID to DGND through a single-point connection (to keep noise on DGND
from affecting the quality of the analog video signal).
Video: LVDS
VIDEO_CC_EXTRAx-
VIDEO_CC_EXTRAx+
Some cameras require more controls than the VIDEO_CCysignals can offer. For these cases,
you can replace some VIDEO_DATAz signals with VIDEO_CC_EXTRAxsignals and control
them using the PLC’s Remote Control Block. Where the VIDEO_CCysignals are dynamic,
VIDEO_CC_EXTRAxsignals are intended for static (rarely changed) settings.
PLC
The PLC (Programmable Logic Controller) lets the IP Engine control external machinery. IP Engines
can use a variety of signal types, depending on the model of IP Engine.
The PLC’s IO Blocks convert signals between the LVTTL levels used by the IP Engine’s onboard
circuitry and signal levels by other equipment and machinery. Depending on the type of IP Engine, the
PLC’s IO Blocks can support LVDS, TTL, and optoisolators. The IO Block protects the IP Engine’s
delicate onboard circuitry from harm caused by EMI and ESD from the outside world.
PLC onboard signals
Ax
LVTTL-level inputs used by the IP Engine’s onboard circuitry. Typically, signals A0 through
A3 are inputs from the PLC connector (after the levels are converted by the IO Block).
Typically, signals A4 through A7 are inputs from the video cable.
Qx
LVTTL-level outputs used by the IP Engine’s onboard circuitry. Typically, signals Q0 through
Q3 are outputs to the PLC connector. Typically, Q4 through Q7 are outputs to the video cable.
Within the PLC, they are called Q4 through Q7 but they are equivalent to VIDEO_CC1
through VIDEO_CC4.
PLC external signals
LVDS_IN-
LVDS_IN+
Low-voltage differential signal. External machinery sends high or low signals alternating the
polarity of a low-voltage DC source. LVDS is tolerant of electrically noisy environments and
can transmit reliably at high rates. LVDS doesn’t always refer to these two signals – for
example, both Camera Link and LVDS cameras transmit video data over many LVDS pairs.

15
Copyright © 2008 Pleora Technologies Inc.
OPTx_IN-
OPTx_IN+
Optically isolated input. The two signals power an onboard opto-isolator (LED) at voltages of
0-5 VDC. Optical isolated signals are slower than TTL signals, but let you keep the IP Engine
electrically separate from the machinery sending the signal.
OPTx_OUT-
OPTx_OUT+
Optically isolated output. Similar to OPTy_IN+ and OPTy_IN-, but the IP Engine sends the
signal. The opto-isolator resides in the IP Engine; the machinery receives a 0-5 VDC signal.
TTL_INx
TTL input. External machinery sends a 0-3.3 VDC signal to the IP Engine. TTL is widely used
and relatively quick. The signal level is with respect to DGND.
TTL_OUTx
TTL output. Similar to TTL_INy, but the IP Engine sends the signal to external machinery.
Serial communication
IP Engines include a variety of serial communication interfaces that let you communicate with a camera
or other serial-capable device. The quantity and type of available serial interface depends on your model
of IP Engine but may include the following:
• UART (universal asynchronous receiver/transmitter)
• USRT (universal synchronous receiver/transmitter)
•I
2C (inter-integrated circuit)
SER_SBx_RX
SER_SBx_TX
Standard-Bandwidth Serial, port x. Standard-Bandwidth Serial sends one byte at a time over
Ethernet. The next byte isn’t sent until the previous byte is acknowledged. The SER_SBx_TX
is an output relative to the IP Engine; SER_SBx_RX is an input.
Standard-Bandwidth Serial is always UART.
SER_HBx_RX
SER_HBx_TX
SER_HBx_CLK
High-Bandwidth Serial, port x. High-Bandwidth Serial sends many bytes over Ethernet at
once, improving overall transmission times, particularly for large messages. The
SER_HBx_TX is an output relative to the IP Engine (Transmit); SER_HBx_RX is an input.
The SER_HBx_CLK is a clock, though some ports may not include this signal.
Depending on your IP Engine, High-Bandwidth Serial may support USRT, UART, and I2C.
SER_SBx_RX-
SER_SBx_RX+
SER_SBx_TX-
SER_SBx_TX+
The SER_SBx_RX and SER_SBx_TX signals, using differential signal pairs instead of
DGND.
High-Bandwidth Serial signal usage
Signal UART mode USRT mode I2C mode
SER_HBx_RX RXD
Receive data
RXD
Receive data
n/a
SER_HBx_TX TXD
Transmit data
TXD
Transmit data
SDA
Data
SER_HBx_CLK n/a SCK
Serial clock
SCL
Serial clock

16 Overview: Signal names
Copyright © 2008 Pleora Technologies Inc.
SER_SBx_RX_RS232
SER_SBx_TX_RS232
The SERx_RX and SERx_TX signals as RS232 level signals. Levels conform to the Electronic
Industries Alliance Recommended Standard 232 (EIA RS-232-C). Signal levels are with
respect to DGND.
RXD
TXD
SCK
SCL
Mode-specific names for High-Bandwidth Serial signals. See SER_HBx_RX.