Sony CDX-3250 User manual

– 1 –
Model Name Using Similar Mechanism CDX-4180
CD Drive Mechanism Type MG-363X-121
Optical Pick-up Name KSS-521A
SERVICE MANUAL
AEP Model
UK Model
CDX-3250
FM/MW/LW COMPACT DISC PLAYER
MICROFILM
SPECIFICATIONS

– 19 –
4-1. IC PIN DESCRIPTION
• IC801 µPD17705GC-526-3B9 (SYSTEM CONTROL)
Pin No. Pin Name I/O Pin Description
1 SIRCS I SIRCS input (A/D)
2 IN-SW I CD mechanism position detection
3 D-SW I CD mechanism position detection
4 SELF-SW I CD mechanism position detection
5 L-SW I LIMIT switch
6 LM-EJ O Loading motor control (Eject direction)
7 LM-LOD O Loading motor control (Loading direction)
8 ANT-ON O Power control for amplifier.
9 MONO O Force MONO output (Not used.)
10 SD I SD signal input
11 BAND-SW I Band plan setting of general area.
12 AREA1-SW I Destination select 1
13 AREA2-SW I Destination select 2
14, 15 RE1, 2 I Rotary encoder input 1, 2
16 SEEK O SEEK output
17 – 20 NC — Not used.
21 GND3 — Ground
22 – 24 KEYIN3 – 1 I A/D key input 3 – 1
25 ROT-IN I Rotary commander input
26 S-METER I FM and MW/LW common signal meter A/D conversion input.
27 TEST-SW I TEST mode select input
28 AM-IFC I MW/LW center frequency input
29 FM-IFC I FM center frequency input
30 VDD2 — Power supply (+5 V)
31 VCOH-FM I Local oscillation frequency input (FM)
32 VCOL-AM I Local oscillation frequency input (MW/LW)
33 GND2 — Ground
34 NC — Not used.
35 EO1-PDOUT O Error out output
36 TESTO — Fixed at “L”.
37 AM-ON(TU-ON) O MW/LW power output (MW/LW select)
38 FM-ON(FM/AM) O FM power output (FM select)
39 LCL/DX O LOCAL/DX select (“H” : LOCAL, “L” : DX)
40 BEEP O BEEP output
41 ACC-IN I Accessory input
42 SCOR I SUBQ data read request
43 MUTE O System mute output
44 AMP-MUTE O Power amplifier mute output
45 TEL-MUTE O Telephone mute output
46 NC — Not used.
47 VOL-CE O Electric volume chip select
48 VOL-CLK O Electric volume serial clock
49 VOL-DATA O Electric volume serial data
50 EMPHO O De-emphasis control output
51 PW-ON O System power control
52 MD-ON O Loading motor power
53 CD-ON O Servo drive power
54 ILL-ON O Illumination output
55, 56 MOD1, 2 O Bus boost control 1, 2
57 NC — Not used.
58 LCD-CE O LCD drive chip select output
SECTION 4
DIAGRAMS

– 20 –
Pin No. Pin Name I/O Pin Description
59 EZ-SEL I SHIFT + input
60 SENS I Information input from servo IC.
61 FOK I Focus OK input
62 LD-ON O Laser diode control
63 NC — Not used. (Connect to GND.)
64 ST/MONO I/O Used for both STEREO indicator display input and force MONO output. (FM)
65 LCD-CKO O LCD driver serial clock output
66 LCD-SO O LCD driver serial data output
67 C.ALARM O Caution alarm output
68 SQ-CKO O Q data read serial clock output
69 CD-RST O Servo IC/DAC reset output
70 SQ-SI I Q data input
71 CD-SO O Serial data output to servo IC.
72 CD-LAT O Data latch output to servo IC.
73 CD-CKO O Serial clock output to servo IC.
74 VREF — Not used.
75 GND1 — Ground
76 X-OUT — Crystal oscillator connection (4.5 MHz)
77 X-IN I Crystal oscillator connection (4.5 MHz)
78 BU-IN I Back-up detection
79 VDD1 — Power supply (+5 V)
80 RESET I RESET input

4-4. SCHEMATIC DIAGRAM — CD MECHANISM SECTION — • Refer to page 22 forWaveforms and Note. • Refer to page 37 for IC Block Diagrams.
CDX-3250
– 25 – – 26 –
(Page 33)
1
(1/2)
A

Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•U: B+ Line.
• Powervoltageisdc 14.4V and fedwith regulated dc power
supply from ACC and BATT cords.
•C: panel designation.
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
< > : CD PLAY
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production
tolerances.
4-6. SCHEMATIC DIAGRAM — DISPLAY SECTION —
CDX-3250
– 29 – – 30 –
B
(Page 36)
CNP552
D561-D578 SML-010YT-T86 (AMBER)
SML-010PT-T86 (GREEN)
GREEN AMBER

CDX-3250
Note:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ωand 1/4W or less unless otherwise
specified.
•¢: internal component.
•C: panel designation.
•U: B+ Line.
• Powervoltageisdc 14.4V and fedwith regulated dc power
supply from ACC and BATT cords.
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
( ) : MW
< > : CD PLAY
∗: Impossible to measure
• Voltages are taken withaVOM(Input impedance 10 MΩ).
Voltage variations may be noted due to normal production
tolerances.
• Signal path.
F: FM
f: MW
J: CD
4-8. SCHEMATIC DIAGRAM — MAIN SECTION (1/2) — • Refer to page 39 for IC Block Diagrams.
– 33 – – 34 –
A
(Page 26)
TU1
TUNER UNIT
1
2
4
3

CDX-3250
4-9. SCHEMATIC DIAGRAM — MAIN SECTION (2/2) — • Refer to page 34 for Note. • Refer to page 39 for IC Block Diagrams.
– 35 – – 36 –
ELECTRICAL
VOLUME
(Page 29)
B
1
POWER REM
(REMOTE IN)
FRONT L-CH –
REAR L-CH –
REAR L-CH +
REAR R-CH –
REAR R-CH +
FRONT L-CH +
FRONT R-CH –
FRONT R-CH +
AMP ANT/REM

– 37 –
• IC Block Diagrams
IC1 CXD2507AQ
IC3 BA6796FP
XLON
SPOD
SPOC
SPOB SPOA
CLKO
VDD
CNIN
SEIN
CLOK
XLAT
XLTO
DATO
52
53
5455
5657
58596061
62
63
64
51
SERVO AUTO
SEQUENCER
33
34
35
36
37
38
39
40
41
42
43
45
46
47
48
49
50
44
DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
VSS
WFCK
EMPH
DOUT
C4M
FSTT
XTSL
XTAO
XTAI
MNTO
20 21 22 23 24 25 26 27 29 30 31 3228
LRCK
PCMD
BCLK
GTOP
XUGF
XPCK
VDD
GFS
RFCK
C2PO
XROF
MNT3
MNT1
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
13
14
15
FOK
MON
MDP
MDS
LOCK
TEST
FILO
FILI
PCO
VSS
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
5
14
CPU
INTERFACE
SUB CODE
PROCESSOR
DIGITAL
CLV
EFM
DEMODULATOR
DIGITAL
PLL
ASYMMETRY
CORRECTOR
5D/A
INTERFACE
ERROR
CORRECTOR
3
6
3
16K
RAM
DIGITAL
OUT
CLOCK
GENERATOR
4
123 4 5678
910 11 12 13 14
OPOUT
CH4-IN
CH4
CTL1
CTL2
FWD
REV
TRAY
GND
CH3 –
CH5 –
COM
CH4 +
CH3 +
CH3-IN
CH3
VREF
CH2
CH2-IN
VCC
VCC
CH1 –
CH2 –
CH1-IN
OP IN –
CH1
CH1 +
OP IN +
CH2 +
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT
DOWN
15
161718
1920
21
22
23
2425
26
27
28
LOGIC
CTL1 CTL2 FWD REV
V/I

– 38 –
IC2 CXA1782BQ
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987
6
5
43
2
1
37
38
39
40
41
42
43
44
45
46
47
48
PHD 2 PHD 1
PHD
LD
RF O
RF I
CP CB CC1 CC2
FOK
SENS
C.OUT
XRST
DATA
XLT
CLK
VCC
ISET
SL O
SL M
SL P
TA O
TA M
FSET
TG2
TGU
SRCH
FE O
FLB
FGD
FDFCT
FE M
FEI
FEO
FE BIAS
F
E
EI
VEE
TED
LPFI
TEI
ATSC
TZC
TDFCT
VC
APC LEVEL S
FOK
MIRR
RF IV AMP1
RF IV AMP2
FE AMP
TTL
IIL
FZC COMP
DFCT
IIL
TTL
IIL DATA REGISTER INPUT SHIFT REGISTER
ADDRESS DECODER
OUTPUT DECODER
TTL
IIL
TOG1-3
BAL1-3
FS1-4 TG1-2 TM1-7 PS1-4
F IV AMP
E IV AMP
BAL1
BAL2
BAL 3
TE AMP
TZC COMP
DFCT
TM1
DFCT
FS4
ATSC
WINDOW COMP
TOG1 TOG2
TOG3
FCS PHASE
COMPENSATION
FS1
F SET
TG2
TM7
TM3
TM4
TM5
TM6
ISET
TRACKING
PHASE
COMPENSATION
HPF COMP LPF COMP
TG1
FS2
TM2
RF M

– 39 –
IC402 TDA7385
IC401 LC75374E
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
DECODER LATCH SHIFT
REGISTER
CONTROL
–
+
+
–
12 3 45 6 7 8 9 10
20
19
18
17
16
15
14
13
12
11
21
22
2324
25
2627282930313233
34
35
36
37
38
39
40
41
42
43
44
LSELO
L4
L3
L2
L1
VDD
R1
R2
R3
R4
RSELO
RVRIN
RCOM
RT1 RT2 RT3
RTOUT
RSIN
NC NC
RSB1 RSB2
RFIN
RFOUT
RROUT
VSS
CL
DI
CE
VREF
LROUT
LFOUT
LFIN
LSB2
LSB1 NC NC LSIN LTOUT LT3 LT2 LT1 LCOM LVRIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TAB
PW-GND
OUT2–
ST-BY
OUT2+
Vcc1
OUT1–
PW-GND1
OUT1+
SVR
IN1 IN2
S-GND
IN4 IN3
AC-GND
OUT3+
PW-GND3
OUT3–
Vcc2
OUT4+
MUTE
OUT4–
PW-GND4
DIAGNOSTICS OUT