Sundance Spas PXIe-700 User manual

PXIe-700 FPGA BOARD
User Guide
PROPRIETARY NOTICE: This document is the property of, and contains proprietary information of
Sundance DSP Inc. The document is delivered on condition that it is used exclusively to evaluate the
technical contents and pricing therein, it shall not be disclosed, duplicated or reproduced in whole or in part
without prior written consent of Sundance DSP Inc.

PXIe-700 User Guide Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
REVISION HISTORY
Revision
Comments
Originator
Date
1.0
Initial Release
Stephen Malchi
Aug 25th, 2016
1.1
Added VADJ details
Stephen Malchi
Sep 18th, 2016
1.2
Updated Flash features and errors
Stephen Malchi
Sep 30th, 2016
1.3
Updated pin out table
Stephen Malchi
Dec 2nd, 2016
1.4
Added DDR3 Memory details
Stephen Malchi
Jun 13th, 2017
1.5
Updated Rev 4.0 Changes
Stephen Malchi
Nov 10th, 2017
1.6
Updated clock pinout
Stephen Malchi
Dec 10th, 2017
1.7
Added J5 pinout
Stephen Malchi
Jan 21st, 2018

PXIe-700 User Guide Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
Table of Contents
1Introduction.............................................................................................................................. 1
1.1 Hardware features............................................................................................................ 1
2Board Description.................................................................................................................... 2
2.1 PXIe-700 Block Diagram and Pictures ............................................................................ 2
2.2 BPI FLASH Memory......................................................................................................... 3
2.3 Xilinx FPGA...................................................................................................................... 3
2.4 Memory............................................................................................................................. 3
2.5 GTX (High Speed Transceivers)...................................................................................... 3
2.6 HPC FMC......................................................................................................................... 4
2.7 LEDs................................................................................................................................. 4
2.8 Switches........................................................................................................................... 4
2.9 Clocks............................................................................................................................... 5
2.10 JTAG ................................................................................................................................ 5
2.11 PXIe.................................................................................................................................. 5
3Operation................................................................................................................................. 7
3.1 Carrier/Motherboard......................................................................................................... 7
3.2 Power Supplies ................................................................................................................ 7
3.3 VADJ voltage.................................................................................................................... 7
3.4 FPGA Configuration......................................................................................................... 9
3.4.1 Configuring FPGA through JTAG............................................................................. 9
3.4.2 Configuring FPGA from Flash .................................................................................. 9
4Application Development....................................................................................................... 11
Appendix....................................................................................................................................... 12
4.1 Pinout ............................................................................................................................. 12
4.1.1 PXIe......................................................................................................................... 12
4.1.2 HPC FMC................................................................................................................ 14
4.1.3 SFP+....................................................................................................................... 15
4.1.4 MMCX ..................................................................................................................... 15
4.1.5 LEDS....................................................................................................................... 16
4.1.6 Clocks...................................................................................................................... 16
4.1.7 DDR3 Interface....................................................................................................... 16
4.1.8 J5 Header................................................................................................................ 19

PXIe-700 User Guide Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
Table of Figures
Figure 1: PXIe-700 Block Diagram................................................................................................. 2
Figure 2: PXIe-700 frontal image.................................................................................................... 2
Figure 3 - JTAG Configuration........................................................................................................ 9
Table of Tables
Table 1 - High Speed Transceivers................................................................................................ 4
Table 2 –LEDs............................................................................................................................... 4
Table 3 - Switch (SW1)................................................................................................................... 5
Table 4 - VADJ Select and Enable pins......................................................................................... 7
Table 5 - PXIe-700 J2 Pinout ....................................................................................................... 13
Table 6 - PXIe-700 J2 pinout........................................................................................................ 13
Table 7 - HPC FMC Pinout........................................................................................................... 14
Table 8 - SFP+ Pinout .................................................................................................................. 15
Table 9 - MMCX Pinout ................................................................................................................ 15
Table 10 - LEDs Pinout................................................................................................................. 16
Table 11 - Clocks pinout............................................................................................................... 16
Table 12 - DDR3 Pinout................................................................................................................ 18
Table 13 - J5 Header Pinout......................................................................................................... 19

PXIe-700 User Guide Page 1 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
1 INTRODUCTION
PXIe-700 is a powerful FPGA board in the ruggedized PXIe form factor. The board is based on
the Xilinx Kintex-7 FPGA (XC7K410T-1FFG900C) with interface to 4 lanes of Gen2 PCIe, 2 GB
of DDR3 memory attached to 2 banks. It includes an HPC FMC site and SFP+ interface. It fully
complies with PXIe standard.
1.1 Hardware features
The hardware has the following features:
1. Kintex-7 FPGA (XC7K325T-1FFG900C or XC7K410T-1FFG900C) (optional faster
speed grades).
2. 4 lanes of PCIe Gen 2.0 using hard core or Gen 3.0 interface to host with custom IP
cores
3. PXI control signals for control and instrumentation support
4. SFP+ cage to provide 10Gb Ethernet using third party IP cores
5. HPC FMC connector with 10 high speed serial links, 2 differential clocks, 68 LVDS pairs,
and 8 single-ended signals
6. Two banks of DDR3 SDRAM memory, each 1GB deep and 32-bit wide
7. 128MB flash with multi-boot capability
8. Clock resources to support White Rabbit extreme-precision time protocol via SFP+ fiber

PXIe-700 User Guide Page 2 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
2 BOARD DESCRIPTION
2.1 PXIe-700 Block Diagram and Pictures
The following diagram shows the major blocks of PXIe-700:
Front
Panel
Xilinx Kintex-7 FPGA
XC7K325T-1FFG900C
or
XC7K410T-1FFG900C
JTAG
.
J3, Gen2 x4
4LEDs
PCIe clock
Rear End
Connectors
PCIe and
PXI Controls
.
J4, PXI 20 IO
Temp Monitor
10 GTX
68 diff pair IO
SFP+
HPC
FMC
FLASH
128MB
1GB
DDR3
8 GPIO
Reset In/Out
1GB
DDR3
/32
/32
4 MMCX
1 GTX
2 CLK input
4 MMCX
8 IO
config
1-GTX
With
White Rabbit
Clock Support
Figure 1: PXIe-700 Block Diagram
Figure 2: PXIe-700 frontal image

PXIe-700 User Guide Page 3 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
2.2 BPI FLASH Memory
The board has 128MB of BPI flash memory for storing FPGA bitstreams or software storage.
•Part number: PC28F00AP30TF (micron)
•Supply voltage: 2.5v
•Data rate: up to 33 MHz
When plugged into a PCIe host the board is enumerated within 100ms and the FPGA needs to
be configured within 100ms. The BPI flash provides fast FPGA configuration.
Multiple bitstreams can be stored in the BPI flash memory. The two most significant address bits
(A25, A24) of the flash are connected to DIP switch SW1 positions 1 and 2. 1 of the 4
bitstreams can be configured by setting the DIP switch.
2.3 Xilinx FPGA
The module is populated with a Xilinx Kintex-7 (FFG900 package) FPGA. The FPGA exists at
the heart of every I/O into and out of the module. Various interfaces are available to the FPGA
from which data is fed for processing, after which the processed data can be passed to the
outside world via any of the interfaces.
The following interfaces are available on the FPGA:
1. Four-lanes of PCIe interface Gen 2.0 using hardcore or Gen 3.0 if using PCIe softcore
for data transfer between the FPGA and the host.
2. High Pin Count (HPC) FMC for IO daughter cards.
3. DDR3 memory interface two banks.
4. The FPGA implements 12 Multi-Gigabit Transceivers. These are routed to FMC
connector (x10), SFP+ (x1) and one transceiver is connected to MMCX connectors.
2.4 Memory
Two banks of 32-bit DDR3 memory is provided on this board. A total of 2GB SDRAM is
attached to this interface for data storage.
The DDR3 memory used on this board is MT41J64M16JT-15E or AS4C64M16D312BCN
IP core to access the memory can be provided, which will provide read and write access to the
memory through host API.
2.5 GTX (High Speed Transceivers)
The FPGA has a total of 16 GTX’s. They are used to provide various interfaces on the board
which is shown in the table below
GTX's
Connector
Interface
4
PXIe (J2)
PCIe
10
FMC (J1)
User
1
SFP+
User

PXIe-700 User Guide Page 4 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
1
MMCX
User
Table 1 - High Speed Transceivers
2.6 HPC FMC
The board has an HPC FMC connector for IO daughter cards. A total of 144 IO’s are connected
to the FPGA out of which 136 IO’s can be used as 68 differential pairs and 8 IO’s are single
ended. There are two differential clocks pins connected to the FPGA.
As mentioned in section 2.5, 10 high speed serial links from the FPGA are available on this
connector.
Note: Please see appendix for pinout.
2.7 LEDs
There are 6 LEDs present on this board. Their function and power on default values is
described below:
LED
USAGE
Power
ON
Default
D1
FPGA/DONE
OFF
D2
FMC_PG_C2M
ON
D3
USER
OFF
D4
USER
OFF
D5
USER
OFF
D6
USER
OFF
D7
USER
OFF
Table 2 –LEDs
Note: D7 is optional and populated instead of D3 and D4.
Note: Rev 3.0 of the board comes up with D3 –D6 as ON when it should be OFF on power up.
2.8 Switches
There is one switch, SW1, on the component side of the board. It has the following settings:
SW1
Control
1
Flash_25
2
Flash_24
3
Factory use

PXIe-700 User Guide Page 5 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4
Factory use
5
Factory use
6
Not used
Table 3 - Switch (SW1)
Pins 1 and 2 are connected to Flash address pins and are used to select the configuration bit-
stream start address. A total of 4 bitstream can be stored and used for FPGA configuration. Pins
3 to 5 should always be set to OFF, ON, OFF as set by the factory. This board only uses Master
BPI x16 mode as it has 16-bit Fast parallel NOR Flash connected to the FPGA.
2.9 Clocks
This board requires several clocks for FPGA and high-speed serial transceivers. There are 6
clock sources available:
1) Clock provided by the PCIe Interface
2) 66.6 MHz FPGA_EMC clock for FPGA configuration from Flash
3) A Voltage-Controlled Crystal Oscillator providing a tunable 125MHz clock via
CDCM61004 for:
a. GTXs
b. FPGA Logic
4) A second VCXO with independent control voltage for use in White Rabbit extreme-
precision clock distribution protocol
5) MMCX connectors to provide external clock for user application
6) External Ref Clock for Transceivers via MMCX connectors
A low jitter clock generator from TI CDCM61004 is used to provide 3 clocks for FPGA logic and
GTX’s.
http://www.ti.com/lit/ds/symlink/cdcm61004.pdf
The output frequencies can range from 43.75 MHz to 683.264 MHz see table 4 of CDCM61004
data sheet. The output frequency divider can be chosen using control pins. On PXIe-700 a 25
MHz clock input clock is used and for the output the control pins are set using 0 ohm resistors
R187 –R193. The factory default settings for output clock is 125 MHz by populating R191,
R192.
For any other clock output please contact Sundance DSP Inc.
Note: Please see appendix for pinouts
2.10 JTAG
A 14-pin 2mm pitch pin header is provided for connection to a Xilinx USB Programmer (using
the standard ribbon cable). This allows access to the internals of the FPGA for configuration and
debugging.
2.11 PXIe
The board conforms to PXIe specifications and provides a hybrid connector for PCIe and control
signals.

PXIe-700 User Guide Page 6 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
J2: 973028 from ERNI backplane connector. This is used to provide PCIe signals in PXIe
format.
J3: 214443 from ERNI backplane connector. This is used to provide PXI control signals.
Note: Please see appendix for pinout.

PXIe-700 User Guide Page 7 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
3 OPERATION
This section describes how to install the hardware and initialize various devices on PXIe-700
before using the host software.
3.1 Carrier/Motherboard
PXIe-700 provides 4 PCIe lanes on J2 PXI hybrid connector, so to establish this host interface a
suitable PXI Express chassis conforming to the latest PXI Express specification which can
accept PXI Express boards must be used.
3.2 Power Supplies
The PXIe host provides 3.3 volt and 12 volt input power. These voltages are brought to the
board through the backplane connector. The module generates the following voltages:
1. 1.0v @16A (0.9v for -1C) : VCCINT, VCCBRAM
2. 1.8v @ 8A : VCCAUX, VCCAUX_IO, VCCO_1.8v
3. 1.3v @ 8A : VCC_LDO
4. 1.5v @ 8A : DDR3 Voltage
5. 3.3v @ 8A : VCCO_3.3v
6. 2.5v @ 8A : VCCO_2.5v
7. VADJ @ 8A : VADJ (Selectable 1.8, 2.5, 3.3V)
8. 1.0v @ 3A : MGTAVCC
9. 1.2v @ 3A : MGTAVTT
10. 1.8v @ 3A : MGTVCCAUX
11. 0.75v @ 3A : Vref, VTT
The power sequence is provided on page 6 in the Xilinx Kintex-7 datasheet.
3.3 VADJ voltage
The module can support different VADJ volatges 1.8v, 2.5v and 3.3v. The select pins can be set
to generate the desired VADJ voltage.
SIGNAL
FPGA PIN
SEL1
SEL0
VADJ
VADJ_SEL0
M19
0
0
1.8v
VADJ_SEL1
P19
0
1
2.5v
1
0
N/A
1
1
3.3v
Rev 4.0 PCB only
VADJ_EN
Description
SIGNAL
FPGA
PIN
0
Disable
VADJ_EN
P23
1
Enable
Table 4 - VADJ Select and Enable pins

PXIe-700 User Guide Page 8 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
Note:
Rev 3.0 PCB
On power up VADJ voltage comes up as 1.8v. If a FMC module with VADJ 2.5v or 3.3v is
populated then the module will receive 1.8v till the FPGA is configured with the right VADJ_SEL
pins as described in the table above.
Rev 4.0 PCB
VADJ voltage is implemented as per FMC standard. On power up VADJ is 0v. After the FMC
EEPROM is read the user can enable VADJ with right voltage using VADJ_SEL pins and
VADJ_EN pin as described in the table above.

PXIe-700 User Guide Page 9 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
3.4 FPGA Configuration
The on-board FPGA can be configured in three different ways
1. JTAG
2. FLASH
3.4.1 Configuring FPGA through JTAG
Connect J4 to a Xilinx JTAG emulator connected to a PC with Vivado 2016.2 . Start Vivado and
Open hardware manager and connect to the local target. The FPGA device is detected by the
software. Select the device and program it with the desired bit stream.
Figure 3 - JTAG Configuration
3.4.2 Configuring FPGA from Flash
The FLASH can ONLY be programmed via JTAG connection and not through the host interface.
In order to program the flash, connect to the FPGA via JTAG. Right click on FPGA -> Add
configuration memory device as shown above. Select PC28F00AP30T x16 BPI as your flash
device and use .mcs and .prm files to burn the flash.

PXIe-700 User Guide Page 10 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
Once the flash has been programmed set switch SW1 to Master BPI mode.
Note: Set pins 3 to 5 on switch SW1 to OFF, ON, OFF for the FPGA to boot from flash.
Multiple bitstreams can be stored in the flash by setting the Warm Boot Start Address
(WBSTAR) register available in 7-series FPGA. More information is available in the
reconfiguration and multiboot section in 7 series FPGAs configuration user guide UG470
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
Note: The multi-boot feature has not been tested as of now. Please refer to the above link.

PXIe-700 User Guide Page 11 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4 APPLICATION DEVELOPMENT
The board comes with a demonstration, confidence-test package called SCom-AXI-BSP.zip.
The BSP (Board Support Package) will include drivers for Windows (Linux OS is optional), Host
API and application program. The host API is based on Sundance Scom (Sundance
Communication) library along with a default FPGA bitstream which will provide users a multi-
channel DMA interface to talk to the user application. The default package is not suitable for
developing user application and is simply for confidence building. If a complete driver and host
API with the relevant IP cores and libraries is required, please contact SDSP sales team for
pricing and delivery.
The document section has all the instructions for installation, setup and testing the hardware.
Please read the documents carefully for proper functionality. For support please contact
Sundance DSP on the support forum https://www.sundancedsp.com/forum/ or write to
[email protected]

PXIe-700 User Guide Page 12 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
APPENDIX
4.1 Pinout
4.1.1 PXIe
This board conforms to PXIe specification.
J2: 973028 from ERNI backplane connector. This is used to provide PCIe signals from PXIe
host to the board.
Note: The control signals are connected to 1.8v Bank (LVCMOS_18). All the differential signals
are LVDS signals.
PIN
A
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0
B
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0
C
1
PXIe_CLK+
AD18
AD18
PXIe_CLK-
AE18
AE18
GND
2
PRSNT#
PWREN
GND
3
SMBDAT
M29
M29
SMBCLK
M28
M28
GND
4
MPWRGD
PERST#
AH19
AH19
GND
5
1PETP0
Y2
Y2
1PETN0
Y1
Y1
GND
6
1PETP2
U4
U4
1PETN2
U3
U3
GND
7
1PETP3
T2
T2
1PETN3
T1
T1
GND
8
1PETP5
1PETN5
GND
9
1PETP6
1PETN6
GND
10
RSV
RSV
GND
PIN
D
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0
E
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0
F
1
PXIe_SYNC+
AF17
AD17
PXIe_SYNC-
AG17
AD16
GND
2
PXIe_DSTARB+
AH17
AH17
PXIe_DSTARB-
AJ17
AJ17
GND
3
RSV
RSV
GND
4
RSV
RSV
GND
5
1PERP0
AA4
AA4
1PERN0
AA3
AA3
GND
6
1PERP2
W4
W4
1PERN2
W3
W3
GND
7
1PERP3
V6
V6
1PERN3
V5
V5
GND
8
1PERP5
1PERN5
GND
9
1PERP6
1PERN6
GND
10
RSV
RSV
GND

PXIe-700 User Guide Page 13 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
PIN
G
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0
H
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0
I
1
PXIe_DSTARC+
AF15
AF15
PXIe_DSTARC-
AG14
AG14
GND
2
PXIe_DSTARA+
AJ19
AF17
PXIe_DSTARA-
AK19
AG17
GND
3
RSV
RSV
GND
4
1REFCLK+
U8
U8
1REFCLK-
U7
U7
GND
5
1PETP1
V2
V2
1PETN1
V1
V1
GND
6
1PERP1
Y6
Y6
1PERN1
Y5
Y5
GND
7
1PETP4
1PETN4
GND
8
1PERP4
1PERN4
GND
9
1PETP7
1PETN7
GND
10
1PERP7
1PERN7
GND
Table 5 - PXIe-700 J2 Pinout
J3: 214443 from ERNI backplane connector. This is used to provide PXI control signals.
Note: These signals are connected to 1.8v Bank
PIN
A
FPGA_PIN
B
FPGA_PIN
C
FPGA_PIN
1
GA4
AB17
GA3
AC19
GA2
AB19
2
5v_AUX
GND
SYS_EN
3
12v
12V
GND
4
GND
GND
3.3V
5
PXI_TRIG3
AB15
PXI_TRIG4
AC16
PXI_TRIG5
AC15
6
PXI_TRIG2
AA15
GND
ATNLED
Y16
7
PXI_TRIG1
AE15
PXI_TRIG0
AC17
ATNSW#
AA16
8
RSV
GND
RSV
PIN
D
FPGA_PIN
E
FPGA_PIN
F
FPGA_PIN
1
GA1
AB18
GA0
AA18
2
WAKE
ALERT#
AG19
3
GND
GND
GND
4
3.3V
3.3V
GND
5
GND
PXI_TRIG6
AC14
GND
6
PXI_STAR
AA17
PXI_CLK10
AF18
GND
7
GND
PXI_TRIG7
AD14
8
PXI_LBL6
AK18
PXI_LBR6
AJ18
Table 6 - PXIe-700 J2 pinout

PXIe-700 User Guide Page 14 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4.1.2 HPC FMC
Table 7 - HPC FMC Pinout

PXIe-700 User Guide Page 15 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4.1.3 SFP+
Note: The control signals are connected to 1.8v bank
PXIe 700 SFP+ Pinout
S.No
SFP+ Pin
FPGA Pin
1
SFP_TX+
P2
2
SFP_TX-
P1
3
SFP_RX+
T6
4
SFP_RX-
T5
5
SFP_TX_FAULT
AH16
6
SFP_TX_DISABLE
AJ16
7
SFP_MOD_DETECT
AE16
8
SFP_RS0
Y18
9
SFP_RS1
Y19
10
SFP_LOS
AF16
Table 8 - SFP+ Pinout
4.1.4 MMCX
PXIe 700 MMCX Pinout
Connector
Pin_name
FPGA
Pin
P1
MGTX_REFCLK+
N8
P2
MGTX_REFCLK-
N7
P3
FPGA_REFCLK+
U28
P4
FPGA_REFCLK-
U27
P5
MGTX_AUX_TX+
N4
P6
MGTX_AUX_TX-
N3
P7
MGTX_AUX_RX+
R4
P8
MGTX_AUX_RX-
R3
Table 9 - MMCX Pinout

PXIe-700 User Guide Page 16 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4.1.5 LEDS
Note: Pins are connected to 2.5v bank
PXIe 700 LED Pinout
S.No
LED
FPGA Pin
1
D2
H29
2
D3
L26
3
D4
L27
4
D5
M27
5
D6
N27
Table 10 - LEDs Pinout
4.1.6 Clocks
Note: Pins are connected to 2.5v bank
PXIe 700 Clock Pinout
S.No
Pin_name
FPGA Pin
Clock Frequency
1
FPGA_EMCCLK
R24
66 MHz
2
FPGA_VCXO_CLK
L25
20 MHz
3
MGT_SYS_CLK0+
C8
125 MHz
4
MGT_SYS_CLK0-
C7
125 MHz
5
MGT_SYS_CLK1+
L8
125 MHz
6
MGT_SYS_CLK1-
L7
125 MHz
7
FPGA_SYS_CLK+
K28
125 MHz
8
FPGA_SYS_CLK-
K29
125 MHz
Table 11 - Clocks pinout
4.1.7 DDR3 Interface
PXIe_700 DDR3 Pinout Bank 1
Signal
FPGA Pin
Signal
FPGA Pin
A0
AD8
CLK+
AB9
A1
AC10
CLK-
AC9
A2
AB10
DQ0
AD3
A3
AB13
DQ1
AC2
A4
AA13
DQ2
AC1
A5
AA10
DQ3
AC5
A6
AA1
DQ4
AC4
A7
Y10
DQ5
AD6
A8
Y11
DQ6
AE6