Sundance Spas PXIe-700 User manual

PXIe-700 FPGA BOARD
User Guide
PROPRIETARY NOTICE: This document is the property of, and contains proprietary information of
Sundance DSP Inc. The document is delivered on condition that it is used exclusively to evaluate the
technical contents and pricing therein, it shall not be disclosed, duplicated or reproduced in whole or in part
without prior written consent of Sundance DSP Inc.

PXIe-700 User Guide Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
REVISION HISTORY
Revision
Comments
Originator
Date
1.0
Initial Release
Stephen Malchi
Aug 25th, 2016
1.1
Added VADJ details
Stephen Malchi
Sep 18th, 2016
1.2
Updated Flash features and errors
Stephen Malchi
Sep 30th, 2016
1.3
Updated pin out table
Stephen Malchi
Dec 2nd, 2016
1.4
Added DDR3 Memory details
Stephen Malchi
Jun 13th, 2017
1.5
Updated Rev 4.0 Changes
Stephen Malchi
Nov 10th, 2017
1.6
Updated clock pinout
Stephen Malchi
Dec 10th, 2017
1.7
Added J5 pinout
Stephen Malchi
Jan 21st, 2018

PXIe-700 User Guide Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
Table of Contents
1Introduction.............................................................................................................................. 1
1.1 Hardware features............................................................................................................ 1
2Board Description.................................................................................................................... 2
2.1 PXIe-700 Block Diagram and Pictures ............................................................................ 2
2.2 BPI FLASH Memory......................................................................................................... 3
2.3 Xilinx FPGA...................................................................................................................... 3
2.4 Memory............................................................................................................................. 3
2.5 GTX (High Speed Transceivers)...................................................................................... 3
2.6 HPC FMC......................................................................................................................... 4
2.7 LEDs................................................................................................................................. 4
2.8 Switches........................................................................................................................... 4
2.9 Clocks............................................................................................................................... 5
2.10 JTAG ................................................................................................................................ 5
2.11 PXIe.................................................................................................................................. 5
3Operation................................................................................................................................. 7
3.1 Carrier/Motherboard......................................................................................................... 7
3.2 Power Supplies ................................................................................................................ 7
3.3 VADJ voltage.................................................................................................................... 7
3.4 FPGA Configuration......................................................................................................... 9
3.4.1 Configuring FPGA through JTAG............................................................................. 9
3.4.2 Configuring FPGA from Flash .................................................................................. 9
4Application Development....................................................................................................... 11
Appendix....................................................................................................................................... 12
4.1 Pinout ............................................................................................................................. 12
4.1.1 PXIe......................................................................................................................... 12
4.1.2 HPC FMC................................................................................................................ 14
4.1.3 SFP+....................................................................................................................... 15
4.1.4 MMCX ..................................................................................................................... 15
4.1.5 LEDS....................................................................................................................... 16
4.1.6 Clocks...................................................................................................................... 16
4.1.7 DDR3 Interface....................................................................................................... 16
4.1.8 J5 Header................................................................................................................ 19

PXIe-700 User Guide Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
Table of Figures
Figure 1: PXIe-700 Block Diagram................................................................................................. 2
Figure 2: PXIe-700 frontal image.................................................................................................... 2
Figure 3 - JTAG Configuration........................................................................................................ 9
Table of Tables
Table 1 - High Speed Transceivers................................................................................................ 4
Table 2 –LEDs............................................................................................................................... 4
Table 3 - Switch (SW1)................................................................................................................... 5
Table 4 - VADJ Select and Enable pins......................................................................................... 7
Table 5 - PXIe-700 J2 Pinout ....................................................................................................... 13
Table 6 - PXIe-700 J2 pinout........................................................................................................ 13
Table 7 - HPC FMC Pinout........................................................................................................... 14
Table 8 - SFP+ Pinout .................................................................................................................. 15
Table 9 - MMCX Pinout ................................................................................................................ 15
Table 10 - LEDs Pinout................................................................................................................. 16
Table 11 - Clocks pinout............................................................................................................... 16
Table 12 - DDR3 Pinout................................................................................................................ 18
Table 13 - J5 Header Pinout......................................................................................................... 19

PXIe-700 User Guide Page 1 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
1 INTRODUCTION
PXIe-700 is a powerful FPGA board in the ruggedized PXIe form factor. The board is based on
the Xilinx Kintex-7 FPGA (XC7K410T-1FFG900C) with interface to 4 lanes of Gen2 PCIe, 2 GB
of DDR3 memory attached to 2 banks. It includes an HPC FMC site and SFP+ interface. It fully
complies with PXIe standard.
1.1 Hardware features
The hardware has the following features:
1. Kintex-7 FPGA (XC7K325T-1FFG900C or XC7K410T-1FFG900C) (optional faster
speed grades).
2. 4 lanes of PCIe Gen 2.0 using hard core or Gen 3.0 interface to host with custom IP
cores
3. PXI control signals for control and instrumentation support
4. SFP+ cage to provide 10Gb Ethernet using third party IP cores
5. HPC FMC connector with 10 high speed serial links, 2 differential clocks, 68 LVDS pairs,
and 8 single-ended signals
6. Two banks of DDR3 SDRAM memory, each 1GB deep and 32-bit wide
7. 128MB flash with multi-boot capability
8. Clock resources to support White Rabbit extreme-precision time protocol via SFP+ fiber

PXIe-700 User Guide Page 2 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
2 BOARD DESCRIPTION
2.1 PXIe-700 Block Diagram and Pictures
The following diagram shows the major blocks of PXIe-700:
Front
Panel
Xilinx Kintex-7 FPGA
XC7K325T-1FFG900C
or
XC7K410T-1FFG900C
JTAG
.
J3, Gen2 x4
4LEDs
PCIe clock
Rear End
Connectors
PCIe and
PXI Controls
.
J4, PXI 20 IO
Temp Monitor
10 GTX
68 diff pair IO
SFP+
HPC
FMC
FLASH
128MB
1GB
DDR3
8 GPIO
Reset In/Out
1GB
DDR3
/32
/32
4 MMCX
1 GTX
2 CLK input
4 MMCX
8 IO
config
1-GTX
With
White Rabbit
Clock Support
Figure 1: PXIe-700 Block Diagram
Figure 2: PXIe-700 frontal image

PXIe-700 User Guide Page 3 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
2.2 BPI FLASH Memory
The board has 128MB of BPI flash memory for storing FPGA bitstreams or software storage.
•Part number: PC28F00AP30TF (micron)
•Supply voltage: 2.5v
•Data rate: up to 33 MHz
When plugged into a PCIe host the board is enumerated within 100ms and the FPGA needs to
be configured within 100ms. The BPI flash provides fast FPGA configuration.
Multiple bitstreams can be stored in the BPI flash memory. The two most significant address bits
(A25, A24) of the flash are connected to DIP switch SW1 positions 1 and 2. 1 of the 4
bitstreams can be configured by setting the DIP switch.
2.3 Xilinx FPGA
The module is populated with a Xilinx Kintex-7 (FFG900 package) FPGA. The FPGA exists at
the heart of every I/O into and out of the module. Various interfaces are available to the FPGA
from which data is fed for processing, after which the processed data can be passed to the
outside world via any of the interfaces.
The following interfaces are available on the FPGA:
1. Four-lanes of PCIe interface Gen 2.0 using hardcore or Gen 3.0 if using PCIe softcore
for data transfer between the FPGA and the host.
2. High Pin Count (HPC) FMC for IO daughter cards.
3. DDR3 memory interface two banks.
4. The FPGA implements 12 Multi-Gigabit Transceivers. These are routed to FMC
connector (x10), SFP+ (x1) and one transceiver is connected to MMCX connectors.
2.4 Memory
Two banks of 32-bit DDR3 memory is provided on this board. A total of 2GB SDRAM is
attached to this interface for data storage.
The DDR3 memory used on this board is MT41J64M16JT-15E or AS4C64M16D312BCN
IP core to access the memory can be provided, which will provide read and write access to the
memory through host API.
2.5 GTX (High Speed Transceivers)
The FPGA has a total of 16 GTX’s. They are used to provide various interfaces on the board
which is shown in the table below
GTX's
Connector
Interface
4
PXIe (J2)
PCIe
10
FMC (J1)
User
1
SFP+
User

PXIe-700 User Guide Page 4 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
1
MMCX
User
Table 1 - High Speed Transceivers
2.6 HPC FMC
The board has an HPC FMC connector for IO daughter cards. A total of 144 IO’s are connected
to the FPGA out of which 136 IO’s can be used as 68 differential pairs and 8 IO’s are single
ended. There are two differential clocks pins connected to the FPGA.
As mentioned in section 2.5, 10 high speed serial links from the FPGA are available on this
connector.
Note: Please see appendix for pinout.
2.7 LEDs
There are 6 LEDs present on this board. Their function and power on default values is
described below:
LED
USAGE
Power
ON
Default
D1
FPGA/DONE
OFF
D2
FMC_PG_C2M
ON
D3
USER
OFF
D4
USER
OFF
D5
USER
OFF
D6
USER
OFF
D7
USER
OFF
Table 2 –LEDs
Note: D7 is optional and populated instead of D3 and D4.
Note: Rev 3.0 of the board comes up with D3 –D6 as ON when it should be OFF on power up.
2.8 Switches
There is one switch, SW1, on the component side of the board. It has the following settings:
SW1
Control
1
Flash_25
2
Flash_24
3
Factory use

PXIe-700 User Guide Page 5 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
4
Factory use
5
Factory use
6
Not used
Table 3 - Switch (SW1)
Pins 1 and 2 are connected to Flash address pins and are used to select the configuration bit-
stream start address. A total of 4 bitstream can be stored and used for FPGA configuration. Pins
3 to 5 should always be set to OFF, ON, OFF as set by the factory. This board only uses Master
BPI x16 mode as it has 16-bit Fast parallel NOR Flash connected to the FPGA.
2.9 Clocks
This board requires several clocks for FPGA and high-speed serial transceivers. There are 6
clock sources available:
1) Clock provided by the PCIe Interface
2) 66.6 MHz FPGA_EMC clock for FPGA configuration from Flash
3) A Voltage-Controlled Crystal Oscillator providing a tunable 125MHz clock via
CDCM61004 for:
a. GTXs
b. FPGA Logic
4) A second VCXO with independent control voltage for use in White Rabbit extreme-
precision clock distribution protocol
5) MMCX connectors to provide external clock for user application
6) External Ref Clock for Transceivers via MMCX connectors
A low jitter clock generator from TI CDCM61004 is used to provide 3 clocks for FPGA logic and
GTX’s.
http://www.ti.com/lit/ds/symlink/cdcm61004.pdf
The output frequencies can range from 43.75 MHz to 683.264 MHz see table 4 of CDCM61004
data sheet. The output frequency divider can be chosen using control pins. On PXIe-700 a 25
MHz clock input clock is used and for the output the control pins are set using 0 ohm resistors
R187 –R193. The factory default settings for output clock is 125 MHz by populating R191,
R192.
For any other clock output please contact Sundance DSP Inc.
Note: Please see appendix for pinouts
2.10 JTAG
A 14-pin 2mm pitch pin header is provided for connection to a Xilinx USB Programmer (using
the standard ribbon cable). This allows access to the internals of the FPGA for configuration and
debugging.
2.11 PXIe
The board conforms to PXIe specifications and provides a hybrid connector for PCIe and control
signals.

PXIe-700 User Guide Page 6 Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: [phone], Fax: [phone], email: [e-mail]
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
J2: 973028 from ERNI backplane connector. This is used to provide PCIe signals in PXIe
format.
J3: 214443 from ERNI backplane connector. This is used to provide PXI control signals.
Note: Please see appendix for pinout.