ON Semiconductor NTB30N20 User manual

©Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 4 1Publication Order Number:
NTB30N20/D
NTB30N20
Power MOSFET
30 Amps, 200 Volts
N−Channel Enhancement−Mode D2PAK
Features
•Source−to−DrainDiode Recovery Time Comparable to a Discrete
Fast Recovery Diode
•Avalanche Energy Specified
•IDSS and RDS(on) Specified at Elevated Temperature
•Mounting Information Provided for the D2PAK Package
•Pb−Free Packages are Available
Typical Applications
•PWM Motor Controls
•Power Supplies
•Converters
MAXIMUM RATINGS (TC= 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS 200 Vdc
Drain−to−Source Voltage (RGS = 1.0 MW)VDGR 200 Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms) VGS
VGSM "30 "40
Vdc
Drain Current − Continuous @ TA25°C
− Continuous @ TA100°C
− Pulsed (Note 2)
ID
ID
IDM
30
22
90
Adc
Total Power Dissipation @ TA= 25°C
Derate above 25°C
Total Power Dissipation @ TA= 25°C (Note 1)
PD
PD
214
1.43
2.0
W
W/°C
W
Operating and Storage Temperature Range TJ, Tstg −55 to
+175 °C
Single Drain−to−Source Avalanche Energy,
Starting TJ= 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL(pk) = 20 A, L = 3.0 mH, RG= 25 W)
EAS
450
mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
RqJC
RqJA
RqJA
0.7
62.5
50
°C/W
Maximum Lead Temperature for Soldering
Purposes for 10 seconds TL260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
2. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
123
4
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
30N20 = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
Device Package Shipping†
ORDERING INFORMATION
NTB30N20 D2PAK 50 Units/Rail
N−Channel
D
S
G
NTB30N20T4 D2PAK 800 Tape & Ree
l
VDSS RDS(ON) TYP IDMAX
200 V 68 mW@ VGS = 10 V 30 A
http://onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NTB30N20G D2PAK
(Pb−Free) 50 Units/Rail
NTB30N20T4G D2PAK
(Pb−Free) 800 Tape & Ree
l
30N20G
AYWW
1
Gate 3 Source
4
Drain
2
Drain

NTB30N20
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS (TC= 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID= 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS 200
−− 307 − −
Vdc
mV/°C
Zero Gate Voltage Collector Current
(VGS = 0 Vdc, VDS = 200 Vdc, TJ= 25°C)
(VGS = 0 Vdc, VDS = 200 Vdc, TJ= 175°C)
IDSS −
−− −5.0 125
mAdc
Gate−Body Leakage Current (VGS = ±30 Vdc, VDS = 0) IGSS − − ±100 nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
VDS = VGS, ID= 250 mAdc)
Temperature Coefficient (Negative)
VGS(th) 2.0
−2.9 −8.9 4.0 −
Vdc
mV/°C
Static Drain−to−Source On−State Resistance
(VGS = 10 Vdc, ID= 15 Adc)
(VGS = 10 Vdc, ID= 10 Adc)
(VGS = 10 Vdc, ID= 15 Adc, TJ= 175°C)
RDS(on) −
−
−
0.068
0.067
0.200
0.081
0.080
0.240
W
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID= 30 Adc) VDS(on) − 2.0 2.5 Vdc
Forward Transconductance (VDS = 15 Vdc, ID= 15 Adc) gFS − 20 − Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 2335 − pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
(VDS = 160 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Coss − −380 148 − −
Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Crss − 75 −
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
(VDD = 100 Vdc, ID= 18 Adc,
VGS = 5.0 Vdc, RG= 2.5 W)
(VDD = 160 Vdc, ID= 30 Adc,
VGS = 10 Vdc, RG= 9.1 W)
td(on) −
−10 12 − −ns
Rise Time tr−
−20 70 − −
Turn−Off Delay Time td(off) −
−40 82 − −
Fall Time tf−
−24 88 − −
Gate Charge (VDS = 160 Vdc, ID= 30 Adc,
VGS = 10 Vdc)
(VDS = 160 Vdc, ID= 18 Adc,
VGS = 5.0 Vdc)
Qtot −
−75 48 100 −nC
Qgs −
−20 16 − −
Qgd − 32 −
BODY−DRAIN DIODE RATINGS (Note 3)
Forward On−Voltage (IS= 30 Adc, VGS = 0 Vdc)
(IS= 30 Adc, VGS = 0 Vdc, TJ= 150°C) VSD − −0.91 0.80 1.1 −Vdc
Reverse Recovery Time (IS= 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
trr − 230 − ns
ta− 140 −
tb− 85 −
Reverse Recovery Stored Charge QRR − 1.85 − mC
3. Indicates Pulse Test: P. W. = 300 ms max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperature.

NTB30N20
http://onsemi.com
3
60
50
40
30
20
10
1
0
6420
08 0
VGS = 10 V
Figure 1. On−Region Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
60
50
40
30
20
10
106420
Figure 2. Transfer Characteristics
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0
Figure 3. On−Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
0.2
0.15
0.05
3525155
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
ID, DRAIN CURRENT (AMPS)
453525155
0.09
0.08
0.07
0.06
0.05
0
0.1
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
3
2
1.5
1
0.5
1751251007550250−25−50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4020
1000
100
10
0
100000
Figure 6. Drain−to−Source Leakage Current
versus Voltage
I
D
, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (
W
)
5545
0.1
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
55
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
IDSS, LEAKAGE (nA)
60 20
0
80
8
100 120 140
4 V
5 V
7 V
6 V
9 V TJ= 25°C
8 V
TJ= 25°C
TJ= −55°C
TJ= 100°C
VDS ≥10 V
TJ= 25°C
TJ= −55°C
TJ= 100°C
VGS = 10 V TJ= 25°C
VGS = 10 V
VGS = 15 V
ID= 15 A
VGS = 10 V TJ= 175°C
VGS = 0 V
TJ= 100°C
2.5
160 180150
10000

NTB30N20
http://onsemi.com
4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr= Q2x RG/(VGG − VGSP)
tf= Q2x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG= the gate drive resistance
and Q2and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RGCiss In [VGG/(VGG − VGSP)]
td(off) = RGCiss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces avoltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
005 510 20
015
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
6000
3000
1000
VGS VDS
5000
2000
4000
VGS = 0 VVDS = 0 V TJ= 25°C
Crss
Ciss
Coss
Crss Ciss
25

NTB30N20
http://onsemi.com
5
30
010.5
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
IS, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (W)
11010
0
1000
1
t, TIME (ns)
VDD = 160 V
ID= 30 A
VGS = 10 V
VGS = 0 V
TJ= 25°C
Figure 10. Diode Forward Voltage versus Current
180
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
150
120
90
60
30
0
10
6
2
0
QG, TOTAL GATE CHARGE (nC)
VDS,DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
8
4
20 7040 0
10
10 5030 60
0.6 0.7 0.8 0.9
10
15
20
5
25
ID= 30 A
TJ= 25°C
VGS
Q2 Q1
QT
VDS
tr
td(off)
td(on)
tf
100
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous IDcan safely be assumed to
equal the values indicated.

NTB30N20
http://onsemi.com
6
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
t, TIME (ms)
0.1
1.0
0.01
0.1
0.2
0.02
D = 0.5
0.05
0.01
SINGLE PULSE
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC= P(pk) RqJC(t)
P(pk)
t1t2
DUTY CYCLE, D = t1/t2
1.0 100.10.010.0010.00010.00001
TJ, STARTING JUNCTION TEMPERATURE (°C)
E
AS
, SINGLE PULSE DRAIN−TO−SOURC
E
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1 1.0 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 13. Thermal Response
1
1000
AVALANCHE ENERGY (mJ)
I
D
, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
25 50 75 100 125
200
10
10 17
5
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
100
400
300
500
1000
100
VGS = 20 V
SINGLE PULSE
TC= 25°C
1 ms
100 ms
10 ms
dc
10 ms
ID= 30 A
150

NTB30N20
http://onsemi.com
7
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SEATING
PLANE
S
G
D
−T−
M
0.13 (0.005) T
231
4
3 PL
K
J
H
V
E
C
A
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.340 0.380 8.64 9.65
B0.380 0.405 9.65 10.29
C0.160 0.190 4.06 4.83
D0.020 0.035 0.51 0.89
E0.045 0.055 1.14 1.40
G0.100 BSC 2.54 BSC
H0.080 0.110 2.03 2.79
J0.018 0.025 0.46 0.64
K0.090 0.110 2.29 2.79
S0.575 0.625 14.60 15.88
V0.045 0.055 1.14 1.40
−B−
M
B
W
W
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
F0.310 0.350 7.87 8.89
L0.052 0.072 1.32 1.83
M0.280 0.320 7.11 8.13
N0.197 REF 5.00 REF
P0.079 REF 2.00 REF
R0.039 REF 0.99 REF
M
L
F
M
L
F
M
L
F
VARIABLE
CONFIGURATION
ZONE RN P
U
VIEW W−W VIEW W−W VIEW W−W
123
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
17.02
0.67
10.66
0.42
3.05
0.12
5.08
0.20
ǒmm
inchesǓ
SCALE 3:1

NTB30N20
http://onsemi.com
8
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
NTB30N20/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.