SyncMOS Technologies International SM39R08A5 User manual

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-1-
Table of Contents
Product List.......................................................................................................................................................................... 3
Description ........................................................................................................................................................................... 3
Features............................................................................................................................................................................... 3
Pin Configuration ................................................................................................................................................................. 4
Block Diagram...................................................................................................................................................................... 5
Pin Description..................................................................................................................................................................... 6
Special Function Register (SFR) ......................................................................................................................................... 7
Function Description .......................................................................................................................................................... 10
1.General Features ........................................................................................................................................................ 10
1.1.Embedded Flash .......................................................................................................................................... 10
1.2.IO Pads ........................................................................................................................................................ 10
1.3.Instruction timing Selection .......................................................................................................................... 10
1.4.The Clock Output Selection ......................................................................................................................... 10
1.5.RESET ..........................................................................................................................................................11
1.5.1.Hardware RESET function...............................................................................................................11
1.5.2.Software RESET function ................................................................................................................11
1.5.3.Reset status .....................................................................................................................................11
1.5.4.Time Access Key register (TAKEY)................................................................................................. 12
1.5.5.Software Reset register (SWRES).................................................................................................. 12
1.5.6.Example of software reset .............................................................................................................. 12
1.6.Clocks .......................................................................................................................................................... 12
2.Instruction Set ............................................................................................................................................................. 13
3.Memory Structure ........................................................................................................................................................ 17
3.1.Program Memory ......................................................................................................................................... 17
3.2.Data Memory................................................................................................................................................ 18
3.2.1.Data memory - lower 128 byte (00h to 7Fh) ................................................................................... 18
3.2.2.Data memory - higher 128 byte (80h to FFh) ................................................................................. 18
4.CPU Engine................................................................................................................................................................. 19
4.1.Accumulator ................................................................................................................................................. 19
4.2.B Register .................................................................................................................................................... 19
4.3.Program Status Word................................................................................................................................... 20
4.4.Stack Pointer ................................................................................................................................................ 20
4.5.Data Pointer ................................................................................................................................................. 20
4.6.Data Pointer 1 .............................................................................................................................................. 21
4.7.Interface control register .............................................................................................................................. 21
5.GPIO............................................................................................................................................................................ 22
6.Timer 0 and Timer 1 .................................................................................................................................................... 23
6.1.Timer/counter mode control register (TMOD) .............................................................................................. 23
6.2.Timer/counter control register (TCON) ........................................................................................................ 24
6.3.T0、T1 signal swapping............................................................................................................................... 24
7.Serial interface ............................................................................................................................................................ 25
7.1.Mode 0 ......................................................................................................................................................... 26
7.2.Mode 1 ......................................................................................................................................................... 26
7.3.Mode 2 ......................................................................................................................................................... 27
7.4.Mode 3 ......................................................................................................................................................... 27
7.5.Multiprocessor communication .................................................................................................................... 27
7.6.Baud rate generator ..................................................................................................................................... 28
8.Watchdog timer ........................................................................................................................................................... 29
9.Interrupt ....................................................................................................................................................................... 32
10.Power Management Unit............................................................................................................................................. 37
10.1.Idle mode ..................................................................................................................................................... 37
10.2.Stop mode .................................................................................................................................................... 37
11.PWM - Pulse Width Modulation .................................................................................................................................. 38
12.IIC function .................................................................................................................................................................. 41

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-2-
13.LVI – Low Voltage Interrupt ......................................................................................................................................... 45
14.10-bit Analog-to-Digital Converter (ADC) .................................................................................................................... 46
15.EEPROM..................................................................................................................................................................... 49
16.Comparator ................................................................................................................................................................. 51
DC Characteristics............................................................................................................................................................. 53
ADC Characteristics .......................................................................................................................................................... 55
Comparator Characteristics ............................................................................................................................................... 55
LVI& LVR Characteristics................................................................................................................................................... 56

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-3-
Product List
SM39R08A5W10MP
Description
The SM39R08A5 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 8K-byte
embedded Flash for program, and executes all ASM51
instructions fully compatible with MCS-51.
SM39R08A5 contains 256B on-chip RAM, more than 8
GPIOs (10L package), various serial interfaces and
many peripheral functions as described below. It can be
programmed via writers. Its on-chip ICE is convenient for
users in verification during development stage.
The high performance of SM39R08A5 can achieve
complicated manipulation within short time. About one
third of the instructions are pure 1T, and the average
speed is 8 times of traditional 8051, the fastest one
among all the 1T 51-series.Its excellent EMI and ESD
characteristics are advantageous for many different
applications.
Ordering Information
SM39R08A5ihhkL yymmv
i: process identifier {W = 1.8V ~ 5.5V}
hh: pin count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
yy: year
mm: month
v: version identifier{ A, B,…}
Postfix Package Pin / Pad
Configuration
M MSOP (118 mil) Page 4
Features
Operating Voltage: 1.8V ~ 5.5V
1~8T modes are software programmable.
Instruction-set compatible with MCS-51.
22.1184MHz Internal RC oscillator, with
programmable clock divider
8K Bytes on-chip flash program memory.
256 bytes RAM as standard 8052,
One serial peripheral interfaces in full duplex mode.
1.1 Synchronous mode, fixed baud rate,
1.2 8-bit UART mode, variable baud rate.
1.3 9-bit UART mode, fixed baud rate,
1.4 9-bit UART mode, variable baud rate.
Additional Baud Rate Generator
Two 16-bit Timer/Counters. (Timer 0, 1)
8 GPIOs(10L MSOP)
Programmable watchdog timer.
One IIC interface. (Master/Slave mode)
10 bit PWM x 4 channel
8 channel 10-bit analog-to-digital converter (ADC)
On-Chip Comparator x 1
On–chip flash memories support IAP/ICP and
EEPROM functions.
On-Chip in-circuit emulator (ICE) functions with
On-Chip Debugger (OCD).
EMI reduction mode (ALE output inhibited).
LVI/LVR.
IO PAD ESD over 4KV.
Enhance user code protection.
External interrupt 0, 1 with four priority levels.
Power management unit for IDLE and power down
modes.

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-4-
Pin Configuration
10 Pin MSOP
(10 Pin Top View)
SM39R08A5
Notes：
1. The pin Reset/P3.6 factory default is GPIO(P3.6). User can configure it to Reset by a flash programmer.

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-5-
Block Diagram
PWM
Flash 8KBytes
SRAM
256Bytes
Interrupt
Timer 0/1
Watchdog
ICE ICP
Port 3 Port 3
T0
T1
SCL
PWM0~3
Interface control
INT0/1
SDA
IIC
SCL
SDA
MAX810
RESET UART
RXD
TXD
Analog
comparator
Cmp0Out
Cmp0NIn Cmp0PIn
ADC
ADC[7:0]

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-6-
Pin Description
10 Pin Symbol I/O Description
1
- P3.0
- RXD
- T0_2
- Cmp0Nin
- ADC0
I/O
- Bit 0 of port 3
- Serial interface receive data
- Timer 0 external input 2
- Comparator 0 negative input
- ADC input channel 0
2
- P3.1
- TXD
- T1_2
- Cmp0PIn
- ADC1
I/O
- Bit 1 of port 3
- Serial interface transmit data
- Timer 1 external input 2
- Comparator 0 positive input
- ADC input channel 1
3
- P3.2
- PWM3
- ADC2
- T1_1
I/O
- Bit 2 of port 3
- PWM channel 3
- ADC input channel 2
- Timer 1 external input 1
4
- P3.3
- PWM2
- ADC3
- T0_1
I/O
- Bit 3 of port 3
- PWM channel 2
- ADC input channel 3
- Timer 0 external input 1
5 VSS I Power supply
6
- P3.4
- INT0_0
- SDA
- ADC4
I/O
- Bit 4 of port 3
- External interrupt 0
- IIC SDA pin & On-Chip Instrumentation Command and data
I/O pin synchronous to SCL in ICE and ICP functions
- ADC input channel 4
7
- P3.5
- INT1_1
- PWM1
- SCL
- CLKOUT
- ADC5
I/O
- Bit 5 of port 3
- External interrupt 1
- PWM channel 1
- IIC SCL pin & On-Chip Instrumentation Clock I/O pin of ICE
and ICP functions
- Clock output
- ADC input channel 5
8
- P3.6
- RESET
- PWM0
- ADC6
I/O
- Bit 6 of port 3
- Reset pin
- PWM channel 0
- ADC input channel 6
9
- P3.7
- INT1_0
- Cmp0Out
- ADC7
I/O
- Bit 7 of port 3
- External interrupt 1
- Comparator 0 output
- ADC input channel 7
10 VDD I Power supply

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-7-
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/Hex
F8 IICS IICCTL IICA1 IICA2 IICRWD IICEBT CMP0CON FF
F0 B OPPIN TAKEY F7
E8 EF
E0 ACC ISPFAH ISPFAL ISPFD ISPFC LVC SWRES E7
D8 P3M0 P3M1 DF
D0 PSW D7
C8 PWMMDH PWMMDL CF
C0 IRCON C7
B8 IEN1 IP1 SRELH PWMD0H PWMD0L PWMD1H PWMD1L BF
B0 P3 PWMD2H PWMD2L PWMD3H PWMD3L PWMC WDTC WDTK B7
A8 IEN0 IP0 SRELL ADCC1 ADCC2 ADCDH ADCDL ADCCS AF
A0 RSTS A7
98 SCON SBUF IEN2 9F
90 AUX IRCON2 97
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON IFCON 8F
80 SP DPL DPH DPL1 DPH1 PCON 87
Note: Special Function Registers reset values and description for SM39R08A5
Register Location Reset value Description
SP 81h 07h Stack Pointer
DPL 82h 00h Data Pointer 0 low byte
DPH 83h 00h Data Pointer 0 high byte
DPL1 84h 00h Data Pointer 1 low byte
DPH1 85h 00h Data Pointer 1 high byte
PCON 87h 00h Power Control
TCON 88h 00h Timer/Counter Control
TMOD 89h 00h Timer Mode Control
TL0 8Ah 00h Timer 0, low byte
TL1 8Bh 00h Timer 1, low byte
TH0 8Ch 00h Timer 0, high byte
TH1 8Dh 00h Timer 1, high byte
CKCON 8Eh 10h Clock control register
IFCON 8Fh 00h Interface control register

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-8-
AUX 91h 00h Auxiliary register
SCON 98h 00h Serial Port Control Register
SBUF 99h 00h Serial Port Data Buffer
IEN2 9Ah 00h Interrupt Enable Register 2
RSTS A1h 00h Reset status register
IEN0 A8h 00h Interrupt Enable Register 0
IP0 A9h 00h Interrupt Priority Register 0
SRELL AAh 00h Serial Port Reload Register, low byte
ADCC1 ABh 00h ADC Control 1 Register
ADCC2 ACh 00h ADC Control 2 Register
ADCDH ADh 00h ADC data high byte
ADCDL AEh 00h ADC data low byte
ADCCS AFh 00h ADC clock select
P3 B0h FFh Port 3
PWMD2H B1h 00h PWM 2 Data register high byte
PWMD2L B2h 00h PWM 2 Data register low byte
PWMD3H B3h 00h PWM 3 Data register high byte
PWMD3L B4h 00h PWM 3 Data register low byte
PWMC B5h 00h PWM control register
WDTC B6h 04h Watchdog timer control register
WDTK B7h 00h Watchdog timer refresh key.
IEN1 B8h 00h Interrupt Enable Register 1
IP1 B9h 00h Interrupt Priority Register 1
SRELH BAh 00h Serial Port Reload Register, high byte
PWMD0H BCh 00h PWM 0 Data register high byte
PWMD0L BDh 00h PWM 0 Data register low byte
PWMD1H BEh 00h PWM 1 Data register high byte
PWMD1L BFh 00h PWM 1 Data register low byte
IRCON C0h 00h Interrupt Request Control Register
PWMMDH CEh 00h PWM Max Data Register, high byte.
PWMMDL CFh 00h PWM Max Data Register, low byte.
PSW D0h 00h Program Status Word
P3M0 DAh 00h Port 3 output mode 0
P3M1 DBh 00h Port 3 output mode 1
ACC E0h 00h Accumulator
ISPFAH E1h 0Fh ISP Flash Address-High register
ISPFAL E2h FFh ISP Flash Address-Low register
ISPFD E3h FFh ISP Flash Data register
ISPFC E4h 00h ISP Flash control register
LVC E6h 20h Low voltage control register
SWRES E7h 00h Software Reset register
B F0h 00h B Register
OPPIN F6H 00h
Op/Cmp pin select

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-9-
TAKEY F7h 00h Time Access Key register
IICS F8h 00h IIC status register
IICCTL F9h 04h IIC control register
IICA1 FAh A0h IIC channel Address 1 register
IICA2 FBh 60h IIC channel Address 2 register
IICRWD FCh 00h IIC channel Read / Write Data buffer
IICEBT FDh 00h IIC Enable Bus Transaction
CMP0CON FEh 00h Comparator 0 control

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-10-
Function Description
1. General Features
SM39R08A5 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the following
sections.
1.1. Embedded Flash
The program can be loaded into the embedded 8KB Flash memory via its writer. The high-quality Flash has a 100K-write
cycle life, suitable for re-programming and data recording as EEPROM.
1.2. IO Pads
The SM39R08A5 has an I/O port: Port 3. Port 3 is 8-bit port. These are: quasi-bidirectional (standard 8051 port outputs),
push-pull, open drain, and input-only. As described in section 5.
The RESET Pin can be configured as I/O port P3.6, when the user uses on-chip hardware RESET mechanism.
1.3. Instruction timing Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM39R08A5 is a 1T to 8T MCU,
i.e., its machine cycle is one-clock to eight-clock. In the other words, it can execute one instruction within one clock to only
eight clocks.
Mnemonic: CKCON Address: 8Eh
7 6 5 4 3 2 1 0 Reset
- ITS - - CLKOUT 10H
ITS: Instruction timing select.
ITS [6:4] Instruction timing
000 1T mode
001 2T mode (default)
010 3T mode
011 4T mode
100 5T mode
101 6T mode
110 7T mode
111 8T mode
The default is in 2T mode, and it can be changed to another Instruction timing mode if CKCON [6:4] (at address 8Eh) is
change any time. Not every instruction can be executed with one machine cycle. The exact machine cycle number for all
the instructions are given in the next section.
1.4. The Clock Output Selection
The SM39R08A5 can generate a clock output signal at P3.5. The CKCON [1:0] (at address 8Eh) can change any time.
CLKOUT: Clock output select.
CKCON [1:0] Mode.
00 GPIO (P3.5)

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-11-
01 Fosc
10 Fosc/2
11 Fosc/4
1.5. RESET
1.5.1. Hardware RESET function
SM39R08A5 provides on-chip hardware RESET mechanism,，the reset duration is programmable by writer or ICP。
on-chip hardware RESET duration
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.5.2. Software RESET function
SM39R08A5 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must
write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register
(SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the SWRES
register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES register is
self-reset at the end of the software reset procedure.
Mnemonic Description Direct Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET
Software Reset function
TAKEY Time Access Key register F7h TAKEY [7:0] 00H
SWRES Software Reset register E7h SWRES [7:0] 00H
1.5.3. Reset status
Mnemonic: RSTS Address: A1h
7 6 5 4 3 2 1 0 Reset
- - - PDRF WDTF SWRF LVRF PORF 00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag
clear by software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by
software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear
by software.

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-12-
1.5.4. Time Access Key register (TAKEY)
Mnemonic: TAKEY Address: F7H
7 6 5 4 3 2 1 0 Reset
TAKEY [7:0] 00H
Software reset register (SWRES) is read-only by default; software must write three specific values
55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That
is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
1.5.5. Software Reset register (SWRES)
Mnemonic: SWRES Address: E7H
7 6 5 4 3 2 1 0 Reset
SWRES [7:0] 00H
SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
1.5.6. Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #0FFh; software reset MCU
1.6. Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division as given in Table 1-1, the clock
source can set by writer or ICP.
Table 1-1: Selection of clock source
Clock source
22.1184MHz from internal OSC
11.0592MHz from internal OSC
5.5296MHz from internal OSC
2.7648MHz from internal OSC
1.3824MHz from internal OSC

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-13-
2. Instruction Set
All SM39R08A5 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM39R08A5 Microcontroller core.
Table 2-1: Arithmetic operations
Mnemonic Description Code Bytes Cycles
ADD A,Rn Add register to accumulator 28-2F 1 1
ADD A,direct Add direct byte to accumulator 25 2 2
ADD A,@Ri Add indirect RAM to accumulator 26-27 1 2
ADD A,#data Add immediate data to accumulator 24 2 2
ADDC A,Rn Add register to accumulator with carry flag 38-3F 1 1
ADDC A,direct Add direct byte to A with carry flag 35 2 2
ADDC A,@Ri Add indirect RAM to A with carry flag 36-37 1 2
ADDC A,#data Add immediate data to A with carry flag 34 2 2
SUBB A,Rn Subtract register from A with borrow 98-9F 1 1
SUBB A,direct Subtract direct byte from A with borrow 95 2 2
SUBB A,@Ri Subtract indirect RAM from A with borrow 96-97 1 2
SUBB A,#data Subtract immediate data from A with borrow 94 2 2
INC A Increment accumulator 04 1 1
INC Rn Increment register 08-0F 1 2
INC direct Increment direct byte 05 2 3
INC @Ri Increment indirect RAM 06-07 1 3
INC DPTR Increment data pointer A3 1 1
DEC A Decrement accumulator 14 1 1
DEC Rn Decrement register 18-1F 1 2
DEC direct Decrement direct byte 15 2 3
DEC @Ri Decrement indirect RAM 16-17 1 3
MUL AB Multiply A and B A4 1 5
DIV Divide A by B 84 1 5
DA A Decimal adjust accumulator D4 1 1

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-14-
Table 2-2: Logic operations
Mnemonic Description Code Bytes Cycles
ANL A,Rn AND register to accumulator 58-5F 1 1
ANL A,direct AND direct byte to accumulator 55 2 2
ANL A,@Ri AND indirect RAM to accumulator 56-57 1 2
ANL A,#data AND immediate data to accumulator 54 2 2
ANL direct,A AND accumulator to direct byte 52 2 3
ANL direct,#data AND immediate data to direct byte 53 3 4
ORL A,Rn OR register to accumulator 48-4F 1 1
ORL A,direct OR direct byte to accumulator 45 2 2
ORL A,@Ri OR indirect RAM to accumulator 46-47 1 2
ORL A,#data OR immediate data to accumulator 44 2 2
ORL direct,A OR accumulator to direct byte 42 2 3
ORL direct,#data OR immediate data to direct byte 43 3 4
XRL A,Rn Exclusive OR register to accumulator 68-6F 1 1
XRL A,direct Exclusive OR direct byte to accumulator 65 2 2
XRL A,@Ri Exclusive OR indirect RAM to accumulator 66-67 1 2
XRL A,#data Exclusive OR immediate data to accumulator 64 2 2
XRL direct,A Exclusive OR accumulator to direct byte 62 2 3
XRL direct,#data Exclusive OR immediate data to direct byte 63 3 4
CLR A Clear accumulator E4 1 1
CPL A Complement accumulator F4 1 1
RL A Rotate accumulator left 23 1 1
RLC A Rotate accumulator left through carry 33 1 1
RR A Rotate accumulator right 03 1 1
RRC A Rotate accumulator right through carry 13 1 1
SWAP A Swap nibbles within the accumulator C4 1 1

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-15-
Table 2-3: Data transfer
Mnemonic Description Code Bytes Cycles
MOV A,Rn Move register to accumulator E8-EF 1 1
MOV A,direct Move direct byte to accumulator E5 2 2
MOV A,@Ri Move indirect RAM to accumulator E6-E7 1 2
MOV A,#data Move immediate data to accumulator 74 2 2
MOV Rn,A Move accumulator to register F8-FF 1 2
MOV Rn,direct Move direct byte to register A8-AF 2 4
MOV Rn,#data Move immediate data to register 78-7F 2 2
MOV direct,A Move accumulator to direct byte F5 2 3
MOV direct,Rn Move register to direct byte 88-8F 2 3
MOV direct1,direct2 Move direct byte to direct byte 85 3 4
MOV direct,@Ri Move indirect RAM to direct byte 86-87 2 4
MOV direct,#data Move immediate data to direct byte 75 3 3
MOV @Ri,A Move accumulator to indirect RAM F6-F7 1 3
MOV @Ri,direct Move direct byte to indirect RAM A6-A7 2 5
MOV @Ri,#data Move immediate data to indirect RAM 76-77 2 3
MOV DPTR,#data16 Load data pointer with a 16-bit constant 90 3 3
MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator 93 1 3
MOVC A,@A+PC Move code byte relative to PC to accumulator 83 1 3
PUSH direct Push direct byte onto stack C0 2 4
POP direct Pop direct byte from stack D0 2 3
XCH A,Rn Exchange register with accumulator C8-CF 1 2
XCH A,direct Exchange direct byte with accumulator C5 2 3
XCH A,@Ri Exchange indirect RAM with accumulator C6-C7 1 3
XCHD A,@Ri Exchange low-order nibble indir. RAM with A D6-D7 1 3

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-16-
Table 2-4: Program branches
Mnemonic Description Code Bytes Cycles
ACALL addr11 Absolute subroutine call xxx11 2 6
LCALL addr16 Long subroutine call 12 3 6
RET from subroutine 22 1 4
RETI from interrupt 32 1 4
AJMP addr11 Absolute jump xxx01 2 3
LJMP addr16 Long iump 02 3 4
SJMP rel Short jump (relative addr.) 80 2 3
JMP @A+DPTR Jump indirect relative to the DPTR 73 1 2
JZ rel Jump if accumulator is zero 60 2 3
JNZ rel Jump if accumulator is not zero 70 2 3
JC rel Jump if carry flag is set 40 2 3
JNC Jump if carry flag is not set 50 2 3
JB bit,rel Jump if direct bit is set 20 3 4
JNB bit,rel Jump if direct bit is not set 30 3 4
JBC bit,direct rel Jump if direct bit is set and clear bit 10 3 4
CJNE A,direct rel Compare direct byte to A and jump if not equal B5 3 4
CJNE A,#data rel Compare immediate to A and jump if not equal B4 3 4
CJNE Rn,#data rel Compare immed. to reg. and jump if not equal B8-BF 3 4
CJNE @Ri,#data rel Compare immed. to ind. and jump if not equal B6-B7 3 4
DJNZ Rn,rel Decrement register and jump if not zero D8-DF 2 3
DJNZ direct,rel Decrement direct byte and jump if not zero D5 3 4
NOP No operation 00 1 1
Table 2-5: Boolean manipulation
Mnemonic Description Code Bytes Cycles
CLR C Clear carry flag C3 1 1
CLR bit Clear direct bit C2 2 3
SETB C Set carry flag D3 1 1
SETB bit Set direct bit D2 2 3
CPL C Complement carry flag B3 1 1
CPL bit Complement direct bit B2 2 3
ANL C,bit AND direct bit to carry flag 82 2 2
ANL C,/bit AND complement of direct bit to carry B0 2 2
ORL C,bit OR direct bit to carry flag 72 2 2
ORL C,/bit OR complement of direct bit to carry A0 2 2
MOV C,bit Move direct bit to carry flag A2 2 2
MOV bit,C Move carry flag to direct bit 92 2 3

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-17-
3. Memory Structure
The SM39R08A5 memory structure follows general 8052 structure. It is 8KB program memory.
3.1. Program Memory
The SM39R08A5 has 8KB on-chip flash memory which can be used as general program memory or EEPROM. The
address range for the 8K byte is $0000 to $1FFF. It can be used to record any data as EEPROM. The procedure of this
EEPROM application function is described in the section 15.
1FFF
0000
8K Program
Memory space
Fig. 3-1: SM39R08A5 programmable Flash

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-18-
3.2. Data Memory
The SM39R08A5 has 256Bytes on-chip SRAM; 256 Bytes of it are the same as general 8052 internal memory structure
Higher 128 Bytes (Accessed by
indirect addressing mode only)
Lower 128 Bytes (Accessed by
direct & indirect addressing mode )
SFR (Accessed by direct addressing
mode only)
00
7F
80
FF
80
FF
Fig. 3-2: RAM architecture
3.2.1. Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.2.2. Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-19-
4. CPU Engine
The SM39R08A5 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM39R08A5 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following chapter describes the main engine register.
Mnemonic Description Direct Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET
8051 Core
ACC Accumulator E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00H
B B register F0h B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00H
PSW Program status
word D0h CY AC F0 RS[1:0] OV PSW.1 P 00H
SP Stack Pointer 81h SP[7:0] 07H
DPL Data pointer low 0 82h DPL[7:0] 00H
DPH Data pointer high
0 83h DPH[7:0] 00H
DPL1 Data pointer low 0 84h DPL1[7:0] 00H
DPH1 Data pointer high
0 85h DPH1[7:0] 00H
AUX Auxiliary register 91h BRGS - - PTS[1:0] PINTS[1:0] DPS 00H
IFCON Interface control
register 8Fh - CDPR - - - - - ISPE 00H
4.1. Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC Address: E0h
7 6 5 4 3 2 1 0 Reset
ACC.7 ACC.6 ACC05 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2. B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B Address: F0h
7 6 5 4 3 2 1 0 Reset
B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.

SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver.A SM39R08A5 02/2013
-20-
4.3. Program Status Word
Mnemonic: PSW Address: D0h
7 6 5 4 3 2 1 0 Reset
CY AC F0 RS [1:0] OV F1 P 00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0] Bank Selected Location
00 Bank 0 00h – 07h
01 Bank 1 08h – 0Fh
10 Bank 2 10h – 17h
11 Bank 3 18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity.
4.4. Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to start from location 08h.
Mnemonic: SP Address: 81h
7 6 5 4 3 2 1 0 Reset
SP [7:0] 07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5. Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR, @DPTR respectively).
Mnemonic: DPL Address: 82h
7 6 5 4 3 2 1 0 Reset
DPL [7:0] 00h
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH Address: 83h
7 6 5 4 3 2 1 0 Reset
DPH [7:0] 00h
DPH [7:0]: Data pointer High 0