TEDIA OPT-821A User manual

General description
The OPT-821A daughter board provides optical isolation and input digital signal
conditioning of the DAQ cards.
The board provides eight input blocks (isolated between each other) for processing
DC signals up to 32 V. All channels work as inverting, i.e. high input voltage is
represented by the output level "L". Every channel is fitted with an indicating LED,
signalizing high input signal level.
The output port operates in NPN open collector mode (requires pull-up resistors;
meets all DAQ cards TEDIA) or TTL mode (requires an external power supply).
General instructions for use
The OPT-821A board is designed for DAQ&C applications and may be used only
according to the manufacturer's recommendations and precautions given in this
manual and other general standards and terms and may be used only such a way,
that its failure caused by any reason will not be dangerous to any person or property.
Installation
The OPT-821A board is supplied as an unencapsulated kit intended for fastening via
four screws, a plastic housing DIN-801 suitable for mounting on the 35 mm DIN
rail is supplied optionally.
The board can be used in an environment with operating temperature -10~60 °C and
relative humidity up to 90%, noncondensing and normal levels of pollution.
Specifications
input voltage - level L: < 5 VDC (i.e. level H on the output signal)
input voltage - level H: > 15 VDC (i.e. level L on the output signal)
maximum input voltage: ±50 VDC
input impedance: 6 kOhm approx.
output voltage - level L: < 0.5 V (1.6 mA max.)
output voltage - level H: > 2.5 V (0.5 mA max., TTL mode)
signal delay: < 0.5 ms
isolation voltage (see note below): 1500 VAC (all inputs against outputs)
100 VDC (between inputs)
power supply (see note below): +8~30 VDC (10 mA typ., 15 mA max.)
recommended cable length: 10 m max. (input signals)
2 m max. (output signals)
dimensions of board: 72 x 88 mm
mounting hole spacing: 61.5 x 77 mm
mounting hole diameter: 3.5 mm
Note: "AC" indicates the rms value of a 50 Hz AC harmonic signal.
Note: The power supply is required only for TTL mode.
K1 connector pin assigment (interface port, D-Sub 9, female)
1 CH0 - DIN port signal (PC card) 6 CH1 - DIN port signal (PC card)
2 CH2 - DIN port signal (PC card) 7 CH3 - DIN port signal (PC card)
3 CH4 - DIN port signal (PC card) 8 CH5 - DIN port signal (PC card)
4 CH6 - DIN port signal (PC card) 9 CH7 - DIN port signal (PC card)
5 GND - common signal (PC card)
Note: The OPT-821A signals operate in "NPN open collector" mode or in TTL levels.
SV1 terminals pin assigment (digital inputs)
1 CH0 - input signal (positive) 9 CH4 - input signal (positive)
2 CH0 - input signal (negative) 10 CH4 - input signal (negative)
3 CH1 - input signal (positive) 11 CH5 - input signal (positive)
4 CH1 - input signal (negative) 12 CH5 - input signal (negative)
5 CH2 - input signal (positive) 13 CH6 - input signal (positive)
6 CH2 - input signal (negative) 14 CH6 - input signal (negative)
7 CH3 - input signal (positive) 15 CH7 - input signal (positive)
8 CH3 - input signal (negative) 16 CH7 - input signal (negative)
Note: The schematic of the input circuits is shown in the figure Fig. 1.
SV2 terminal block pin assigment (power supply)
1 power supply (+8~30 VDC, current consumption 10 mA typ., 15 mA max.)
2 power supply (GND, directly connected to pin 5 of K1 connector)
Note: The power supply is required only for TTL mode.
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
OPT-821A
SV1
K1
SV2
116
2 1

Fig. 1. Simplified schematic of OPT-821A internal circuits.
An external power supply 8~30V is not required if the input port of the PC
card is equipped with pull-up resistors (all types of TEDIA cards are
equipped with pull-up resistors).
Manufacturing, sales office, service center and technical support:
TEDIA spol. s r. o.
Zabelska 12, 31200 Plzen, Czech Republic
phone/e-mail: https://www.tedia.eu/contacts
address:
SV1-15
SV1-3
SV1-1
SV1-16
K1-6
K1-9
K1-5
K1-1
SV1-2
SV1-4
5V SV2-1
SV2-2
6K0
4K7
6K0
4K7
6K0
4K7
8~30V
OPT-821A
User Guide
(further information available at http://www.tedia.eu)
document revision: 02.2013, © 1994-2013 TEDIA®spol. s r. o.