Texas Instruments TMS320C645X User manual

TMS320C645x Serial Rapid IO (SRIO)
User's Guide
Literature Number: SPRU976March 2006

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Contents
Preface .............................................................................................................................. 131 Overview .................................................................................................................. 141.1 General RapidIO System ......................................................................................... 141.2 RapidIO Feature Support in SRIO .............................................................................. 171.3 Standards .......................................................................................................... 181.4 External Devices Requirements ................................................................................. 182 SRIO Functional Description ....................................................................................... 192.1 Overview ............................................................................................................ 192.2 SRIO Pins .......................................................................................................... 242.3 Functional Operation .............................................................................................. 243 Logical/Transport Error Handling and Logging ............................................................. 734 Interrupt Conditions ................................................................................................... 744.1 CPU Interrupts ..................................................................................................... 744.2 General Description ............................................................................................... 744.3 Interrupt Condition Control Registers ........................................................................... 754.4 Interrupt Status Decode Registers .............................................................................. 834.5 Interrupt Generation ............................................................................................... 854.6 Interrupt Pacing .................................................................................................... 854.7 Interrupt Handling ................................................................................................. 865 SRIO Registers .......................................................................................................... 885.1 Introduction ......................................................................................................... 885.2 Peripheral Identification Register (PID) ......................................................................... 995.3 Peripheral Control Register (PCR) ............................................................................ 1005.4 Peripheral Settings Control Register (PER_SET_CNTL) ................................................... 1015.5 Peripheral Global Enable Register (GBL_EN) ............................................................... 1045.6 Peripheral Global Enable Status Register (GBL_EN_STAT) .............................................. 1055.7 Block nEnable Register (BLK n_EN) .......................................................................... 1065.8 Block nEnable Status Register (BLK n_EN_STAT) ......................................................... 1075.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) ......................................................... 1085.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) ......................................................... 1095.11 Packet Forwarding Register nfor 16b DeviceIDs (PF_16B_CNTL n)..................................... 1105.12 Packet Forwarding Register nfor 8b DeviceIDs (PF_8B_CNTL n)........................................ 1115.13 SERDES Receive Channel Configuration Registers n(SERDES_CFGRX n_CNTL) ................... 1125.14 SERDES Transmit Channel Configuration Registers n(SERDES_CFGTX n_CNTL) .................. 1145.15 SERDES Macro Configuration Register n(SERDES_CFG n_CNTL) ..................................... 1165.16 DOORBELL nInterrupt Status Register (DOORBELL n_ICSR) ............................................ 1175.17 DOORBELL nInterrupt Clear Register (DOORBELL n_ICCR) ............................................. 1185.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ...................................................... 1195.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ....................................................... 1205.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ....................................................... 1215.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ........................................................ 1225.22 LSU Status Interrupt Register (LSU_ICSR) .................................................................. 1235.23 LSU Clear Interrupt Register (LSU _ICCR) .................................................................. 1245.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) ................. 125
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5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) .................. 1265.26 DOORBELL nInterrupt Condition Routing Register (DOORBELL n_ICRR) .............................. 1275.27 DOORBELL nInterrupt Condition Routing Register 2 (DOORBELL n_ICRR2) .......................... 1285.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) ....................................... 1295.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) ...................................... 1305.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) ........................................ 1315.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) ...................................... 1325.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) ....................................... 1335.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) ....................................... 1345.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) ....................................... 1355.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) ....................................... 1365.36 Error, Reset, and Special Event Interrupt Condition Routing Register(ERR_RST_EVNT_ICRR) ...................................................................................... 1375.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2(ERR_RST_EVNT_ICRR2) ..................................................................................... 1385.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3(ERR_RST_EVNT_ICRR3) ..................................................................................... 1395.39 INTDST nInterrupt Status Decode Registers (INTDST n_DECODE)...................................... 1405.40 INTDST nInterrupt Rate Control Registers (INTDST n_RATE_CNTL) .................................... 1415.41 LSU nControl Register 0 (LSU n_REG0) ...................................................................... 1425.42 LSU nControl Register 1 (LSU n_REG1) ...................................................................... 1435.43 LSU nControl Register 2 (LSU n_REG2) ...................................................................... 1445.44 LSU nControl Register 3 (LSU n_REG3) ...................................................................... 1455.45 LSU nControl Register 4 (LSU n_REG4) ...................................................................... 1465.46 LSU nControl Register 5 (LSU n_REG5) ...................................................................... 1475.47 LSU nControl Register 6 (LSU n_REG6) ...................................................................... 1485.48 LSU Congestion Control Flow Mask n(LSU_FLOW_MASKS n).......................................... 1495.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) ................. 1505.50 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) ......................... 1515.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) .................. 1525.52 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) .......................... 1535.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) ...................................... 1545.54 Transmit CPPI Supported Flow Mask Registers n(TX_CPPI_FLOW_MASKS n)....................... 1555.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ....................................... 1575.56 Receive CPPI Control Register (RX_CPPI_CNTL) ......................................................... 1585.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) ..................... 1595.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) ..................... 1605.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) ..................... 1615.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) ..................... 1625.61 Mailbox-to-Queue Mapping Register L n(RXU_MAP_L n).................................................. 1635.62 Mailbox-to-Queue Mapping Register H n(RXU_MAP_H n)................................................. 1645.63 Flow Control Table Entry Registers (FLOW_CNTL n)....................................................... 1655.64 Device Identity CAR (DEV_ID) ................................................................................. 1665.65 Device Information CAR (DEV_INFO) ........................................................................ 1675.66 Assembly Identity CAR (ASBLY_ID) .......................................................................... 1685.67 Assembly Information CAR (ASBLY_INFO).................................................................. 1695.68 Processing Element Features CAR (PE_FEAT) ............................................................. 1705.69 Source Operations CAR (SRC_OP)........................................................................... 1715.70 Destination Operations CAR (DEST_OP) .................................................................... 1725.71 Processing Element Logical Layer Control CSR (PE_LL_CTL) ........................................... 173
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5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ................................... 1745.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ..................................... 1755.74 Base Device ID CSR (BASE_ID) .............................................................................. 1765.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) ............................................... 1775.76 Component Tag CSR (COMP_TAG) .......................................................................... 1785.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) ............................ 1795.78 Port Link Time-Out Control CSR (SP_LT_CTL) ............................................................. 1805.79 Port Response Time-Out Control CSR (SP_RT_CTL) ..................................................... 1815.80 Port General Control CSR (SP_GEN_CTL) .................................................................. 1825.81 Port Link Maintenance Request CSR n(SP n_LM_REQ) .................................................. 1835.82 Port Link Maintenance Response CSR n(SP n_LM_RESP) ............................................... 1845.83 Port Local AckID Status CSR n(SP n_ACKID_STAT) ...................................................... 1855.84 Port Error and Status CSR n(SP n_ERR_STAT) ............................................................ 1865.85 Port Control CSR n(SP n_CTL) ................................................................................ 1885.86 Error Reporting Block Header (ERR_RPT_BH) ............................................................. 1905.87 Logical/Transport Layer Error Detect CSR (ERR_DET) .................................................... 1915.88 Logical/Transport Layer Error Enable CSR (ERR_EN) ..................................................... 1925.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)................................. 1935.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) .......................................... 1945.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) ............................................. 1955.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ............................................ 1965.93 Port-Write Target Device ID CSR (PW_TGT_ID) ........................................................... 1975.94 Port Error Detect CSR n(SP n_ERR_DET) .................................................................. 1985.95 Port Error Rate Enable CSR n(SP n_RATE_EN) ........................................................... 1995.96 Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) ............................... 2005.97 Port nPacket/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) ....................... 2015.98 Port nPacket/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) ....................... 2025.99 Port nPacket/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) ....................... 2035.100 Port nPacket/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) ...................... 2045.101 Port Error Rate CSR n(SP n_ERR_RATE) .................................................................. 2055.102 Port Error Rate Threshold CSR n(SP n_ERR_THRESH) ................................................. 2065.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .................................... 2075.104 Port IP Mode CSR (SP_IP_MODE) .......................................................................... 2085.105 Serial Port IP Prescalar (IP_PRESCAL) ..................................................................... 2105.106 Port-Write-In Capture CSR n(SP_IP_PW_IN_CAPT n)................................................... 2115.107 Port Reset Option CSR n(SP n_RST_OPT) ................................................................ 2125.108 Port Control Independent Register n(SP n_CTL_INDEP) ................................................. 2135.109 Port Silence Timer n(SP n_SILENCE_TIMER) ............................................................. 2155.110 Port Multicast-Event Control Symbol Request Register n(SP n_MULT_EVNT_CS) .................. 2165.111 Port Control Symbol Transmit n(SP n_CS_TX) ............................................................. 217
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List of Figures
1 RapidIO Architectural Hierarchy .......................................................................................... 152 RapidIO Interconnect Architecture ....................................................................................... 163 Serial RapidIO Device to Device Interface Diagrams ................................................................. 174 SRIO Peripheral Block Diagram .......................................................................................... 205 Operation Sequence ....................................................................................................... 216 1x/4x RapidIO Packet Data Stream (Streaming-Write Class) ........................................................ 227 Serial RapidIO Control Symbol Format.................................................................................. 228 SRIO Conceptual Block Diagram ........................................................................................ 259 Load/Store Data Transfer Diagram ...................................................................................... 3210 Load/Store Registers for RapidIO (Address Offset: LSU1 0x400-0x418, LSU2 0x420-0x438, LSU30x440-0x458, LSU4 0x460-0x478) ....................................................................................... 3311 LSU Registers Timing ..................................................................................................... 3512 Example Burst NWRITE_R ............................................................................................... 3613 Load/Store Module Data Flow ............................................................................................ 3714 CPPI RX Scheme for RapidIO ............................................................................................ 4115 Message Request Packet ................................................................................................. 4116 Queue Mapping Table (Address Offset: 0x0800 - 0x08FC) .......................................................... 4217 Queue Mapping Register RXU_MAP_L n............................................................................... 4318 Queue Mapping Register RXU_MAP_H n............................................................................... 4319 RX Buffer Descriptor Fields ............................................................................................... 4420 RX CPPI Mode Explanation .............................................................................................. 4721 CPPI Boundary Diagram .................................................................................................. 4822 TX Buffer Descriptor Fields ............................................................................................... 4923 Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) .............................. 5224 RX Buffer Descriptor ....................................................................................................... 5725 TX Buffer Descriptor ....................................................................................................... 5826 Doorbell Operation ......................................................................................................... 5927 Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) ............................................ 6128 Transmit Source Flow Control Masks ................................................................................... 6229 Configuration Bus Example ............................................................................................... 6330 DMA Example .............................................................................................................. 6431 GBL_EN (Address 0x0030) ............................................................................................... 6532 GBL_EN_STAT (Address 0x0034) ....................................................................................... 6533 BLK0_EN (Address 0x0038) .............................................................................................. 6534 BLK0_EN_STAT (Address 0x003C) ..................................................................................... 6635 BLK1_EN (Address 0x0040) .............................................................................................. 6636 BLK1_EN_STAT (Address 0x0044) ..................................................................................... 6637 BLK8_EN (Address 0x0078) .............................................................................................. 6638 BLK8_EN_STAT (Address 0x007C) ..................................................................................... 6639 Emulation Control (Peripheral Control Register PCR 0x0004) ....................................................... 6840 Bootload Operation ........................................................................................................ 7241 Detectable Errors ........................................................................................................... 7342 RapidIO DOORBELL Packet for Interrupt Use ......................................................................... 7443 DOORBELL0 Interrupt Registers for Direct I/O Transfers ............................................................ 7644 DOORBELL1 Interrupt Registers for Direct I/O Transfers ............................................................ 7645 DOORBELL2 Interrupt Registers for Direct I/O Transfers ............................................................ 7746 DOORBELL3 Interrupt Registers for Direct I/O Transfers ............................................................ 7747 RX_CPPI Interrupts Using Messaging Mode Data Transfers ........................................................ 7848 TX _CPPI Interrupts Using Messaging Mode Data Transfers ........................................................ 7849 LSU Load/Store Module Interrupts ....................................................................................... 7950 ERR_RST_EVNT Error, Reset, and Special Event Interrupt ......................................................... 8051 Doorbell 0 Interrupt Condition Routing Registers ...................................................................... 81
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52 Load/Store Module Interrupt Condition Routing Registers ............................................................ 8253 Error, Reset, and Special Event Interrupt Condition Routing Registers ............................................ 8354 Sharing of ISDR Bits ....................................................................................................... 8455 Example Diagram of Interrupt Status Decode Register Mapping .................................................... 8456 INTDST n_Decode Interrupt Status Decode Register ................................................................. 8557 INTDST n_RATE_CNTL Interrupt Rate Control Register .............................................................. 8658 Peripheral ID Register (PID) .............................................................................................. 9959 Peripheral Control Register (PCR) ..................................................................................... 10060 Peripheral Settings Control Register (PER_SET_CNTL) ............................................................ 10161 Peripheral Global Enable Register (GBL_EN) ........................................................................ 10462 Peripheral Global Enable Status Register (GBL_EN_STAT) ....................................................... 10563 Block nEnable Register (BLK n_EN) ................................................................................... 10664 Block nEnable Status Register (BLK n_EN_STAT) .................................................................. 10765 RapidIO DEVICEID1 Register (DEVICEID_REG1) .................................................................. 10866 RapidIO DEVICEID2 Register (DEVICEID_REG2) .................................................................. 10967 Packet Forwarding Register nfor 16b DeviceIDs (PF_16B_CNTL n).............................................. 11068 Packet Forwarding Register nfor 8b DeviceIDs (PF_8B_CNTL n)................................................. 11169 SERDES Receive Channel Configuration Registers n(SERDES_CFGRX n_CNTL) ............................ 11270 SERDES Transmit Channel Configuration Registers n(SERDES_CFGTX n_CNTL) ........................... 11471 SERDES Macros CFG (0-3) Registers (SERDES_CFG n_CNTL) ................................................. 11672 DOORBELL nInterrupt Status Register (DOORBELL n_ICSR) ..................................................... 11773 DOORBELL nInterrupt Clear Register (DOORBELL n_ICCR) ...................................................... 11874 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ............................................................... 11975 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ................................................................ 12076 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) ................................................................ 12177 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) ................................................................. 12278 LSU Status Interrupt Register (LSU_ICSR) ........................................................................... 12379 LSU Clear Interrupt Register (LSU _ICCR) ........................................................................... 12480 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) .......................... 12581 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) ........................... 12682 DOORBELL nInterrupt Condition Routing Register (DOORBELL n_ICRR) ....................................... 12783 DOORBELL nInterrupt Condition Routing Register 2 (DOORBELL n_ICRR2) ................................... 12884 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) ................................................ 12985 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) ............................................... 13086 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) ................................................. 13187 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) ............................................... 13288 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) ................................................ 13389 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) ................................................ 13490 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) ................................................ 13591 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) ................................................ 13692 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) ............ 13793 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) ........ 13894 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) ........ 13995 INTDST nInterrupt Status Decode Registers (INTDST n_DECODE)............................................... 14096 INTDST nInterrupt Rate Control Registers (INTDST n_RATE_CNTL) ............................................. 14197 LSU nControl Register 0 (LSU n_REG0) ............................................................................... 14298 LSU nControl Register 1 (LSU n_REG1) ............................................................................... 14399 LSU nControl Register 2 (LSU n_REG2) ............................................................................... 144100 LSU nControl Register 3 (LSU n_REG3) ............................................................................... 145101 LSU nControl Register 4 (LSU n_REG4) ............................................................................... 146102 LSU nControl Register 5 (LSU n_REG5) ............................................................................... 147103 LSU nControl Register 6 (LSU n_REG6) ............................................................................... 148104 LSU Congestion Control Flow Mask n(LSU_FLOW_MASKS n)................................................... 149
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105 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) .......................... 150106 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) .................................. 151107 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) ........................... 152108 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) ................................... 153109 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) ............................................... 154110 Transmit CPPI Supported Flow Mask Registers n(TX_CPPI_FLOW_MASKS n)................................ 155111 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) ................................................ 157112 Receive CPPI Control Register (RX_CPPI_CNTL) .................................................................. 158113 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) .............................. 159114 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) .............................. 160115 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) .............................. 161116 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) .............................. 162117 Mailbox-to-Queue Mapping Register L n(RXU_MAP_L n)........................................................... 163118 Mailbox-to-Queue Mapping Register H n(RXU_MAP_H n).......................................................... 164119 Flow Control Table Entry Registers (FLOW_CNTL n)................................................................ 165120 Device Identity CAR (DEV_ID) .......................................................................................... 166121 Device Information CAR (DEV_INFO) ................................................................................. 167122 Assembly Identity CAR (ASBLY_ID) ................................................................................... 168123 Assembly Information CAR (ASBLY_INFO)........................................................................... 169124 Processing Element Features CAR (PE_FEAT) ...................................................................... 170125 Source Operations CAR (SRC_OP).................................................................................... 171126 Destination Operations CAR (DEST_OP) ............................................................................. 172127 Processing Element Logical Layer Control CSR (PE_LL_CTL) .................................................... 173128 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ............................................ 174129 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) .............................................. 175130 Base Device ID CSR (BASE_ID) ....................................................................................... 176131 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) ........................................................ 177132 Component Tag CSR (COMP_TAG) ................................................................................... 178133 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) ..................................... 179134 Port Link Time-Out Control CSR (SP_LT_CTL) ...................................................................... 180135 Port Response Time-Out Control CSR (SP_RT_CTL) .............................................................. 181136 Port General Control CSR (SP_GEN_CTL) ........................................................................... 182137 Port Link Maintenance Request CSR n(SP n_LM_REQ) ........................................................... 183138 Port Link Maintenance Response CSR n(SP n_LM_RESP) ........................................................ 184139 Port Local AckID Status CSR n(SP n_ACKID_STAT) ............................................................... 185140 Port Error and Status CSR n(SP n_ERR_STAT) ..................................................................... 186141 Port Control CSR n(SP n_CTL) ......................................................................................... 188142 Error Reporting Block Header (ERR_RPT_BH) ...................................................................... 190143 Logical/Transport Layer Error Detect CSR (ERR_DET) ............................................................. 191144 Logical/Transport Layer Error Enable CSR (ERR_EN) .............................................................. 192145 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT).......................................... 193146 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) ................................................... 194147 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) ...................................................... 195148 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ..................................................... 196149 Port-Write Target Device ID CSR (PW_TGT_ID) .................................................................... 197150 Port Error Detect CSR n(SP n_ERR_DET) ........................................................................... 198151 Port Error Rate Enable CSR n(SP n_RATE_EN) .................................................................... 199152 Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) ........................................ 200153 Port nPacket/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) ................................ 201154 Port nPacket/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) ................................ 202155 Port nPacket/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) ................................ 203156 Port nPacket/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) ................................ 204157 Port Error Rate CSR n(SP n_ERR_RATE) ............................................................................ 205
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158 Port Error Rate Threshold CSR n(SP n_ERR_THRESH) ........................................................... 206159 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) .............................................. 207160 Port IP Mode CSR (SP_IP_MODE) .................................................................................... 208161 Serial Port IP Prescalar (IP_PRESCAL) ............................................................................... 210162 Port-Write-In Capture CSR n(SP_IP_PW_IN_CAPT n)............................................................. 211163 Port Reset Option CSR n(SP n_RST_OPT) .......................................................................... 212164 Port Control Independent Register n(SP n_CTL_INDEP) ........................................................... 213165 Port Silence Timer n(SP n_SILENCE_TIMER) ....................................................................... 215166 Port Multicast-Event Control Symbol Request Register n(SP n_MULT_EVNT_CS) ............................ 216167 Port Control Symbol Transmit n(SP n_CS_TX) ...................................................................... 217
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List of Tables
1RapidIO Documents and Links ........................................................................................... 182 Packet Type ................................................................................................................. 233 Pin Description .............................................................................................................. 244 Bits of SERDES_CFG n_CNTL Register (0x120 - 0x12c) ............................................................. 265 Line Rate versus PLL Output Clock Frequency ........................................................................ 276 RATE Bit Effects ............................................................................................................ 277 Frequency Range versus MPY ........................................................................................... 288 Bits of SERDES_CFGRX n_CNTL Registers ........................................................................... 289 EQ Bits ....................................................................................................................... 3010 Bits of SERDES_CFGTX n_CNTL Registers ........................................................................... 3011 SWING Bits ................................................................................................................. 3112 DE Bits ....................................................................................................................... 3113 Control/Command Register Field Mapping ............................................................................. 3314 Status Fields ................................................................................................................ 3415 RX DMA State Head Descriptor Pointer (HDP) (Address Offset 0x600-0x63C) ................................... 4316 RX DMA State Completion Pointer (CP) (Address Offset 0x600-0x63C) ........................................... 4317 RX Buffer Descriptor Field Descriptions ................................................................................. 4518 TX DMA State Head Descriptor Pointer (HDP) (Address Offset 0x500 – 0x53C) ................................. 4919 TX DMA State Completion Pointer (CP) (Address Offset 0x580 – 0x5BC) ........................................ 4920 TX Buffer Descriptor Field Definitions ................................................................................... 4921 Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC) .............................. 5222 Flow Control Table Entry Registers (Address Offset 0x0900 - 0x093C) ............................................ 6123 Transmit Source Flow Control Masks ................................................................................... 6224 Enable and Enable Status Bit Field Descriptions ...................................................................... 6625 Emulation Control Signals ................................................................................................. 6926 Interrupt Source Configuration Options ................................................................................. 7627 Interrupt Condition Routing Options ..................................................................................... 8128 Serial Rapid IO (SRIO) Registers ........................................................................................ 8829 Peripheral ID Register (PID) Field Descriptions ........................................................................ 9930 Peripheral Control Register (PCR) Field Descriptions ............................................................... 10031 Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions ..................................... 10132 Peripheral Global Enable Register (GBL_EN) Field Descriptions .................................................. 10433 Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions ................................. 10534 Block nEnable Register (BLK n_EN) Field Descriptions ............................................................. 10635 Block nEnable Status Register (BLK n_EN_STAT) Field Descriptions ............................................ 10736 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................ 10837 RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................ 10938 Packet Forwarding Register nfor 16b DeviceIDs (PF_16B_CNTL n) Field Descriptions ....................... 11039 Packet Forwarding Register nfor 8b DeviceIDs (PF_8B_CNTL n) Field Descriptions .......................... 11140 SERDES Receive Channel Configuration Registers n(SERDES_CFGRX n_CNTL) Field Descriptions ..... 11241 EQ Bits ..................................................................................................................... 11342 SERDES Transmit Channel Configuration Registers n(SERDES_CFGTX n_CNTL) Field Descriptions ..... 11443 SWING Bits ................................................................................................................ 11544 DE Bits ..................................................................................................................... 11545 SERDES Macros CFG (0-3) Registers (SERDES_CFG n_CNTL) Field Descriptions ........................... 11646 DOORBELL nInterrupt Status Register (DOORBELL n_ICSR) Field Descriptions ............................... 11747 DOORBELL nInterrupt Clear Register (DOORBELL n_ICCR) Field Descriptions ................................ 11848 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Field Descriptions ......................................... 11949 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Field Descriptions .......................................... 120
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50 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions ......................................... 12151 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions .......................................... 12252 LSU Status Interrupt Register (LSU_ICSR) Field Descriptions ..................................................... 12353 LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions ..................................................... 12454 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) Field Descriptions .... 12555 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) Field Descriptions ..... 12656 DOORBELL nInterrupt Condition Routing Register (DOORBELL n_ICRR) Field Descriptions ................. 12757 DOORBELL nInterrupt Condition Routing Register 2 (DOORBELL n_ICRR2) Field Descriptions ............. 12858 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Field Descriptions .......................... 12959 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Field Descriptions ......................... 13060 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Field Descriptions ........................... 13161 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Field Descriptions ......................... 13262 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Field Descriptions ......................... 13363 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Field Descriptions ......................... 13464 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Field Descriptions ......................... 13565 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Field Descriptions ......................... 13666 Error, Reset, and Special Event Interrupt Condition Routing Register (ERR_RST_EVNT_ICRR) FieldDescriptions ............................................................................................................... 13767 Error, Reset, and Special Event Interrupt Condition Routing Register 2 (ERR_RST_EVNT_ICRR2) FieldDescriptions ............................................................................................................... 13868 Error, Reset, and Special Event Interrupt Condition Routing Register 3 (ERR_RST_EVNT_ICRR3) FieldDescriptions ............................................................................................................... 13969 INTDST nInterrupt Status Decode Registers (INTDST n_DECODE) Field Descriptions ........................ 14070 INTDST nInterrupt Rate Control Registers (INTDST n_RATE_CNTL) Field Descriptions ....................... 14171 LSU nControl Register 0 (LSU n_REG0) Field Descriptions ........................................................ 14272 LSU nControl Register 1 (LSU n_REG1) Field Descriptions ........................................................ 14373 LSU nControl Register 2 (LSU n_REG2) Field Descriptions ........................................................ 14474 LSU nControl Register 3 (LSU n_REG3) Field Descriptions ........................................................ 14575 LSU nControl Register 4 (LSU n_REG4) Field Descriptions ........................................................ 14676 LSU nControl Register 5 (LSU n_REG5) Field Descriptions ........................................................ 14777 LSU nControl Register 6 (LSU n_REG6) Field Descriptions ........................................................ 14878 LSU Congestion Control Flow Mask n(LSU_FLOW_MASKS n) Field Descriptions ............................ 14979 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP) Field Descriptions .... 15080 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) Field Descriptions ............ 15181 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP) Field Descriptions .... 15282 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP) Field Descriptions ............ 15383 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 15484 Transmit CPPI Supported Flow Mask Registers n(TX_CPPI_FLOW_MASKS n) Field Descriptions ......... 15685 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions ......................... 15786 Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions ............................................ 15887 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) Field Descriptions ........ 15988 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) Field Descriptions ........ 16089 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) Field Descriptions ........ 16190 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) Field Descriptions ........ 16291 Mailbox-to-Queue Mapping Register L n(RXU_MAP_L n) Field Descriptions ..................................... 16392 Mailbox-to-Queue Mapping Register H n(RXU_MAP_H n) Field Descriptions .................................... 16493 Flow Control Table Entry Registers (FLOW_CNTL n) Field Descriptions ......................................... 16594 Device Identity CAR (DEV_ID) Field Descriptions ................................................................... 16695 Device Information CAR (DEV_INFO) Field Descriptions ........................................................... 16796 Assembly Identity CAR (ASBLY_ID) Field Descriptions ............................................................. 16897 Assembly Information CAR (ASBLY_INFO) Field Descriptions .................................................... 16998 Processing Element Features CAR (PE_FEAT) Field Descriptions ............................................... 170
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99 Source Operations CAR (SRC_OP) Field Descriptions ............................................................. 171100 Destination Operations CAR (DEST_OP) Field Descriptions ....................................................... 172101 Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions .............................. 173102 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions ...................... 174103 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions ........................ 175104 Base Device ID CSR (BASE_ID) Field Descriptions ................................................................. 176105 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) Field Descriptions .................................. 177106 Component Tag CSR (COMP_TAG) Field Descriptions ............................................................ 178107 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Field Descriptions .............. 179108 Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions ................................................. 180109 Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions ........................................ 181110 Port General Control CSR (SP_GEN_CTL) Field Descriptions .................................................... 182111 Port Link Maintenance Request CSR n(SP n_LM_REQ) Field Descriptions ..................................... 183112 Port Link Maintenance Response CSR n(SP n_LM_RESP) Field Descriptions ................................. 184113 Port Local AckID Status CSR n(SP n_ACKID_STAT) Field Descriptions ......................................... 185114 Port Error and Status CSR n(SP n_ERR_STAT) Field Descriptions .............................................. 186115 Port Control CSR n(SP n_CTL) Field Descriptions .................................................................. 188116 Error Reporting Block Header (ERR_RPT_BH) Field Descriptions ................................................ 190117 Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... 191118 Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions ....................................... 192119 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions ................... 193120 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions ............................. 194121 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions ................................ 195122 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions ............................... 196123 Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions .............................................. 197124 Port Error Detect CSR n(SP n_ERR_DET) Field Descriptions ..................................................... 198125 Port Error Rate Enable CSR n(SP n_RATE_EN) Field Descriptions .............................................. 199126 Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) Field Descriptions ................. 200127 Port nPacket/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) Field Descriptions .......... 201128 Port nPacket/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) Field Descriptions .......... 202129 Port nPacket/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) Field Descriptions .......... 203130 Port nPacket/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) Field Descriptions .......... 204131 Port Error Rate CSR n(SP n_ERR_RATE) Field Descriptions ..................................................... 205132 Port Error Rate Threshold CSR n(SP n_ERR_THRESH) Field Descriptions ..................................... 206133 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Field Descriptions ........................ 207134 Port IP Mode CSR (SP_IP_MODE) Field Descriptions .............................................................. 208135 Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions ........................................................ 210136 Port-Write-In Capture CSR n(SP_IP_PW_IN_CAPT n) Field Descriptions ....................................... 211137 Port Reset Option CSR n(SP n_RST_OPT) Field Descriptions .................................................... 212138 Port Control Independent Register n(SP n_CTL_INDEP) Field Descriptions .................................... 213139 Port Silence Timer n(SP n_SILENCE_TIMER) Field Descriptions ................................................. 215140 Port Multicast-Event Control Symbol Request Register n(SP n_MULT_EVNT_CS) Field Descriptions ...... 216141 Port Control Symbol Transmit n(SP n_CS_TX) Field Descriptions ................................................ 217
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PrefaceSPRU976 – March 2006
Read This First
About This Manual
This document describes the Serial Rapid IO (SRIO) on the TMS320C645x devices.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.•The term "word" describes a 32-bit value. The term "halfword" describes a 16-bit value.
Related Documentation From Texas InstrumentsThe following documents describe the C6000™ devices and related support tools. Copies of thesedocuments are available on the Internet at www.ti.com. Tip: Enter the literature number in the search boxprovided at www.ti.com .
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189 ) gives anintroduction to the TMS320C62x™ and TMS320C67x™ DSPs, development tools, and third-party support.
TMS320C6455 Technical Reference (literature number SPRU965 ) gives an introduction to theTMS320C6455™ DSP and discusses the application areas that are enhanced.
TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C andassembly code for the TMS320C6000™ DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the CodeComposer Studio™ integrated development environment and software tools.
Code Composer Studio Application Programming Interface Reference Guide (literature numberSPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allowsyou to program custom plug-ins for Code Composer.
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes theTMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal directmemory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,bandwidth management, and the memory and cache.
TMS320C645x DSP Peripherals Overview Reference Guide (literature number SPRUE52 ) provides abrief description of the peripherals available on the TMS320C645x digital signal processors (DSPs).
TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234 ) is a download with the latestchip support libraries.Trademarks
C6000, TMS320C62x, TMS320C67x, TMS320C6455, TMS320C6000, Code Composer Studio, RapidIOare trademarks of Texas Instruments.
InfiniBand is a trademark of the InfiniBand Trade Association.
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1 Overview
1.1 General RapidIO System
User's GuideSPRU976 – March 2006
Serial RapidIO (SRIO)
The RapidIO peripheral used in the TMS320C645x is called a serial RapidIO (SRIO). This chapterdescribes the general operation of a RapidIO system, how this module is connected to the outside world,the definitions of terms used within this document, and the features supported and not supported forSRIO.
RapidIO™ is a non-proprietary high-bandwidth system level interconnect. It is a packet-switchedinterconnect intended primarily as an intra-system interface for chip-to-chip and board-to-boardcommunications at Gigabyte-per-second performance levels. Uses for the architecture can be found inconnected microprocessors, memory, and memory mapped I/O devices that operate in networkingequipment, memory subsystems, and general purpose computing. Principle features of RapidIO include:•Flexible system architecture allowing peer-to-peer communication•Robust communication with error detection features•Frequency and port width scalability•Operation that is not software intensive•High bandwidth interconnect with low overhead•Low pin count•Low power•Low latency
1.1.1 RapidIO Architectural Hierarchy
RapidIO is defined as a 3-layer architectural hierarchy.•Logical layer: Specifies the protocols, including packet formats, which are needed by endpoints toprocess transactions•Transport layer: Defines addressing schemes to correctly route information packets within a system•Physical layer: Contains the device level interface information such as the electrical characteristics,error management data, and basic flow control data
In the RapidIO architecture, a single specification for the transport layer is compatible with differingspecifications for the logical and physical layers (see Figure 1 ).
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Globally
shared
memory spec
logical
Future
Message
passingsystem
I/O
Logical specification
Information necessary for the end point
to process the transaction (i.e., transaction
type, size, physical address)
to end in the system (i.e., routing address)
Information to transport packet from end
Transport specification
spec
transport
Common
between two physical devices (i.e., electrical
Information necessary to move packet
interface, flow control)
Physical specification
1x/4x
LP serialLP-LVDS
8/16 Future
spec
physical
checklist
Compliance
Inter-
operability
specification
Overview
Figure 1. RapidIO Architectural Hierarchy
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Host Subsystem I/O Control Subsystem
DSP Farm
TDM,GMII, Utopia
Communications Subsystem PCI Subsystem
InfiniBand HCA™
To System Area
Network
Memory
Memory Memory
Memory
RapidIO RapidIO RapidIO
RapidIO
RapidIO
Backplane
PCI
RapidIO
RapidIO
RapidIO
RapidIO
Switch
Control
Processor
IO
Processor
RapidIO to
InfiniBand
RapidIO
Switch
RapidIO
Switch
Legacy
Comm
Processor
RapidIO
Switch
RapidIO to
PCI Bridge
ASIC/FPGA
Memory Memory
Host
Processor
Host
Processor
DSP DSP DSP DSP
Comm
Processor
Overview
1.1.2 RapidIO Interconnect Architecture
The interconnect architecture is defined as a packet switched protocol independent of a physical layerimplementation. Figure 2 illustrates the interconnection system.
Figure 2. RapidIO Interconnect Architecture
(1) InfiniBand™ is a trademark of the InfiniBand Trade Association.
1.1.3 1x/4x LP-Serial
Currently, there are two physical layer specifications recognized by the RapidIO Trade Association: 8/16LP-LVDS and 1X/4X LP-Serial. The 8/16 LP-LVDS specification is a point-to-point synchronous clocksourcing DDR interface. The 1X/4X LP-Serial specification is a point-to-point, AC coupled, clock recoveryinterface. The two physical layer specifications are not compatible.
SRIO complies with the 1X/4X LP-Serial specification. The serializer/deserializer (SERDES) technology inSRIO also aligns with that specification.
The 1X/4X LP-Serial specification currently covers three frequency points: 1.25, 2.5, and 3.125 Gbps. Thisdefines the total bandwidth of each differential pair of I/O signals. An 8b/10b encoding scheme ensuresample data transitions for the clock recovery circuits. Due to the 8b/10b encoding overhead, the effectivedata bandwidth per differential pair is 1.0, 2.0, and 2.5 Gbps respectively. Serial RapidIO only specifiesthese rates for both the 1X and 4X ports. A 1X port is defined as 1 TX and 1 RX differential pair. A 4X portis a combination of four of these pairs. This document describes a 4X RapidIO port that can also beconfigured as four 1X ports, thus providing a scalable interface capable of supporting a data bandwidth of1 to 10 Gbps.
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Serial RapidIO 1x Device to 1x Device Interface Diagram
Serial RapidIO 4x Device to 4x Device Interface Diagram
1x Device
TD[0]
TD[0]
RD[0]
RD[0] TD[0]
TD[0]
1x Device
RD[0]
RD[0]
RD[0-3]
RD[0-3]
4x Device
TD[0-3]
RD[0-3]
RD[0-3]
TD[0-3]
4x Device
TD[0-3]
TD[0-3]
1.2 RapidIO Feature Support in SRIO
Overview
Figure 3. Serial RapidIO Device to Device Interface Diagrams
Features Supported in SRIO:•RapidIO Interconnect Specification V1.2 compliance, Errata 1.2•LP-Serial Specification V1.2 compliance•4X Serial RapidIO with auto-negotiation to 1X port, optional operation for four 1X ports•Integrated clock recovery with TI SERDES•Hardware error handling including Cyclic Redundancy Code (CRC)•Differential CML signaling supporting AC and DC coupling•Support for 1.25, 2.5, and 3.125 Gbps rates•Power-down option for unused ports•Read, write, write with response, streaming write, outgoing Atomic, and maintenance operations•Generates interrupts to the CPU (Doorbell packets and internal scheduling)•Support for 8b and 16b device ID•Support for receiving 34b addresses•Support for generating 34b, 50b, and 66b addresses•Support for the following data sizes: byte, half-word, word, double-word•Big endian data transfers•Direct IO transfers•Message passing transfers•Data payloads of up to 256B•Single messages consisting of up to 16 packets•Elastic storage FIFOs for clock domain handoff•Short run and long run compliance•Support for Error Management Extensions•Support for Congestion Control Extensions•Support for one multi-cast ID
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1.3 Standards
1.4 External Devices Requirements
Overview
Features Not Supported:•Compliance with the Global Shared Memory specification (GSM)•8/16 LP-LVDS compatible•Destination support of RapidIO Atomic Operations•Simultaneous mixing of frequencies between 1X ports (all ports must be the same frequency)•Target atomic operations (including increment, decrement, test-and-swap, set, and clear) for internalL2 memory and registers
The SRIO peripheral is compliant to V1.2 of the RapidIO Interconnect Specification and V1.2 of theLP-Serial specification.
Table 1. RapidIO Documents and Links
Document Link Description
Official RapidIO Web Site http://www.RapidIO.org Various associated docs
SRIO provides a seamless interface to all devices which are compliant to V1.2 of the LP-Serial RapidIOspecification. This includes ASIC, microprocessor, DSP, and switch fabric devices from multiple vendors.Compliance to the specification can be verified with bus-functional models available through the RapidIOTrade Association, as well as test suites currently available for licensing.
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2 SRIO Functional Description
2.1 Overview
SRIO Functional Description
2.1.1 Peripheral Data Flow
This peripheral is designed to be an external slave module that is capable of mastering the internal DMA.This means that an external device can push (burst write) data to the DSP as needed, without having togenerate an interrupt to the CPU. This has two benefits. It cuts down on the total number of interrupts, andit reduces handshaking (latency) associated with read-only peripherals.
SRIO specifies data packets with payloads up to 256 bytes. Many times, transactions will span acrossmultiple packets. RapidIO specifies a maximum of 16 transactions per message. Although a request isgenerated for each packet transaction so that the DMA can transfer the data to L2 memory, an interrupt isonly generated after the final packet of the message. This interrupt notifies the CPU that data is availablein L2 Memory for processing.
As an endpoint device, the peripheral accepts packets based on the destination ID. Two options exist forpacket acceptance and are mode selectable. The first option is to only accept packets whose DestIDsmatch the local deviceID in 0x0080. This provides a level of security. The second option is to acceptincoming packets matching the deviceID in either 0x0080 or 0x0084. This allows for system multicastoperations.
Data flow through the peripheral can be explained using the high-level block diagram shown in Figure 4 .High-speed data enters from the device pins into the RX block of the SERDES macro. The RX block is adifferential receiver expecting a minimum of 175mV peak-to-peak differential input voltage (Vid). Levelshifting is performed in the RX block, such that the output is single ended CMOS. The serial data is thenfed to the SERDES clock recovery block. The sole purpose of this block is to extract a clock signal fromthe data stream. To do this, a low-frequency reference clock is required, 1/10
th
or ½0
th
the data rate. Forexample, for 3.125 Gbps data, a reference clock of 312.5Mhz or 156.25Mhz is needed. Typically, thisclock comes from an off-chip stable crystal oscillator and is a LVDS device input separate to the SERDES.This clock is distributed to the SERDES PLL block which multiplies that frequency up to that of the datarate. Eight phases of this high-speed clock are created and routed to the clock recovery blocks. The clockrecovery block further interpolates eight times between these clock phases. This provides clock edgeresolution of 1/96
th
the Unit Interval (UI). The clock recovery block samples the incoming data andmonitors the relative positions of the data edges. With this information, it can provide the data and acenter-aligned clock to the S2P block. The S2P block uses the newly recovered clock to demux the datainto 10-bit words. At this point, the data leaves the SERDES macro at 1/10th the pin data rate,accompanied by an aligned byte clock.
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1.25-3.125 Gbps
differential data
Rx Clock
recovery S2P
10b
Clk 8b/10b
decode 8b
Clock
recovery
Rx 8b8b/10b
decode
10b
ClkS2P
Clock
recovery
Rx 8b8b/10b
decode
10b
ClkS2P
Clock
recovery
Rx 8b8b/10b
decode
10b
ClkS2P
PLL
Tx
Tx
Tx
Tx
P2S
P2S
P2S
P2S
8b
8b
8b
8b
10b 8b/10b
coding
Clk
8b/10b
coding
8b/10b
coding
8b/10b
coding
10b
Clk
10b
Clk
10b
Clk
FIFO
FIFO
FIFO
FIFO
System
clock
Capability
registers
Control
Command
and status
registers
SERDES
Clock domain 2 Clock domain 3
Clock domain 1
DMA
bus
Packet Generation
Lane striping
Lane de-skew
CRC error detection
CRC generation
Buffering address and data handoff
FIFO
FIFO
FIFO
FIFO
SRIO Functional Description
Figure 4. SRIO Peripheral Block Diagram
Within the physical layer, the data next goes to the 8b/10b decode block. 8b/10b encoding is used byRapidIO to ensure adequate data transitions for the clock recovery circuits. Here the 20% encodingoverhead is removed as the 10-bit data is decoded to the raw 8-bit data. At this point, the recovered byteclock is still being used.
The next step is clock synchronization and data alignment. These functions are handled by the FIFO andlane de-skewing blocks. The FIFO provides an elastic store mechanism used to hand off between therecovered clock domains and a common system clock. After the FIFO, the four lanes are synchronized infrequency and phase, whether 1X or 4X mode is being used. The FIFO is 8 words deep. The lanede-skew is only meaningful in the 4X mode, where it aligns each channel’s word boundaries, such that theresulting 32-bit word is correctly aligned.
The CRC error detection block keeps a running tally of the incoming data and computes the expectedCRC value for the 1X or 4X mode. The expected value is compared against the CRC value at the end ofthe received packet.
After the packet reaches the logical layer, the packet fields are decoded and the payload is buffered.Depending on the type of received packet, the packet routing is handled by functional blocks which controlthe DMA access.
2.1.2 SRIO Packets
The SRIO data stream consists of data fields pertaining to the logical layer, the transport layer, and thephysical layer.•The logical layer consists of the header (defining the type of access) and the payload (if present).•The transport layer is partially dependent on the physical topology in the system, and consists ofsource and destination IDs for the sending and receiving devices.•The physical layer is dependent on the physical interface (i.e., serial versus parallel RapidIO) andincludes priority, acknowledgment, and error checking fields.
2.1.2.1 Operation Sequence
SRIO transactions are based on request and response packets. Packets are the communication elementbetween endpoint devices in the system. A master or initiator generates a request packet which istransmitted to a target. The target then generates a response packet back to the initiator to complete thetransaction.
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