Texas Instruments TRF7960 User manual

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TRF7960, TRF7961
SLOU186G –AUGUST 2006–REVISED MAY 2017
TRF7960, TRF7961 Multiple-Standard Fully Integrated 13.56-MHz RFID
Analog Front End and Data-Framing Reader System
1 Device Overview
1
1.1 Features
1
• Completely Integrated Protocol Handling
• Separate Internal High-PSRR Power Supplies for
Analog, Digital, and PA Sections Provide Noise
Isolation for Superior Read Range and Reliability
• Dual Receiver Inputs With AM and PM
Demodulation to Minimize Communication Holes
• Receiver AM and PM RSSI
• Reader-to-Reader Anticollision
• High Integration Reduces Total BOM and Board
Area
– Single External 13.56-MHz Crystal Oscillator
– MCU-Selectable Clock-Frequency Output of RF,
RF/2, or RF/4
– Adjustable 20-mA High-PSRR LDO for
Powering External MCU
• Easy to Use With High Flexibility
– Automatically Configured Default Modes for
Each Supported ISO Protocol
– 12 User-Programmable Registers
– Selectable Receiver Gain
– Programmable Output Power (100 mW or
200 mW)
– Adjustable ASK Modulation Range (8% to 30%)
– Built-In Receiver Band-Pass Filter With User-
Selectable Corner Frequencies
• Wide Operating Voltage Range of 2.7 V to 5.5 V
• Ultra-Low-Power Modes
– Power Down: <1 µA
– Standby: 120 µA
– Active (RX Only): 10 mA
• Parallel 8-Bit or Serial 4-Pin Serial Peripheral
Interface (SPI) With MCU Using 12-Byte FIFO
• Ultra-Small 32-Pin QFN Package (5 mm × 5 mm)
• Available Tools (Also See Tools and Software)
– Reference Design and EVM With Development
Software
– Source Code Available for MSP430™ MCU
1.2 Applications
• Secure Access Control
• Product Authentication • Medical Systems • Public Transport or Event Ticketing
1.3 Description
The TRF7960 and TRF7961 devices are integrated analog front end and data-framing systems for a
13.56-MHz RFID reader system that supports multiple protocols including ISO/IEC 14443 A and B,
FeliCa™, and ISO/IEC 15693. Built-in programming options make it suitable for a wide range of
applications for proximity and vicinity identification systems.
The reader is configured by selecting the desired protocol in the control registers. Direct access to all
control registers allows fine-tuning of various reader parameters as needed.
The device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO
protocols onboard. Other standards and even custom protocols can be implemented by using one of the
direct modes that the device offers. These direct modes let the application fully control the AFE and also
gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the
associated (extracted) clock signal.
The receiver system has a dual-input receiver architecture to maximize communication robustness. The
receivers also include various automatic and manual gain control options. The received signal strength
from transponders, ambient sources, or internal levels is available in the RSSI register.
A SPI or parallel interface can be used for the communication between the MCU and the TRF796x reader.
When the built-in hardware encoders and decoders are used, transmit and receive functions use a 12-byte
FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the
MCU can process the data in real time.

3 (SPI) or 8 (Parallel)
Impedance
Matching
Circuit
TX_OUT
RX_IN1
RX_IN2
VDD_X
VDD_I/O
SYS_CLK
DATA_CLK
VCC
TRF796x MSP430 MCU
Crystal
13.56 MHz
IRQ
OSC_IN
OSC_OUT
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Device Overview Copyright © 2006–2017, Texas Instruments Incorporated
The TRF7960 and TRF7961 devices support a wide supply voltage range of 2.7 V to 5.5 V and data
communication levels from 1.8 V to 5.5 V for the MCU I/O interface.
The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm)
equivalent into a 50-Ωload when using a 5-V supply and supports OOK and ASK modulation with
selectable modulation depth.
Built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional
external circuits within the reader system.
Start evaluating the TRF7960 multiprotocol transceiver IC with the TRF7960AEVM or the TRF7960ATB.
Documentation,Tools, Reference Designs, and Software,Samples
(1) For more information, see Section 9,Mechanical, Packaging, and
Orderable Information.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
TRF7960RHB VQFN (32) 5 mm × 5 mm
TRF7961RHB VQFN (32) 5 mm × 5 mm
1.4 Typical Application
Figure 1-1 shows a typical application block diagram.
Figure 1-1. Application Block Diagram

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Table of ContentsCopyright © 2006–2017, Texas Instruments Incorporated
Table of Contents
1 Device Overview ......................................... 1
1.1 Features .............................................. 1
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Typical Application ................................... 2
2 Revision History ......................................... 4
3 Device Comparison ..................................... 5
3.1 Related Products ..................................... 5
4 Terminal Configuration and Functions.............. 6
4.1 Pin Diagram .......................................... 6
4.2 Signal Descriptions................................... 6
5 Specifications ............................................ 8
5.1 Absolute Maximum Ratings .......................... 8
5.2 ESD Ratings.......................................... 8
5.3 Recommended Operating Conditions................ 8
5.4 Electrical Characteristics ............................. 8
5.5 Thermal Resistance Characteristics.................. 9
6 Detailed Description ................................... 10
6.1 Overview ............................................ 10
6.2 Power Supplies...................................... 10
6.3 Receiver – Analog Section.......................... 16
6.4 Register Descriptions................................ 22
6.5 Direct Commands From MCU to Reader ........... 31
6.6 Reader Communication Interface ................... 33
6.7 Parallel Interface Communication................... 34
6.8 Serial Interface Communication..................... 36
7 Applications, Implementation, and Layout........ 41
7.1 Application Schematics ............................. 41
8 Device and Documentation Support ............... 43
8.1 Getting Started and Next Steps..................... 43
8.2 Device Nomenclature ............................... 43
8.3 Tools and Software ................................. 44
8.4 Documentation Support............................. 44
8.5 Related Links........................................ 45
8.6 Community Resources.............................. 45
8.7 Trademarks.......................................... 45
8.8 Electrostatic Discharge Caution..................... 45
8.9 Export Control Notice ............................... 45
8.10 Glossary............................................. 45
9 Mechanical, Packaging, and Orderable
Information .............................................. 46

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Revision History Copyright © 2006–2017, Texas Instruments Incorporated
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from August 12, 2010 to May 18, 2017 Page
• Removed "and AGC" from "Selectable Receiver Gain" in Section 1.1,Features ........................................... 1
• Updated list of applications.......................................................................................................... 1
• Changed contents of Section 1.3,Description.................................................................................... 1
• Added Device Information table .................................................................................................... 2
• Added Section 1.4,Typical Application............................................................................................ 2
• Added Section 3,Device Comparison, and moved Table 3-1 to it............................................................. 5
• Added Section 3.1,Related Products ............................................................................................. 5
• Changed the title of Section 4 from Physical Characteristics to Terminal Configuration and Functions.................. 6
• Removed former Section 3.2, Packaging and Ordering Information (see Section 9,Mechanical, Packaging, and
Orderable Information)............................................................................................................... 7
• Updated note (1) on Section 5.1,Absolute Maximum Ratings, to standard wording........................................ 8
• Moved ESD ratings from Absolute Maximum Ratings to Section 5.2,ESD Ratings; changed ratings from positive
voltages only to positive and negative; added notes for HBM and CDM...................................................... 8
• Changed format of MIN, TYP, and MAX columns in Section 5.4,Electrical Characteristics ............................... 8
• Added the fD_CLKmax parameter in Section 5.4,Electrical Characteristics ..................................................... 9
• Changed title of and moved Section 5.5,Thermal Resistance Characteristics .............................................. 9
• Moved contents of Section 6.1,Overview from former Section 2............................................................. 10
• Removed a paragraph that began "The second receiver gain stage and digitizer stage..." in Section 6.3,
Receiver – Analog Section......................................................................................................... 17
• Added the last sentence to the paragraph that begins "The start of the receive operation (successfully received
SOF)..." in Section 6.3.2,Receiver – Digital Section .......................................................................... 18
• Added "and ISO/IEC 15693" to the first sentence of the paragraph that begins "The framing section also
supports bit-collision detection..." in Section 6.3.2,Receiver – Digital Section ............................................. 18
• Changed B2 to Reserved in Table 6-11,Chip Status Control Register (Address = 00h) ................................. 23
• Changed B1 and B0 to Reserved in Table 6-22,RX Special Setting Register (Address = 0Ah) ........................ 28
• Corrected the name of the Reset FIFO command in Table 6-31,Command Codes, and Section 6.5.2,Reset FIFO 31
• Added the last sentence to the paragraph that begins "The serial communications work in the same manner..."
in Section 6.8,Serial Interface Communication................................................................................. 36
• Removed former section External Power Amplifier Application............................................................... 40
• Added Section 7,Applications, Implementation, and Layout, and moved the application schematics to it ............. 41
• Added Section 8,Device and Documentation Support......................................................................... 43
• Added Section 9,Mechanical, Packaging, and Orderable Information ...................................................... 46

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Device ComparisonCopyright © 2006–2017, Texas Instruments Incorporated
3 Device Comparison
Table 3-1 summarizes the device characteristics.
Table 3-1. Device Comparison
DEVICE
PROTOCOLS
ISO/IEC 14443 A AND B ISO/IEC 15693,
ISO/IEC 18000-3 Tag-it™
106 kbps 212 kbps 424 kbps 848 kbps
TRF7960 ✓✓✓✓✓✓
TRF7961 ✓ ✓
3.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Wireless Connectivity Connect more with the broadest wireless connectivity portfolio in
the industry.
Products for NFC / RFID TI provides one of the most differentiated NFC and RFID product portfolios in
the industry and is your solution to meet a broad range of NFC connectivity and RFID
identification needs.
Companion Products for TRF7960 Review products that are frequently purchased or used with this
product.
Reference Designs for TRF7960 The TI Designs Reference Design Library is a robust reference design
library that spans analog, embedded processor, and connectivity. Created by TI experts to
help you jump start your system design, all TI Designs include schematic or block diagrams,
BOMs, and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.

Exposed Thermal Pad
1
8
7
6
5
4
3
2
24
17
18
19
20
21
22
23
VDD_A
RX_IN1
VSS_RX
VSS_RF
TX_OUT
VDD_PA
VDD_RF
VIN
I/O_7
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
RX_IN2
VDD_I/O
VSS_A
MOD
IRQ
ASK/OOK
BAND_GAP
VSS
VDD_X EN2 DATA_CLK SYS_CLK EN VSS_D OSC_OUT OSC_IN
32 31 30 29 28 27 26 25
910 11 12 13 14 15 16
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Terminal Configuration and Functions Copyright © 2006–2017, Texas Instruments Incorporated
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output
4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the pinout of the 32-pin RHB package.
Figure 4-1. 32-Pin RHB Package (Top View)
4.2 Signal Descriptions
Table 4-1 describes the device signals.
Table 4-1. Signal Descriptions
TERMINAL TYPE(1) DESCRIPTION
NAME NO.
VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
VIN 2 SUP External supply input to chip (2.7 V to 5.5 V)
VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4)
VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)
TX_OUT 5 OUT RF output (selectable output power, 100 mW at 8 Ωor 200 mW at 4 Ω, with VDD = 5 V)
VSS_RF 6 SUP Negative supply for PA; normally connected to circuit ground
VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground
RX_IN1 8 INP RX input, used for AM reception
RX_IN2 9 INP RX input, used for PM reception
VSS 10 SUP Chip substrate ground
BAND_GAP 11 OUT Band-gap voltage (1.6 V); internal analog voltage reference; must be AC-bypassed to ground
ASK/OOK 12 BID Also can be configured to provide the received analog signal output (ANA_OUT)
Direct mode, selects either ASK or OOK modulation (0 = ASK, 1 = OOK)
IRQ 13 OUT Interrupt request

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Terminal Configuration and FunctionsCopyright © 2006–2017, Texas Instruments Incorporated
Table 4-1. Signal Descriptions (continued)
TERMINAL TYPE(1) DESCRIPTION
NAME NO.
MOD 14 INP Direct mode, external modulation input
VSS_A 15 SUP Negative supply for internal analog circuits; normally connected to circuit ground
VDD_I/O 16 SUP Supply for I/O communications (1.8 V to 5.5 V). Should be connected to VIN for 5-V
communication, VDD_X for 3.3-V communication, or any other voltage from 1.8 V to 5.5 V.
I/O_0 17 BID I/O pin for parallel communication
I/O_1 18 BID I/O pin for parallel communication
I/O_2 19 BID I/O pin for parallel communication
I/O_3 20 BID I/O pin for parallel communication
I/O_4 21 BID I/O pin for parallel communication
I/O_5 22 BID I/O pin for parallel communication Strobe out clock for serial communication
Data clock output in direct mode
I/O_6 23 BID I/O pin for parallel communication MISO for serial communication (SPI)
Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0
I/O_7 24 BID I/O pin for parallel communication.
MOSI for serial communication (SPI)
EN2 25 INP Pulse enable and selection of power-down mode. If EN2 is connected to VIN, then VDD_X is active during power down to support the MCU. Pin can also be used for pulse wake up from
power-down mode.
DATA_CLK 26 INP Clock input for MCU communication (parallel and serial)
SYS_CLK 27 OUT Clock for MCU (3.39 / 6.78 / 13.56 MHz) at EN = 1 and EN2 = don't care
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN 28 INP Chip enable input (If EN = 0, then chip is in power-down mode.)
VSS_D 29 SUP Negative supply for internal digital circuits; normally connected to circuit ground
OSC_OUT 30 OUT Crystal oscillator output
OSC_IN 31 INP Crystal oscillator input
VDD_X 32 OUT Internally regulated supply (2.7 V to 3.4 V) for external circuitry (MCU)
Thermal Pad Connected to circuit ground

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Specifications Copyright © 2006–2017, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability or lifetime of the device.
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Supply voltage 6 V
IOOutput current 150 mA
TJMaximum junction temperature Any condition 140 °C
Continuous operation, long-term reliability(2) 125
Tstg Storage temperature range –55 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
5.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
Machine model (MM) ±200
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
VIN Supply voltage 2.7 5 5.5 V
TJOperating virtual junction temperature –40 125 °C
TAOperating ambient temperature –40 25 110 °C
5.4 Electrical Characteristics
TYP values at 25°C, MIN and MAX values over operating ambient temperature range, VS= 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPD Supply current in power-down
mode All systems disabled, including supply voltage regulators 1 10 µA
IPD2 Supply current in power-down
mode 2 The reference voltage generator and VDD_X remain active to support external circuitry. 120 300 µA
ISTBY Supply current in standby mode Oscillator running, supply voltage regulators in
low-consumption mode 1.5 4 mA
ION1 Supply current without antenna
driver current Oscillator, regulators, RX, and AGC are active, TX is off 10 16 mA
ION2 Supply current with antenna
driver current Oscillator, regulators, RX, AGC, and TX are active, Pout = 100 mW 70 mA
ION3 Supply current with antenna
driver current Oscillator, regulators, RX, AGC, and TX are all active, Pout = 200 mW 120 mA
BG Band-gap voltage Internal analog reference voltage 1.4 1.6 1.7 V
VPOR Power-on-reset (POR) voltage 1.4 2 2.5 V
VDD_A Regulated supply for analog
circuitry 3.1 3.5 3.8 V

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Electrical Characteristics (continued)
TYP values at 25°C, MIN and MAX values over operating ambient temperature range, VS= 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. The MISO driver has a typical
output resistance of 400 Ω(12-ns time constant when 30-pF load is used).
VDD_RF Regulated supply for RF circuitry Regulator set for 5-V system with 250-mV
difference 4 4.6 5.2 V
VDD_X Regulated supply for external
circuitry 3.1 3.4 3.8 V
PPSRR Rejection of external supply noise
on the supply VDD_RF regulator The difference between the external supply and
the regulated voltage is higher than 250 mV,
measured at 212 kHz 20 26 dB
RRFOUT PA driver output resistance Half-power mode 8 12 Ω
Full-power mode 4 6
RRFIN RX_IN1 and RX_IN2 input
resistance 5 10 20 kΩ
VRFIN Maximum input voltage At RX_IN1 and RX_IN2 inputs 3.5 VPP
VSENS Input sensitivity fSUBCARRIER = 424 kHz 1.2 2.5 mVPP
fSUBCARRIER = 848 kHz 1.2 3
tSET_PD Setup time after power down 10 20 ms
tSET_STBY Setup time after standby mode 30 100 µs
tREC Recovery time after modulation
(ISO/IEC 14443) Modulation signal: sine, 424 kHz, 10 mVpp 60 µs
fSYS_CLK SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 30 60 120 kHz
fD_CLKmax Maximum DATA_CLK frequency Depends on capacitive load on the I/O lines, TI
recommends 2 MHz(1) 2 4 8 MHz
CLKMAX Maximum CLK frequency 2 MHz
VIL Input logic low 0.2 ×
VDD_I/O 0.2 × VDD_I/O V
VIH Input logic high 0.8 ×
VDD_I/O V
ROUT Output resistance of I/O_0 to
I/O_7 low_io = H for VDD_I/O < 2.7 V 400 800 Ω
RSYS_CLK Output resistance of SYS_CLK low_io = H for VDD_I/O < 2.7 V 200 400 Ω
(1) This data was taken using the JEDEC standard high-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase
substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best
performance and long-term reliability.
5.5 Thermal Resistance Characteristics
PACKAGE RθJC
(°C/W) RθJA (1) (°C/W) POWER RATING(2)
TA≤25°C TA= 85°C
RHB (32) 31 36.4 2.7 W 1.1 W

3 (SPI) or 8 (Parallel)
Impedance
Matching
Circuit
TX_OUT
RX_IN1
RX_IN2
VDD_X
VDD_I/O
SYS_CLK
DATA_CLK
VCC
TRF796x MSP430 MCU
Crystal
13.56 MHz
IRQ
OSC_IN
OSC_OUT
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Detailed Description Copyright © 2006–2017, Texas Instruments Incorporated
6 Detailed Description
6.1 Overview
Figure 6-1 shows a typical application diagram for the TRF796x devices. A parallel or serial interface can
be implemented for communication between the MCU and reader. Transmit and receive functions use
internal encoders and decoders with a 12-byte FIFO register. For direct transmit or receive functions, the
encoders and decoders can be bypassed so the MCU can process the data in real time. The transmitter
has selectable output power levels of 100 mW (20 dBm) or 200 mW (23 dBm) into a 50-Ωload (5-V
supply) and supports ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise
rejection for the complete reader system.
Figure 6-1. Typical Application Diagram
Data transmission supports low-level encoding for ISO/IEC 15693, modified Miller for ISO/IEC 14443 A,
high-bit-rate systems for ISO/IEC 14443, and Tag-it coding systems. Included with the data encoding is
automatic generation of SOF, EOF, CRC, and parity bits.
The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also
includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to
cover a broad range of input subcarrier signal options. The received signal strength for AM and PM
modulation is accessible through the RSSI register. The receiver output is a digitized subcarrier signal
among a selectable protocol and bit rate as outlined in Table 6-13. A selected decoder delivers bit stream
and a data clock as outputs.
The receiver system also includes a framing system. This system performs a CRC or parity check,
removes the EOF and SOF settings, and organizes the data in bytes. Framed data is then accessible to
the MCU through a 12-byte FIFO register and MCU interface. The framing supports ISO/IEC 14443 and
ISO/IEC 15693 protocols.
The TRF796x supports data communication levels from 1.8 V to 5.5 V for the MCU I/O interface, while
also providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is available for
additional system circuits.
6.2 Power Supplies
The positive supply pin, VIN (pin 2), has an input voltage range of 2.7 V to 5.5 V. The positive supply input
sources three internal regulators with output voltages VDD_RF, VDD_A, and VDD_X that use external bypass
capacitors for supply noise filtering. These regulators provide enhanced PSRR for the RFID reader
system. Table 6-1 describes the power supplies.

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Detailed DescriptionCopyright © 2006–2017, Texas Instruments Incorporated
The regulators are not independent and have common control bits for output voltage setting. The
regulators can be configured to operate in either automatic or manual mode. The automatic regulator
mode setting ensures an optimal compromise between regulator PSRR and highest possible supply
voltage for RF output power. The manual mode allows the application to manually configure the regulator
settings.
Table 6-1. Power Supplies
SUPPLY DESCRIPTION
VDD_RF
The regulator VDD_RF (pin 3) is used to source the RF output stage. The voltage regulator can be set for either 5-V or 3-V
operation.
When configured for 5-V operation, the output voltage can be set from 4.3 V to 5 V in 100-mV steps. The current sourcing
capability for 5-V operation is 150 mA maximum over the adjusted output voltage range.
When configured for 3-V operation, the output voltage can be set from 2.7 V to 3.4 V, also in 100-mV steps. The current
sourcing capability for 3-V operation is 100 mA maximum over the adjusted output voltage range.
VDD_A
Regulator VDD_A (pin 1) supplies voltage to analog circuits within the reader chip. The voltage setting is divided in two ranges.
When configured for 5-V operation, the output voltage is fixed at 3.5 V. When configured for 3-V operation, the output voltage
can be set from 2.7 V to 3.4 V in 100-mV steps.
NOTE: The VDD_A and VDD_X regulators are configured together (their settings are not independent).
VDD_X
Regulator VDD_X (pin 32) can be used to source the digital I/O of the reader chip together with other external system
components. When configured for 5-V operation, the output voltage is fixed at 3.4 V. When configured for 3-V operation, the
output voltage can be set from 2.7 to 3.4 V in 100-mV steps.
The total current sourcing capability of the VDD_X regulator is 20 mA (maximum) over the adjusted output range.
NOTE: The VDD_A and VDD_X regulators are configured together (their settings are not independent).
VDD_PA The VDD_PA pin (pin 4) is the positive supply pin for the RF output stage and is externally connected to the regulator output
VDD_RF (pin 3).
6.2.1 Negative Supply Connections
The negative supply connections are all externally connected together (to GND). The substrate connection
is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic negative supply is VSS_D (pin 29),
the RF output stage negative supply is VSS_TX (pin 6), and the negative supply for the RF receiver input is
VSS_RX (pin 7).
6.2.2 Digital I/O Interface
To allow compatible I/O signal levels, the TRF796x has a separate supply input VDD_I/O (pin 16), with an
input voltage range of 1.8 V to 5.5 V. This pin supplies the I/O interface (I/O_0 to I/O_7), IRQ, SYS_CLK,
and DATA_CLK pins of the reader. In typical applications, VDD_I/O is connected directly to VDD_X to ensure
that the I/O signal levels of the MCU are the same as the internal logic levels of the reader.
6.2.3 Supply Regulator Configuration
The supply regulators can be automatically or manually configured by the control bits. Table 6-2 lists the
manual regulator settings for a 5-V system. Table 6-3 lists the manual regulator settings for a 3-V system.
Table 6-4 and Table 6-5 list the automatic mode gain settings for 5-V and 3-V systems, respectively.
The automatic mode is the default configuration. In automatic mode, the regulators are automatically set
every time the system is activated by asserting the EN input high. The internal regulators are also
automatically reconfigured every time the automatic regulator selection bit is set high (on the rising edge).

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The application can reset the automatic mode setting from a state in which the automatic setting bit is
already high by changing the automatic setting bit from high to low to high. The regulator-configuration
algorithm adjusts the regulator outputs 250 mV below the VIN level, but not higher than 5 V for VDD_RF, 3.5
V for VDD_A, and 3.4 V for VDD_X. This algorithm ensures the highest possible supply voltage for the RF
output stage while maintaining an adequate PSRR (power supply rejection ratio). As an example, the
application can improve the PSRR if there is a noisy supply voltage from VDD_X by increasing the target
voltage difference across the VDD_X regulator as listed for automatic regulator settings in Table 6-4 and
Table 6-5.
Table 6-2. Supply-Regulator Setting – Manual – 5-V System
BYTE
ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 B1 B0
0x00 1 5-V system
0x0B 0 Manual regulator setting
0x0B 0 1 1 1 VDD_RF = 5 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.5 V, VDD_X = 3.4 V
0x0B 0 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.5 V, VDD_X = 3.4 V
Table 6-3. Supply-Regulator Setting – Manual – 3-V System
BYTE
ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2 B1 B0
0x00 0 3-V system
0x0B 0 Manual regulator setting
0x0B 0 1 1 1 VDD_RF = 3.4 V, VDD_A, VDD_X = 3.4 V
0x0B 0 1 1 0 VDD_RF = 3.3 V, VDD_A, VDD_X = 3.3 V
0x0B 0 1 0 1 VDD_RF = 3.2 V, VDD_A, VDD_X = 3.2 V
0x0B 0 1 0 0 VDD_RF = 3.1 V, VDD_A, VDD_X = 3.1 V
0x0B 0 0 1 1 VDD_RF = 3.0 V, VDD_A, VDD_X = 3.0 V
0x0B 0 0 1 0 VDD_RF = 2.9 V, VDD_A, VDD_X = 2.9 V
0x0B 0 0 0 1 VDD_RF = 2.8 V, VDD_A, VDD_X = 2.8 V
0x0B 0 0 0 0 VDD_RF = 2.7 V, VDD_A, VDD_X = 2.7 V
(1) x = Don't care
Table 6-4. Supply-Regulator Setting – Automatic – 5-V System
BYTE
ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2(1) B1 B0
0x00 1 5-V system
0x0B 1 x 1 1 Automatic regulator setting; approximately 250-mV difference
0x0B 1 x 1 0 Automatic regulator setting; approximately 350-mV difference
0x0B 1 x 0 0 Automatic regulator setting; approximately 400-mV difference

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(1) x = Don't care
Table 6-5. Supply-Regulator Setting – Automatic – 3-V System
BYTE
ADDRESS OPTION BITS SETTING IN CONTROL REGISTER ACTION
B7 B6 B5 B4 B3 B2(1) B1 B0
0x00 0 3-V system
0x0B 1 x 1 1 Automatic regulator setting; approximately 250-mV difference
0x0B 1 x 1 0 Automatic regulator setting; approximately 350-mV difference
0x0B 1 x 0 0 Automatic regulator setting; approximately 400-mV difference
6.2.4 Power Modes
The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in
the Chip Status Control register (00h).
The main reader enable input is EN (which has a threshold level of 1 V [minimum]). Any input signal level
from 1.8 V to VIN can be used. When EN is set high, all of the reader regulators are enabled, together with
the 13.56-MHz oscillator, and the SYS_CLK output clock for an external MCU.
The auxiliary enable input EN2 has two functions:
• A direct connection from EN2 to VIN ensures availability of the regulated supply (VDD_X) and an
auxiliary clock signal (60 kHz) on the SYS_CLK output (same for the case EN = 0). This mode is
intended for systems in which the MCU controlling the reader is also being supplied by the reader
supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets
the MCU supply and clock be available during power down.
• EN2 enables start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case,
the EN input is controlled by the MCU or other system device that is without supply voltage during
complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input
(which has a 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to
condition EN = 1). This start-up mode lasts until all of the regulators have settled and the 13.56-MHz
oscillator has stabilized. If the EN input is set high by the MCU (or other system device), the reader
stays active. If the EN input is not set high within 100 µs after the SYS_CLK output is switched from
auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system
returns to a complete power-down mode. This option can be used to wake the reader system from
complete power down by using a push-button switch or by sending a single pulse.
After the reader EN line is high, the other power modes are selected by control bits. Table 6-6 lists the
power mode options and functions.

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Table 6-6. Power Modes
BYTE
ADDRESS
OPTION BITS SETTING IN CHIP STATUS CONTROL
REGISTER EN EN2 FUNCTIONALITY CURRENT
B7
stby B6 B5 rfon B4 B3 rf_pwr B2 B1 rec_on B0
0x00 0 0 Complete power down <1 µA
0x00 0 1 VDD_X available, SYS_CLK auxiliary frequency
60 kHz is ON 120 µA
0x00 1 x x x 1 x All supply regulators active and in
low power mode,
13.56-MHz oscillator on,
SYS_CLK clock available 1.5 mA
0x00 0 0 x 0 1 x All supply regulators active, 13.56-MHz oscillator on,
SYS_CLK clock available 3.5 mA
0x00 0 0 x 1 1 x All supply regulators active,
13.56-MHz oscillator on,
SYS_CLK clock available,
Receiver active 10 mA
0x00 0 1 1 x 1 x
All supply regulators active,
13.56-MHz oscillator on,
SYS_CLK clock available,
Receiver active,
Transmitter active in half-power
mode
70 mA
(at 5 V)
0x00 0 1 0 x 1 x
All supply regulators active,
13.56-MHz oscillator running,
SYS_CLK clock available,
Receiver active,
Transmitter active in full-power
mode
120 mA
(at 5 V)
During reader inactivity, the TRF796x can be placed in power-down mode (EN = 0). The power down can
be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) with the regulated
supply (VDD_X) and 60-kHz auxiliary clock (SYS_CLK) available to the MCU or other system device.
When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are
activated and the 13.56-MHz oscillator is started. When the supplies are settled and the oscillator
frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the
selected frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and
perform the required tasks. The control system (MCU) can then write appropriate bits to the Chip Status
Control register (address 0x00) and select the operation mode.
The standby mode (bit 7 = 1 in register 0x00) is the active mode with the lowest current consumption. The
reader can recover from this mode to full operation in 100 µs.
The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 in register 0x00) is the next active mode
with low power consumption. The reader is capable of recovering from this mode to full operation in 25 µs.
The active mode with only the RF receiver section active (bit 1 = 1 in register 0x00) can be used to
measure the external RF field (see Section 6.3.1) if reader-to-reader anticollision is implemented.
The active mode with the entire RF section active (bit 5 = 1 in register 0x00) is the normal mode used for
transmit and receive operations.
6.2.5 Timing Diagrams
Figure 6-2 shows an oscilloscope trace of chip power up.
Figure 6-3 shows an oscilloscope trace of chip enable to clock start with EN2 low and EN high.
Figure 6-4 shows an oscilloscope trace of chip enable to clock start with EN2 high and EN low.

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Figure 6-2. Chip Power Up [VIN (Blue) to Crystal Start (Red)]
Figure 6-3. Chip Enable to Clock Start, EN2 Low and EN High (Blue) to Start of System Clock (Red)

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Figure 6-4. Chip Enable to Clock Start, EN2 High and EN Low (Blue) to Start of System Clock (Red)
6.3 Receiver – Analog Section
The TRF796x has two receiver inputs, RX_IN1 (pin 8) and RX_IN2 (pin 9). The two inputs are connected
to an external filter to ensure that AM modulation from the tag is available on at least one of the two
inputs. The external filter provides a 45° phase shift for the RX_IN2 input to allow further processing of a
received PM-modulated signal (if it appears) from the tag. This architecture eliminates any possible
communication holes that may occur from the tag to the reader.
The two RX inputs are multiplexed to two receiver channels: the main receiver and the auxiliary receiver.
Receiver input multiplexing is controlled by control bit B3 (pm_on) in the Chip Status Control register
(address 0x00). The main receiver is composed of an RF-detection stage, gain, filtering with AGC, and a
digitizing stage whose output is connected to the digital processing block. The main receiver also has an
RSSI measuring stage, which measures the strength of the demodulated signal.
The primary function of the auxiliary receiver is to measure the RSSI of the modulation signal. It also has
similar RF-detection, gain, filtering with AGC, and RSSI blocks.
The default setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary
receiver (bit pm_on = 0). When a response from the tag is detected by the RSSI, values on both inputs
are measured and stored in the RSSI Level register (address 0x0F). The control system reads the RSSI
values and switches to the stronger receiver input (RX_IN1 or RX_IN2 by setting pm_on = 1).
The receiver input stage is an RF level detector. The RF amplitude level on RX_IN1 and RX_IN2 inputs
should be approximately 3 VPP for a VIN supply level greater than 3.3 V. If the VIN level is lower, the RF
input peak-to-peak voltage level should not exceed the VIN level. VIN is the main supply voltage to the
device at pin 2.
The first gain and filtering stage following the RF-envelope detector has a nominal gain of 15 dB with an
adjustable band-pass filter. The band-pass filter has adjustable 3-dB frequency steps (100 kHz to 400 kHz
for high pass and 600 kHz to 1500 kHz for low pass). Following the band-pass filter is another gain-and-
filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first stage.

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The internal filters are configured automatically, with internal presets for each new selection of a
communication standard in the ISO Control register (address 0x01). If required, additional fine-tuning can
be accomplished by writing directly to the RX Special Setting register (address 0x0A). Table 6-22 lists the
bits of the RX Special Settings register (address 0x0A) that control the receiver analog section.
6.3.1 Received Signal Strength Indicator (RSSI)
The RSSI measurement block measures the demodulated signal (except in the case of a direct command
for RF-amplitude measurement; see Section 6.5). The measuring system latches the peak value, so the
RSSI level can be read after the end of the receive packet. The RSSI register values reset with every
transmission by the reader. This allows an updated RSSI measurement for each new tag response.
Table 6-7 and Table 6-8 list the correlation between the RF input level and RSSI designation levels on
RX_IN1 and RX_IN2.
Table 6-7 compares the RSSI level and the RSSI bit value. The RSSI has seven levels (3 bits each) with
4-dB increments. The input level is the peak-to-peak modulation level of the RF signal as measured on
one side envelope (positive or negative).
Table 6-7. RSSI Level Versus Register Bit Value
RSSI1234567
Input level 2 mVpp 3.2 mVpp 5 mVpp 8 mVpp 13 mVpp 20 mVpp 32 mVpp
As an example, from Table 6-8, let B2 = 1, B1 = 1, B0 = 0. This yields an RSSI value of 6. From Table 6-7
a bit value of 6 indicates an RSSI level of 20 mVpp.
Table 6-8. RSSI Bit Value and Oscillator Status Register (0x0F)
BIT SIGNAL FUNCTION COMMENTS
B7 Unused
B6 osc_ok Crystal oscillator stable
B5 rssi_x2 Most significant bit (MSB) of auxiliary receiver RSSI 4 dB per stepB4 rssi_x1 Auxiliary receiver RSSI
B3 rssi_x1 Least significant bit (LSB) of auxiliary receiver RSSI
B2 rssi_2 MSB of main receiver RSSI 4 dB per stepB1 rssi_1 Main receiver RSSI
B0 rssi_0 LSB of main receiver RSSI
6.3.2 Receiver – Digital Section
The received subcarrier is digitized to form a digital representation of the modulated RF envelope. This
digitized signal is applied to digital decoders and framing circuits for further processing.
The digital part of the receiver consists of two sections, which partly overlap. The first section consists of
the bit decoders for the various protocols, and the second section consists of the framing logic. The bit
decoders convert the subcarrier coded signal to a bit stream and also to the data clock. Thus, the
subcarrier-coded signal is transformed to serial data, and the data clock is extracted. The decoder logic is
designed for maximum error tolerance. This enables the decoders to successfully decode even partly
corrupted (due to noise or interference) subcarrier signals.
In the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like
the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are
automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is
clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external
microcontroller system.

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The start of the receive operation (successfully received SOF) sets the flags in the IRQ Status register.
The end of the receive operation is indicated to the external system (MCU) by sending an interrupt request
(pin 13, IRQ). If the receive data packet is longer than 8 bytes, an interrupt is sent to the MCU when the
received data occupies 75% of the FIFO capacity to signal that the data should be removed from the
FIFO. Use the FIFO Status register (0x1C) to provide the number of bytes that should be clocked out
during the actual FIFO read.
If any error in data format, parity, or CRC is detected, the external system is notified of the error by an
interrupt-request pulse. The source condition of the interrupt-request pulse is available in the IRQ Status
register (address 0x0C) (see Table 6-24).
The ISO Control register (address 0x01) is the primary control for the digital part of the receiver. By writing
to this register, the application selects the protocol to be used. With each new write in this register, the
default presets are loaded in all related registers, so no further adjustments in other registers are typically
needed for proper operation.
Table 6-12 describes the coding of the ISO Control register. The TRF7961 does not include the
ISO/IEC 14443 functionality; therefore, the features and commands for this protocol are not functional for
the TRF7961.
The framing section also supports bit-collision detection as specified in ISO/IEC 14443 A and
ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ
Status register. For ISO/IEC 14443 A specifically, the position of the bit collision is written in two registers:
partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt Mask
register (0x0D) (bits B6 and B7). The collision position is presented as a sequential bit number, where the
count starts immediately after the start bit. For example, the collision in the first bit of the UID would give
the value 00 0001 0000 in the collision position registers. The count starts with 0, and the first 16 bits are
the command code and the NVB byte (the NVB byte is the number of valid bits).
The receive section also has two timers. The RX wait time timer is controlled by the value in the RX Wait
Time register (address 0x08). This timer defines the time after the end of the transmit operation in which
the receive decoders are not active (held in reset state). This prevents incorrect detections resulting from
transients following the transmit operation. The value of the RX Wait Time register defines this time in
increments of 9.44 µs. This register is preset at every write to ISO Control register (address 0x01)
according to the minimum tag-response time defined by each standard.
The RX no response timer is controlled by the RX No Response Wait Time register (address 0x07). This
timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If
there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ Status
Control register. This enables the external controller to be relieved of the task of detecting empty slots.
The wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically,
for every new protocol selection.
6.3.3 Transmitter
The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing, and RF output
stage.
6.3.3.1 Transmitter – Analog Section
The 13.56-MHz crystal oscillator (connected to pins 31 and 32) directly generates the RF for the RF output
stage. It also generates the clock signal for the digital section and the clock signal output on SYS_CLK
(pin 27), which can be used by an external MCU system.
During partial power-down mode (EN = 0, EN2 = 1), the frequency of SYS_CLK is 60 kHz. During normal
reader operation, SYS_CLK can be programmed by bits B4 and B5 in the Modulator and SYS_CLK
Control register (address 0x09); available clock frequencies are 13.56 MHz, 6.78 MHz, or 3.39 MHz.
Table 6-9 lists the recommendations for the reference crystal (HC49U).

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Table 6-9. Crystal Recommendations
PARAMETER SPECIFICATION
Frequency 13.560000 MHz
Mode of operation Fundamental
Type of resonance Parallel
Frequency tolerance ±20 ppm
Aging <5 ppm/year
Operation temperature range –40°C to 85°C
Equivalent series resistance 50 Ω, minimum
NOTE
The value of the two external shunt capacitors on the crystal oscillator is calculated based on
the specified load capacitance of the crystal. The external capacitors (connected to the OSC
pins 30 and 31), are calculated as two capacitors in series plus CS(the internal I/O
capacitance of the oscillator gate plus PCB stray capacitance). The stray capacitance (CS)
can be estimated at 5 ±2 pF (typical).
As an example, given a crystal with a required load capacitance (CL) of 18 pF,
CL= ((C1× C2) / (C1+ C2)) + CS
18 pF = ((27 pF × 27 pF) / (27 pF + 27 pF)) + 4.5 pF
From this example, 18-pF capacitors would be placed on pins 30 and 31 to ensure proper
crystal oscillator operation.
The transmit power level is selectable as either half power of 100 mW (20 dBm) or full power of 200 mW
(23 dBm) when configured for 5-V automatic operation. The transmit output impedance is 8 Ωwhen
configured for half power and 4 Ωwhen configured for full power. Selection of the transmit power level is
set by bit B4 (rf_pwr) in the Chip Status Control register (see Table 6-11). When configured for 3-V
automatic operation, the transmit power level is typically selectable as either 33 mW (15 dBm) in half-
power mode or 70 mW (18 dBm) in full-power mode (VDD_RF at 3.3 V). Lower operating voltages result
in reduced transmit power levels.
In typical operation, the transmit modulation is configured by the selected ISO Control register (address
0x01). External control of the transmit modulation is possible by setting the ISO Control register (address
0x01) to direct mode. While in direct mode, the transmit modulation is set by the ASK/OOK pin (pin 12).
External control of the modulation type is enabled by setting B6 = 1 (en_ook_p) in the Modulator and
SYS_CLK Control register (address 0x09). ASK modulation depth is controlled by bits B0, B1, and B2 in
the Modulator and SYS_CLK Control register (address 0x09). The range of the ASK modulation is 7% to
30%, or 100% (OOK).
Table 6-21 describes the coding of the Modulator and SYS_CLK Control register.
The length of the modulation pulse is defined by the protocol selected in the ISO Control register. With a
high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than
intended. For such cases, the modulation pulse length can be corrected by using the TX Pulse Length
register. If the register contains all zeros, then the pulse length is governed by the protocol selection. If the
register contains a value other than 00h, the pulse length is equal to the value of the register in 73.7-ns
increments. This means the range of adjustment is 73.7 ns to 18.8 µs.

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6.3.3.2 Transmitter – Digital Section
The digital portion of the transmitter is very similar to that of the receiver. Before beginning data
transmission, the FIFO should be cleared with a Reset command (0x0F). Data transmission is initiated
with a selected command (see Table 6-31). The MCU then commands the reader to do a continuous Write
command (3Dh, see Table 6-33) starting from register 1Dh. Data written into register 1Dh is the TX Length
Byte1 (upper and middle nibbles), while the following byte in register 1Eh is the TX Length Byte2 (lower
nibble and broken byte length). The TX byte length determines when the reader sends the EOF byte. After
the TX length bytes, FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data
transmission begins automatically after the first byte is written into the FIFO. The TX Length bytes and
FIFO can be loaded with a continuous-write command because the addresses are sequential.
If the data length is longer than the allowable size of the FIFO, the external system (MCU) is warned when
the majority of data from the FIFO has already been transmitted by sending an interrupt request with a
flag in the IRQ register signaling FIFO low or high status. The external system should respond by loading
the next data packet into the FIFO.
At the end of the transmit operation, the external system is notified by another interrupt request with a flag
in the IRQ register that signals the end of TX.
The TX Length register also supports incomplete bytes transmitted. The high 2 nibbles in register 0x1D
and the nibble composed of bits B4 to B7 in register 0x1E store the number of complete bytes to be
transmitted. Bit 0 (in register 0x1E) is a flag that signals the presence of additional bits to be transmitted
that do not form a complete byte. The number of bits are stored in bits B1 to B3 of the same register
(0x1E).
The protocol is selected by the ISO Control register (address 0x01), which also selects the receiver
protocol. As defined by the selected protocol, the reader automatically adds all the special signals, like
start of communication, end of communication, SOF, EOF, parity bits, and CRC bytes. The data is then
coded to the modulation pulse level and sent to the modulation control of the RF output stage. This means
that the external system is only required to load the FIFO with data, and all the low-level coding is done
automatically. Also, all registers used in transmission are automatically preset to the optimum value when
a new selection is entered into the ISO Control register.
Some protocols have options, and two registers are provided to select the TX protocol options. The first
register is ISO14443B TX Options (address 0x02). This register controls the SOF and EOF selection and
EGT (extra guard time) selection for the ISO/IEC 14443 B protocol (see Table 6-14)
The second register controls the ISO/IEC 14443 high-bit-rate options. This register enables the use of
different bit rates for RX and TX operations in the ISO/IEC 14443 high bit-rate protocol. Additionally, it also
selects the parity system for the ISO/IEC 14443 A high-bit-rate selection (see Table 6-15).
The transmit section also has a timer that can be used to start the transmit operation at a precise time
interval from a selected event. This is necessary if the tag requires a reply in an exact window of time
following the tag response. The TX timer uses two registers (addresses 0x04 and 0x05). In first register
(address 0x04), two bits (B7 and B6) define the trigger conditions. The remaining 6 bits are the upper bits
and the 8 bits in register address 0x05 are lower bits, which are preset to the counter. The increment is
590 ns and the range of this counter is from 590 ns to 9.7 ms. See Table 6-16 for the bit definitions
(trigger conditions).
6.3.4 Direct Mode
Direct mode supports two configurations:
Direct mode 0 (bit 6 = 0 in the ISO Control register) enables use of only the front-end functions of the
reader, bypassing the protocol implementation in the reader. For transmit functions, the application has
direct access to the transmit modulator through the MOD pin (pin 14). On the receive side, the application
has direct access to the subcarrier signal (digitized RF envelope signal) on I/O_6 (pin 23).